JP3490252B2 - Packet-multiplexed audio / video signal separation device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention receives an image signal, an audio signal and system control data which are data-compressed based on a digital compression encoding method such as MPEG and further packet-multiplexed. The present invention relates to a packet-multiplexed video / audio signal separating device that separates and extracts a signal and a sound signal, and extracts a necessary amount of system control data and analyzes the contents.

[0002]

2. Description of the Related Art When handling image signals and audio signals in digital satellite broadcasting, optical discs, etc., a compression coding method is widely used in which the signals are digitized and the information redundancy is reduced to compress the information amount. Has been. System control technology that transmits compressed and encoded image signals and audio signals (these are referred to as elements) and that outputs audio and displays images is described in, for example, "ITU-T Rec.
| ISO / IEC13818-1: 1994 Information technology −
Coding of moving pictures and associated audio −
Part 1: Systems "(commonly known as MPEG system). By using the above technique and packetizing the above elements for time division multiplexing, it is possible to transmit a plurality of sets (that is, programs) of an image and its accompanying audio through the same channel (program multiplexing).

In such an MPEG system, a program stream (PS: PS:
A Program Stream) packet and a Transport Stream (TS) packet are defined. An apparatus that receives a program multiplexed as a TS packet, separates a desired TS packet, and decodes and outputs an image signal and an audio signal is disclosed in, for example, Japanese Patent Laid-Open No. 7-1.
No. 70490 and Japanese Patent Laid-Open No. 8-275147.

FIG. 12 is a block diagram showing an example of such a conventional packet separating apparatus. 1 is a demodulating apparatus, 2 is a packet separating apparatus, 21 is a PID (packet ID) filter, and 22 is a program clock reference ( PC
R: Program Clock Reference) counter, 23 is PI
D table, 24 decoder I / F (interface), 25 bus I / F, 3 clock generator, 4 video decoder, 5 video decoder buffer, 6 audio decoder, 7 and 8 DAC (digital / digital) Analog converter, 9 is RAM (random access
Reference numeral 10 is a CPU (central processing unit), and 11 is a ROM (read only memory).

A program-multiplexed information signal is input in the form of a bit stream from a transmission medium such as cable television or satellite broadcasting or a recording medium such as an optical disk. This bit stream is an MPEG TS
An error correction code is added to the packet, and further transmission line modulation is performed. This input bit stream is subjected to demodulation and error correction processing in the demodulation device 1, and TS
The packet is supplied to the packet separation device 2. The packet demultiplexing device 2 demultiplexes and extracts a necessary TS packet in order to obtain a desired video / audio signal from the program-multiplexed TS packet and sends it to the subsequent stage.

Here, the structure of the TS packet will be described with reference to FIG.

In the figure, the TS packet is fixed length data of 188 bytes, and is alternately arranged with an error correction code of 16 bytes. Each TS packet is basically a 4-byte transport stream header (TS
Header) and a payload containing data to be transmitted, but an extension header called an adaptation field is inserted between the TS header and the payload as needed. In the 4-byte TS header, an identifier representing the attribute of the TS packet, that is, the packet ID (PID) is represented by 13 bits, and the adaptation field is used when the program is encoded. It is used to transfer information such as a program clock reference (PCR) which is time information necessary for recovering the system clock on the decoding side.

The payload can be roughly classified into that shown in FIG. 2A and that shown in FIG. 2B according to the content of the information to be transmitted.

In FIG. 2A, the payload is PES (Packet).
ized Elementary Stream: packetized elementary stream) shows a case where it is a part of a packet. This PES packet is composed of a PES header and a coded image signal or coded audio signal which is the content element of the program to be transmitted. The PES header also describes the type of the element, the PES packet length, and a time stamp (PTS: Packet Time Stamp) that describes the time at which each element should be displayed or output.
Etc. are included. The sequence of such PES packets is sequentially segmented, and each segment is stored in the payload of a different TS packet.

FIG. 2B shows a program-specific information (PSI) in which the payload is unique information for system control.
service information (SI: Service Infomatio), which is information peculiar to the service such as ion) and program information.
n) (Note that in the following, these information PSI, SI
Are collectively referred to as PSI / SI data). This PSI / SI data is tabulated for each unit called a section, and the payload is ex1.
As part of a long section shown as
It may include multiple sections shown as ex2. That is, the columns of such sections are sequentially divided, and each division is stored in the payload of a different TS packet. However, in the case of ex1, what is stored in the payload of each TS packet is a part of the section. And
In the case of ex2, there are multiple sections.

Further, as in the case of ex2, the head of the section does not always match the head of the payload. That is, an integral number of sections are not always stored in the payload. Therefore, when the beginning of the section is located in the middle of the payload, offset information (this is called a pointer field) from the last byte of the TS header or adaptation field to the beginning of the section in the payload is called payload field. It is written at the beginning of so that the beginning position of the section can be known.

In each section, in addition to the PSI / SI data that is the contents of the section, at the beginning of the section, a table ID indicating the table type of the section and a section length indicating the section length are described. A header and a Cyclic Redundancy Check (CRC) are included at the end of each section.

The PSI data has a hierarchical table structure, and a program map table (PMT: Program Map Table) that describes the correspondence between elements and PIDs (packet IDs) for each program (set of image and audio).
Or a program association table (PAT: Program Association) that describes the correspondence between these PMTs and PIDs.
etion Table) etc. are included.

When the TS packet to be transmitted is encrypted (scrambled), key information for descrambling the scramble is required. In such a case, the PSI is used for each program. Entitlement Control Message (ECM) that represents descramble information for each contract, and Entitlement Management Message (EMM) that represents key information for each contract subscriber.
ge) is also included. Further, when there are a plurality of scramble systems, the relation between the ECM and EMM corresponding to these scramble systems is represented by a conditional access table (CAT).
Described by.

As described above, each TS packet has the format shown in FIG.
Some have a payload containing an element as shown in (a), and some have a payload containing information for system control (system control data) as shown in FIG. 2B, and these have a PID. Can be determined. Further, in the TS packet having the system control data, the contents of each section can be identified by the section header.

Next, the packet separation device 2 in FIG. 2 will be described.

In the packet demultiplexing device 2, the PID of the TS packet storing the program to be decoded is stored in the PID table 23, and when the program-multiplexed TS packet is received from the demodulating device 1, the PID filter 21 receives this. When the PID of the TS packet and the PID stored in the PID table are compared, and the two match,
The TS packet at this time is extracted. This extracted T
The S packet includes elements included in the program to be decoded and PSI / SI data necessary for system control. The PID table 23 is written with necessary PIDs from the CPU 10 via the data bus and the bus I / F 25.

Among the TS packets extracted by the PID filter 21, those containing elementary data such as images and sounds are sequentially supplied to the decoder I / F 24 to remove the TS header and the adaptation field and the like. By writing and reading in the buffer, it becomes continuous data, which is supplied to the video decoder 4 and the audio decoder 6. The video decoder 4 uses the video decoding buffer 5, that is, the image information supplied discontinuously is sequentially written into the video decoding buffer 5 and read as continuous image information, and a digital image signal is decoded from this image information. The audio decoder 6 also uses a built-in buffer and similarly decodes a digital audio signal. The decoded digital image signal and digital audio signal are converted into analog image signals and audio signals by the DACs 7 and 8 at synchronized timings and supplied to a monitor and a speaker (not shown).

In addition, in the PID filter 21, when the extracted TS packet is provided with an adaptation field containing PCR information for recovering the system clock, the PCR information is extracted from this adaptation field. And supplies it to the PCR counter 22. The PCR counter 22 takes the difference between the internal counter information and the received PCR information, and supplies the obtained difference value to the clock generator 3. Therefore, the clock generator 3 controls the acceleration and deceleration of the system clock according to the received difference value and reproduces the system clock that follows the PCR information in the bit stream of the extracted TS packet.

On the other hand, the T extracted by the PID filter 21
The PSI / SI data of the S packet is transferred via the bus I / F 25, temporarily stored in the packet storage area in the RAM 9, and read by the CPU 10 to reconstruct the section. Of the reconfigured sections, only the information necessary for system control is extracted by the CPU 10 and held in another storage area in the RAM 9 again.
Information that is analyzed by the PU 10 and is necessary for system control is extracted. Then, the CPU 10 uses the extracted system control information to execute the system control program stored in the ROM 11, and the packet separation circuit 2
It controls the video decoder 4, the audio decoder 6, and the like.

Further, the CPU 10 uses the extracted PSI / S
The program information of I data is analyzed and graphic data is processed, and this is processed by an on-screen display (OSD).
Using the function, the video decoder 4 processes the program to display the program guide on the monitor.

[0022]

However, in the above-mentioned conventional technique, the PID filter 21 selects the PSI / SI data only by the PID filtering process and includes the selected PSI / SI data including those that do not require analysis. Since all SI data is transferred to the CPU 10,
The CPU 10 handles an extremely large amount of data processing amount for the filtering process, which may increase the load on the CPU 10 and reduce the processing time allocation time for other system processes.

For example, when receiving a scrambled pay digital satellite broadcast, the EMM data including the scramble key information for each contractor is different for each contracting subscriber who has a reception contract. Such different information is transmitted in the TS packet of the same PID. Therefore, which section corresponds to which contract subscriber is
It is determined by referring to the subscriber ID described in the section. Therefore, when such EMM data is sent to the CPU 10 only by PID filtering, the CP
The U10 needs to analyze the section data included in all the EMM data and select the section corresponding to his / her subscriber ID, and the amount of data to be processed becomes very large.

Further, regarding the SI including the program information, the program data sent is for one week,
The processing of extracting only the section related to a desired program from the program data also imposes a heavy load on the CPU 10.

As described above, when the PSI / SI data processing load increases, the CPU 10 allocation time for other system processing decreases, and as a result, the responsiveness to the processing for interfacing with the user deteriorates. Or
There is a problem that the complicated OSD display becomes slow.

The object of the present invention is to eliminate such a problem,
Reduces the processing load on PU PSI / SI data,
It is an object of the present invention to provide a packet-multiplexed video / audio signal separating device capable of improving responsiveness to an interface with a user.

[0027]

In order to achieve the above object, the present invention shares a processing means with a section filtering process and a PID filtering process for transmitting only a packet including a desired section. That is, the PID filtering process and the section filtering process share the means for detecting the match between the packet in the buffer and the preset table data in a time-division manner with a filter having a configuration similar to that of the conventional PID filter. , This reduces the amount of PSI / SI data sent to the CPU.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a packet-multiplexed video / audio signal separating apparatus according to the present invention, in which 26 is a PID / section filter, and 2 is a block diagram.
Reference numeral 7 denotes a PID / PSI table, parts corresponding to those in FIG.

In the figure, the TS packet from the demodulator 1 is supplied to the PID / section filter 26 in the packet separator 2 and the TS of the desired PID is obtained by the PID stored in the PID / PSI table 27.
The packet is extracted and supplied to the decoder I / F 24. The processing of this TS packet is the same as that of the conventional technique shown in FIG.

Of the input TS packets, P
PS extracted by the ID / section filter 26
The I / SI data is sent to and held in the RAM 9 via the bus I / F 25 and the CPU bus.

At this time, if the PSI / SI data contains a large amount of data unnecessary for system control, such as an EMM packet containing key information for each contract subscriber, as in the prior art shown in FIG. , PID filter 23 is used to extract PSI / SI data including such unnecessary data, and the entire PSI / SI data is processed by the CPU 10.

However, in this embodiment, the PID / section filter 26 refers to a part of the data of the section included in the TS packet corresponding to the PID specified by the PID / PSI table 27, and this is necessary. Information is determined in section units, and based on the result of the determination, only packets that include the necessary section are read through the bus I / F 25 and CPU bus.
Transfer to AM9.

The CPU 10 sends the PSI sent to the RAM 9
/ SI Reads the data, reconstructs the section, analyzes the data, and extracts the information required for system control. Then, the CPU 10 uses the extracted data to PID the packet to be extracted, such as PAT or PMT.
Alternatively, the section data is written in the table RAM 27 via the bus I / F 25, and according to the system control program stored in the ROM 11, the packet separation device 2, the video decoder 4, the audio decoder 6
Etc., and further, the PSI stored in the RAM 9
The program information is extracted from the / SI data, a program guide or the like is created by the OSD function, and is output to the monitor via the video decoder 4.

In such a system, the PS sent to the RAM 9
Of the I / SI data, unnecessary packets can be deleted by section filtering processing.
It is possible to reduce the amount of processing in the CPU 10 that is spent in analyzing SI data. This allows the CPU 1 to perform other processing such as user interface processing and OSD processing.
A large processing time of 0 can be assigned, and the responsiveness of the entire system can be improved.

FIG. 3 is a block diagram showing a specific example of the PID / section filter 26 and the PID / PSI table 27 shown in FIG. 1. 261 is a buffer I / F, 2
62 is a buffer RAM, 263 is a data parser, 264
Is a TS data register, 265 is a table data register, 266 is a coincidence detector, 267 is a filtering state controller, 268 is a data output switching circuit, 27
Reference numeral 1 is a PID / PSI table RAM, and 272 is a table RAM I / F.

In the figure, first, the buffer RAM 26
An access procedure to access No. 2 will be described.

The TS packet supplied to the PSI / section filter 26 is temporarily stored in the buffer RAM 262 via the buffer I / F 261. Buffer RAM
The data accumulated in 262 is read out via the buffer I / F 261 for filtering or data transfer to the CPU 10 (FIG. 1).

FIG. 4 is a timing chart showing this operation. In this embodiment, as shown in FIGS. 4A and 4B, it is assumed that the demodulation device 1 (FIG. 1) supplies a synchronization signal each time the TS packet sent to the buffer RAM 262 starts. , The TS packet has a length of 188 bytes, and the period of the 16-byte error correction code removed by the demodulator 1 is a free period.

The buffer RAM 262 stores packets n,
TS packets are continuously input like n + 1, n + 2, ... (where n is an arbitrary integer) (this is RA
M access a: FIG. 4 (c)). Each input TS
For the packet, the PSI / section filtering process is started together with the sync signal supplied at the start of input of the next TS packet (this is called RAM access b: FIG. 4D) until the next sync signal is supplied. To end. The TS packet, which has been determined by the PSI / section filtering process as to whether or not the data should be extracted, is further output to the data output switching circuit 268 via the buffer I / F 261 at the same time as the next synchronization signal after the filtering process. It is started (this is called RAM access c: FIG. 4E).

According to such an access method to the buffer RAM 262, three Ts are stored in the buffer RAM 262.
There will be S packets, but this buffer RA
As the capacity of M, it is sufficient to have a capacity of two TS packets. This will be described with reference to FIG.

FIG. 5 shows how data is occupied in the address space in the buffer RAM 262. The horizontal axis represents time, and the vertical axis represents the address of the buffer RAM 262. The hatched portion is valid data. Shows the portion occupied by.

In the figure, the address space of the buffer RAM 262 has two areas having the capacity of TS packets (areas of address spaces 0 to 187 and address spaces 188 to 37).
5 areas), TS packets are stored in one area, and PSI / section filtering processing is performed on the TS packet (RAM access b), and in the other area, PSI / section filtering processing is performed. The TS packet which has finished is read (RAM access c) and the TS packet which is newly input is written (RAM access a). For example, taking the third packet period from the left in FIG. 5 as an example, in the area of one address space 0 to 187, the packet (n + 1) is stored and the PSI / section filtering process is performed. In the area of the other address space 188 to 375, writing of a newly input packet (n + 2) and PS
Packet n after I / section filtering is completed
Is being read. The read packet n is output to the data output switching circuit 268. Then, in the next packet period, one address space 0
To 187 are written and read as described above, and the PSI / section filtering process of the TS packet stored in the other address space 188 to 375 is performed, and the TS packet is written every packet period. , The area for reading and the area for storing TS packets for PSI / section filtering processing are exchanged.

By the way, in general, the average transmission rate of TS data in a received satellite broadcast signal is 60 Mbit / sec.
(= 7.5 Mbytes / sec) or less, and the data rate input from the demodulator 1 to the packet separation circuit 2 is about the same. On the other hand, the system clock of the entire packet separation circuit 2 is defined by the MPEG system so that 27 MHz is used as a reference clock, and the TS data is transmitted by a transfer data line having a bit width of 32 bits (= 4 bytes). If it is read in synchronization with (i.e., read in 4 bytes in parallel), it will be about 27 x 4 = 108.
TS packet buffer RA at an average speed of M bytes / sec
It will be possible to output from M262.

Therefore, even if the average transmission rate of the received TS packets and the system clock are used, the RAM access in FIG. The write address of access a does not exceed the read address of RAM access c, and the address space of 1 TS packet capacity is
Can be shared for packet input and output.

FIG. 6 shows the buffer RAM 262 in FIG.
6 is a diagram showing a control for making the input / output speeds of the TS packet data average and keeping the access to the buffer RAM 262 constant during one TS packet period.

In FIG. 7A, the buffer I / F 26
1 is provided with a time slot generation circuit 2611. When the cycles in which the RAM access a, b, c can be performed are time slots a, b, c, respectively, the time slot generation circuit 2611 outputs these time slots a to c.
Are sequentially generated.

FIG. 6B shows such time slots a, b,
It is a figure which shows the generation | occurrence | production timing of c, By changing the time slot which generate | occur | produces for every 1 cycle of a system clock, RAM access ac can be allocated on average in the packet period. By assigning many cycles to the time slot b, PS
It speeds up the data access required for I / section filtering. Also, in the time slots a and c,
It is assigned once every four cycles of the system clock.
Therefore, the generation of the time slots a to c is repeated with four cycles of the system clock as a cycle.

The data input rate in the RAM access a was originally about 7.5 Mbytes / sec, and it was not necessary to access the buffer RAM 262 at 32 bits per cycle of the system clock. Even once in a cycle,
The writing speed to the buffer RAM 262 is not so affected. On the other hand, assuming that the RAM access c is once every four cycles of the system clock, the average output speed is 1/4 of the above-mentioned about 108 Mbytes / sec (= about 27 Mbytes / se).
c), but it is still sufficiently faster than the average write speed in RAM access c (about 7.5 Mbytes / sec), so as described above, TS packets are stored in the same address space area of the buffer RAM 262. Input and output can be mixed.

As described above, in this embodiment, 2
The data of three TS packets can be handled by using the buffer RAM 262 having the capacity of the TS packet, and the capacity of the buffer RAM 262 can be reduced, and the circuit scale and the cost can be reduced.

Returning to FIG. 3, the PSI / section filtering process will be described next.

As described with reference to FIG. 4, the buffer RAM 2
For the data accumulated in 62, the PS
The I / section filtering process starts, but for this reason, the data of the TS packet to be subjected to this filtering process is read from the buffer RAM 262 and sent to the data parser 263 via the buffer I / F 261. That is, when the PID / section filtering process is performed, the data necessary for the PSI / section filtering process is read from the TS packet in the buffer RAM 262 via the buffer I / F 261, and sent to the data parser 263. Of the data supplied to the data parser, only those that need to be detected for matching with the contents in the PID / PSI table RAM 271 are selected.
The TS data register 264 is rearranged in an appropriate order.
Stored in.

On the other hand, the reference data to be compared with the data stored in the TS data register 264 is PID / PS
I table RAM 271 to table RAM I / F 27
2 through the table data register 265
Stored in.

The data stored in the TS data register 264 and the table data register 265 is the coincidence detector 2
The data is read out to 66, and it is judged for each bit whether or not there is a match. When all the inspected bits match, the matching flag of "1" is sent to the filtering state controller 267. If the match flag is “1”, the filtering state controller 267
Determines the filtering state according to a preset processing flowchart, and determines this by the data parser 26.
3 and the coincidence detector 266 and the table RAM 27. This filtering state is analyzed, and the TS data and table data necessary for the next match determination are respectively processed as described above with the data parser 263 and the table RAM I / F2.
72 is read, and the coincidence detector 266 again detects the coincidence of a predetermined number of bits.

As a result of the PSI / section filtering process, the filtering state controller 267
When it is determined that the audio / video TS packet should be sent to the decoder I / F 24 (FIG. 1), the audio PID hit flag / video PID hit flag is sent to the data output switching circuit 268, and the CPU 10
When it is determined that the PID is the PID of the PSI / SI data to be sent to (FIG. 1) (hereinafter referred to as PSI / SI data / PID), the PSI / SI / PID hit flag is sent to the data output switching circuit 268.

The data output switching circuit 268 reflects each of the above hit flags at the time of data output in the next TS packet period read from the buffer RAM 262, and when the audio / video PID hit flag is "1", the buffer I / F 261. The TS packet read from the buffer RAM 262 is sent to the decoder I / F 24 (FIG. 1) via the, and when the PSI / SI / PID hit flag is “1”, the TS packet read in the same manner is transferred to the bus I / F 25.
Transfer to RAM 9 (FIG. 1) via (FIG. 1). If none of these hit flags is "1", the data read from the buffer RAM 262 is discarded.

As shown in FIG. 7, the PID / PSI table RAM 271 is provided with 32 PID tables. Of these, PSI / SI / PID other than PCR, video and audio PIDs are further provided. ,
A 12-byte section data table (section data table) used in the section filtering process is provided for each section filtering process. The number of section data M for each PSI / SI / PID is arbitrary, but the maximum number of section data in this section data table is 32.
Up to individual pieces.

FIG. 8 is a diagram showing a specific example of a memory map in the PID / PSI table RAM 271 including the above PID table and section data table.

In the figure, the PID / PSI table R
In AM271, PID is assigned to addresses H (0000) to H (003E).
A table is stored (however, H () represents hexadecimal), and a section data table is stored at addresses H (007A) to H (003E). Also, the address H (004
0) to H (0078) are PSI / SI in the PID table.
The data indicating the relationship between the PID and the section data in the section data table is stored. Specifically, the start number (address) and the end number of the section data assigned to each PID are stored together ( For example, regarding the section data No. 1 to No. M for PSI / SI / PID of PID No. 3, the start address in the PID / PSI table RAM 271 is H (007A), and the start address is H (0040A). And end address (not shown) are stored).

The data stored in the PID / PSI table RAM 271 is the table RAMI.
It is written by reflecting the result of the CPU 10 analyzing the system control data via / F272. This allows
PID of data required for CPU 10 to control the system
You can specify the data to determine whether the data is needed or not for each section with the or section filter.

Next, referring to FIG. 9, PID /
The section filtering process will be described.

After the resetting, when the filtering process becomes possible, the PID / section filter 26 is in a waiting state for detecting the sync signal from the demodulator 1 (step 10).
0). When the synchronization signal is detected, the PID hit flags generated at the previous TS packet are cleared (step 101).

Thereafter, the PID hits are detected (step 102). In this PID hit detection,
Matching detection is performed for all 32 PID tables shown in FIG. 7, and a matching detection flag indicating the result is filtered for each PID by the filtering state controller 267.
Hold in.

Here, as a result of matching detection of 32 PID tables, time information PC for system clock recovery
When the PID held in the TS data register 264 matches the PID including R (PCR / PID) (step 103), the PCR / PID hit flag is set to "1". As a result, the PCR counter 22 (FIG. 1) reads the time information PCR in the adaptation field (FIG. 2A) held in the TS data register 264, and controls the clock generator 3 as described above. (Step 104).

When the PID held in the TS data register 264 matches the audio / video PID (FIG. 7) in the PID table read from the PSI / SI table RAM 271 held in the table data register. (Steps 105 and 107), the audio PID hit flag and the video PID hit flag are set to "1" and sent to the data output switching circuit 268 (steps 106 and 108), the filtering process is ended and the process returns to step 100, Wait until the sync signal is detected.

PI of PSI / SI table RAM 271
If there is no PID matching the PID held in the TS data register 264 in the D table (FIG. 7) (step 109), the filtering process is terminated and the process returns to step 100. Even if such a PID exists, the section If filtering is not needed (step 110),
The PID / SI / PID hit flag is set to "1" to end the filtering process, and the process returns to step 100.

PI of PSI / SI table RAM 271
PSI / SI.D of the D table (FIG. 7). The PID matches the PID held in the TS data register 264 (step 109), and there is section data (FIG. 7) for this PSI / SI / PID. When the section filtering process is necessary for the TS packet (step 110), the last TS packet having the same PID as the PID held in the TS data register 264 should be extracted in the previous TS packet filtering process. The continuation flag indicating that the section was in the middle is confirmed (step 112). When the continuation flag is "1", the TS packet is not subjected to the section filtering process,
The necessary sections will be included, and PSI / SI / P will be included.
The ID hit flag is set to "1" (step 113). In this case, in order to check whether or not the continuation flag is set to "1" for the current TS packet, the process proceeds to step 114 in the subsequent stage.

That is, first, the range (start number and end number) in the section data table (FIG. 7) of the section data for the PSI / SI.PID that matches the PID held in the TS data register 264 is loaded ( (Step 114), section filtering is performed for each section (FIG. 2B) included in the TS packet of this PID (Steps 115 to 118). For each section included in this TS packet, M section data within the loaded range are sequentially loaded to determine whether or not there is a section hit. If there is a section hit, PSI / The SI / PID hit flag is set to "1".

When the section filtering process is performed on the section included in this TS packet (step 118), it is determined whether the last section needs to be extracted and continues to the next and subsequent TS packets (step 118). 119), if it continues, the continuation flag is set to "1" (step 120), otherwise it is set to "0" (step 121).

In the above processing operation, as the PSI / section filtering processing, as shown in FIG.
A process of comparing PIDs and a process of comparing section data are performed. Details of the timing of the comparison processing are shown in FIGS. 10B and 10C.

FIG. 10B shows the TS data register 264 and the table data register 2 when comparing PIDs.
1 and 65 and the coincidence detector 266 are shown in units of system clock cycles.
0 (c) indicates processing in units of system clock cycles in the TS data register 264, the table data register 265, and the coincidence detector 266 when comparing section data.

In the case of comparing PIDs in FIG. 10B, first, the TS header including the PID of the TS packet (FIG. 2) is loaded into the TS data register 264 in two cycles of the system clock. In the next 4 cycles, the adaptation field (Fig. 2) of this TS packet is loaded. Then, these TS header and adaptation field are held as they are. Next 1
P in the PID / PSI table RAM 271 by cycle
PIDNO.0 of the ID table (FIG. 7) is loaded into the table data register 265, and in the next one cycle, PIDNO.0 and the PID of the TS data register 264.
At the same time, the values of and are taken into the coincidence detector 266 for coincidence detection, and at the same time, the next PID No. 1 in the PID table is loaded into the table data register 265. And
In the next cycle, this PIDNO.1 and the PID of the TS data register 264 are taken into the coincidence detector 266 to detect coincidence, and at the same time, the next PIDNO.2 of the PID table is loaded into the table data register 265. To be done. Hereinafter, this operation is repeated until there is a PID hit.

Further, in the case of comparing section data with each other in FIG. 10C, the buffer RAM 2 is stored in the TS data register 264 in 6 cycles of the system clock.
The data of one section read from 62 is loaded, and the PI is loaded into the table data register 265.
First section data No. 0 read from the section data table of the D / PSI table RAM 271
To load. The TS data register 264 holds the loaded section data as it is. Next 6
In the first cycle, the section data of the TS data register 264 and the section data No. 0 of the table data register 265 are taken into the coincidence detector 266 for coincidence detection, and the PID is detected in these 6 cycles. / PSI table RAM2
The next section data No. 1 read from the section data table 71 is stored in the table data register 26.
Load to 4. Thereafter, in the same manner, the TS data register 264 is set in units of 6 system clock cycles.
And the section data of the table data register 265 are detected by the coincidence detector 266, and the section data of the section data table is loaded into the table data register 265.

In this way, the TS data register 26
When the section filtering processing of one section data in 4 is completed, the same T
The next section data of the S packet is read and TS
The data is loaded into the data register 264 and the above section filtering process is repeated.

As described above, in this embodiment, the PID
The TS data register 264, the table data register 265, and the coincidence detector 266 are shared in a time-sharing manner for comparison between each other and comparison between section data.
PID / section filtering is realized by the same device by simply adding a small-scale circuit to the PID filter used conventionally.

Next, a second embodiment of the packet-multiplexed video / audio signal separating apparatus according to the present invention will be described. However, the circuit configuration and PID filtering of the second embodiment are the same as those of the first embodiment.

In the first embodiment, the number of sections in the TS packet containing PSI / SI data is such that PID / section filtering is possible within one TS packet transmission period, and is referred to by the PID / section filter 26. The operation of the section filter was not guaranteed when there is a restriction that the section data to be stored does not extend between TS packets. However, according to the MPEG standard and the like, there is no limitation on the number of sections in one TS packet, and it is allowed to arbitrarily set the section breaks. This second embodiment is
This is to cope with such a case.

FIG. 11 is a flow chart showing the main part of the section filtering process of the second embodiment, and shows the process after the processes of steps 112 and 113 in FIG.

In the figure, the TS packet is a PS that requires section filtering processing in step 110 of FIG.
When it is determined that the I / SI data is included, step 112 in FIG.
Or after the processing of 113 is performed, the start number and the end number of the section table to be referenced shown in FIG. 8 are read from the PID / PSI table RAM 271 (step
200).

At this point, the number M of section data in the section table to be referred to per section is known. Further, as shown in FIG. 10C, the system clock requires 6 cycles to load each section data from the section table (a match detector 266 performs the match detection in one of these cycles). Since one cycle is required to detect the matching of the last section data, an extra cycle is added to the section data and the cycle required for the section filtering process on the section data loaded in the TS data register 264 is performed. The number is 6 × M + 1 + 1 = 6 × M + 2. In this case, as described with reference to FIG. 6, the time slot b for the section filtering process can be accessed once every two cycles of the system clock.

Therefore, assuming that the input TS packet is 8-bit parallel data, the transmission rate is 7.5 Mbytes / sec, and the system clock is 27 MHz, the TS packet is as described in FIG. With a transmission rate of 7.5 Mbytes / sec, 204 cycles (= 18
PID from demodulator 1 at a cycle of 8 bytes + 16 bytes)
Since it is sent to the section filter 26, this period is 204 / (7.5 × 10 ⁶ ) = 27.2 μsec. For this purpose, the PID / section filter 26
Needs to process 1 TS packet by the system clock within the period of 27.2 μsec. This period corresponds to 27 × 10 ⁶ × 27.2 = approximately 734 cycles with a system clock of 27 MHz. That is, one TS packet must be processed in the period of about 734 cycles by the system clock of 27 MHz.

Therefore, the PID / PSI table RAM2
Assuming that the PID table stored in 71 has 32 PIDs as shown in FIG.
From the description in (b), the number of cycles required for PID filtering using such a PID table is 2 + 4 + 32 (= load count) +1 (= match detection of PIDNO.31) +1 ( (Extra) = 40 cycles, and if c is the number of cycles required for processing other than such PID / section filtering, then TS
Maximum PID / section filtering per packet (ie maximum number of allowed sections)
It is sufficient for Nmax to satisfy 40 + c + (6 × M + 2) × Nmax <734 (1). In this equation (1),
If the section data M is determined, the maximum allowable section number Nmax can be uniquely obtained. Therefore, by providing the filtering state controller 267 with a table ROM storing a table showing the correspondence relationship between the section data number M in the section data table and the maximum allowable section number Nmax of the TS packet, the maximum allowable section number Nmax can be easily set. Obtainable.

In this way, in FIG. 11, step 201 determines the maximum allowable section number Nmax in this way. When the maximum allowable section number Nmax is obtained,
As described in 0 (c), the TS data register 264
Section data is loaded into (step 202). When this section data is completed and does not extend to the next TS packet (step 203), steps 204 and 205
Thus, similar to steps 116 and 117 in FIG. 9, section filtering of the loaded section data by the section data table (FIG. 7) is performed,
If there is a next section in the same TS packet (step
206), unless the number of sections that have been section-filtered so far exceeds the maximum allowable section number Nmax (step 208), the processing from step 202 is repeated for the next section data.

When the section filtering processing of all the sections of the TS packet at this time is completed (step 206), as in steps 119 to 121 in FIG.
In the processing of steps 207, 211 and 212, the continuation flag is set to "1" or "0" and the process returns to step 100 of FIG.
Prepare for packet PID / section filtering.

If the number of section-filtered sections exceeds the maximum allowable number of sections Nmax (step 208), the section filtering processing for the subsequent sections is canceled and PSI / P is performed.
The ID hit flag is set to "1" (step 210), the section data of this TS packet is sent to the CPU 10 (FIG. 1) as described in FIG. 3, and the continuation flag of the PID of this TS packet is set. After setting it to "1" (step 211), the process returns to step 100 of FIG. 9 to prepare for the PID / section filtering process of the next TS packet. As a result, even if the data necessary for system control is included in the section that is not subjected to the section filtering process, the TS packet is transferred to the CPU 10, so that this data can be analyzed. Even if the section that is not subjected to the section filtering process does not contain the necessary data, such a section is ignored during the analysis of the CPU 10, so that there is no problem.

Further, in this case, the continuation flag is set to 1 even if the section which is not subjected to the section filtering process extends across the TS packets.
This is because it is transferred to 0. Further, even if the section to be extracted does not extend between TS packets, only the next TS packet of the same PID is transferred to the CPU and is also ignored during analysis.

By adding the above processing, it is possible to prevent a section required for the CPU 10 from being omitted without complicating the circuit configuration.

Next, when the data part to be section-filtered in the loaded section is also included in the next TS packet and thereafter, the section filtering process for that section is not completed (step 20).
3) About the data up to this halfway loaded, M
If there is a hit in each section data (step 20
9), CP with PSI / PID hit flag set to "1"
Transfer to U10 (step 210),
The continuation flag is set to "1" and the process returns to step 100 in FIG.
If there is no hit in the M section data (step 209), the continuation flag is set to "0" and the process returns to step 100 in FIG.

As a result, even if the data of the section to be section-filtered continues to the next TS packet, the CPU 1 determines that the data should be extracted.
Can be transferred to 0. At the same time, by setting the continuation flag to "1", subsequent TS packets having the same PID can also be transferred to the CPU 10. Even if this transferred section should not be extracted, CPU1
Since it is ignored during the analysis of 0, no failure occurs in the processing of the system.

In general, the above cases occur at an exceptional frequency, and the amount of unnecessary data transferred to the CPU 10 is small. Therefore, the influence on other processing is small, and it is possible to prevent the system control data from being missed.

[0091]

As described above, according to the present invention,
The same filter circuit can be commonly used for PID filtering and section filtering without increasing the circuit scale of the conventional PID filter provided in the packet separating circuit, thereby reducing the processing amount for CPU filtering. , A margin to other processing can be secured.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a packet-multiplexed video / audio signal separation device according to the present invention.

FIG. 2 is a diagram showing an internal structure of a packet according to MPEG.

FIG. 3 is a block diagram showing a specific example of a PID / section filter in FIG.

FIG. 4 is a buffer I / F and a buffer RAM in FIG.
6 is a timing chart showing the operation of FIG.

5 is a diagram showing a data occupation state for each packet period in the buffer RAM in FIG.

6 is a timing diagram showing an operation of a buffer I / F in FIG.

7 is a diagram showing a specific example of a table stored in a PID / PSI table RAM in FIG.

FIG. 8 is a memory map diagram of a PID / PSI table RAM having the table shown in FIG.

9 is a schematic diagram of P of the PID / section filter shown in FIG.
It is a flow chart which shows ID / section filtering processing.

10 is a timing diagram showing a PID / section filtering process of the PID / section filter shown in FIG.

FIG. 11 is a flowchart showing a main part of a section filtering process in the device for separating a packet and other purified image and audio signals according to the present invention.

FIG. 12 is a block diagram showing an example of a conventional packet-multiplexed video / audio signal separation device.

[Explanation of symbols]

1 Demodulator 2 Packet separation device 3 clock generator 4 video decoder 5 Video decoder buffer 6 audio decoder 7,8 Digital / Analog converter 9 RAM 10 CPU 11 ROM 22 PCR counter 24 Decoder I / F 25 bus I / F 26 PID / Section Filter 27 PID / PSI table 261 Buffer I / F 262 buffer RAM 263 Data Parser 264 TS data register 265 table data register 266 coincidence detector 267 Filtering State Controller 268 data output switching circuit 271 PID / PSI table RAM 272 table RAM I / F 2611 time slot generation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hisao Oku, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Multimedia System Development Division (72) Yukio Fujii 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address Hitachi Co., Ltd. Multimedia System Development Headquarters (72) Inventor Toshihisa Oishi 5-22-1, Josuihoncho, Kodaira-shi, Tokyo In-house Hitachi Microcomputer System Co., Ltd. (72) Kazuyuki Takada Josui, Kodaira, Tokyo 5-22 Hommachi, Hitachi Microcomputer System Co., Ltd. (56) References JP-A-8-275151 (JP, A) JP-A-9-182049 (JP, A) (58) Fields investigated (Int.Cl . ⁷ , DB name) H04N ^7/ 00-7/10 H04N ^7/ 12-7/173 H04N ^7/ 20-7/68

Claims (6)

(57) [Claims] 1. A plurality of sets of compression-coded image data and audio data associated with the image data, and system control data tabulated for each section of a predetermined format are packetized, and further. A multiplexed bitstream is input, a set of image data and audio data accompanying the image data are separated and extracted from the bitstream, and system control data is extracted and analyzed from the bitstream. In a packet-multiplexed video / audio signal separation device, a buffer memory for temporarily storing the input bitstream, a packet which is a part of the bitstream is read from the buffer memory, and data of the packet is read. A packet identifier described in a fixed position of the packet to represent the type A PID filter for extracting all PIDs, performing a PID filtering process for detecting a match between the PID and the first reference data set in advance, and extracting the packet of the matched PID; Regarding the packet having the system control data among the extracted packets, a part of the section of the packet is further read from the buffer memory to perform a match detection with preset second reference data, and a match is made. Section filter for performing a section filtering process for extracting the packet including the section, a packet storage memory for storing the packet including the system control data extracted by the section filtering process, and a section for storing the packet from the storage memory. System control data And a processor for controlling the system by reading out the packet, extracting a section required for system control from the system control data in the packet, analyzing the contents, and the PID filter and the section. A means for detecting coincidence with a filter is shared by time division, and the PI is
A packet-multiplexed video and audio, characterized in that a D filter detects a match between the PID and the first reference data, and the section filter detects a match between the section and the second reference data. Signal separation device. 2. The start of the PID filtering process for a packet n, which is the n-th packet (where n is an integer), according to claim 1,
The packet (n + 1) next to the packet n is synchronized with the timing at which the packet is started to be input to the buffer memory, and
The PID filtering process and the section filtering process for the packet n are performed on the packet (n
A packet-multiplexed video / audio signal separating apparatus comprising means for ending the packet (n + 2) subsequent to (+1) by the time the input to the buffer memory is started. 3. The buffer memory according to claim 2, wherein the buffer memory has a memory capacity for two packets, and the memory capacity is divided into two address spaces by one memory capacity for the packet. The PID filtering process and the section filtering process are performed on the packet n stored in any one of the address spaces, and the PI is used in the other address space in the one address space.
The packet (n + 1) that is the same as the output of the packet (n-1) that is one packet before the packet n that has been subjected to the D filtering process and the section filtering process.
And the address space for performing the PID filtering processing and the section filtering processing of the packet and the address space for inputting / outputting the packet are switched for each packet period. Separation device for multiplexed audiovisual signals. 4. The cycle according to claim 2, wherein a cycle for inputting / outputting data to / from the buffer memory is a first cycle that allows the packet to be input to the buffer memory, and a PID filtering process from the buffer memory. A second cycle that allows reading of data for the section filtering process is distinguished from a third cycle that reads data for transferring data from the buffer memory to the packet storage memory, and From the timing at which the packet n starts to be input to the buffer memory, the packet (n
Packet-multiplexed video / audio signal, characterized in that the first cycle, the second cycle, and the third cycle are switched in a fixed order every cycle until just before (+1) is started to be input. Separation device. 5. The packet n according to claim 2, wherein the packet n to be subjected to the section filtering process includes a plurality of sections, and the section filter is configured to start inputting the packet (n + 1) into the buffer memory. At the time when the section filtering process is terminated, if there is a section in the packet n that has not been determined by the section filtering process, it is presumed that the packet n is a packet to be extracted and the packet n is extracted. A packet-multiplexed video / audio signal separation device characterized by transferring to a storage memory. 6. The section filtering process according to claim 2, wherein the section filter has one section to be subjected to a section filtering process across the packet n and the subsequent packet. Then, if it is not possible to determine whether or not this packet n should be extracted, it is presumed that the section extending over two or more packets has necessary data as system control data, and the packet n is transferred to the packet storage memory. A packet-multiplexed video / audio signal separating device.