JP3489252B2 - Test data generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test data generator, and more particularly to a test data generator suitable for testing a device for decoding digital data including video data encoded by the MPEG system.

[0002]

2. Description of the Related Art As a device for transmitting video data and audio data via a broadcasting satellite or a communication satellite and receiving and demodulating the data at a receiving device, an IRD (Int.
rgrated Receiver / Decoder)
It has been known. In this IRD, the received data is decoded and supplied to the monitor device for display.

In the process of manufacturing these devices, it is necessary to supply test data to the receiving device to actually perform the decoding operation in order to check whether the device normally operates.

Also, in the process of developing the control program for the receiver, test data is needed to check whether the input signal is decoded correctly.

Conventionally, as the test data, data actually broadcast is received and used as the test data, or, for example, an encoder for broadcasting is used and the data output from the encoder is used as the test data. I was trying to use it.

[0006]

However, the method of receiving the data actually broadcast and using this as the test data does not always obtain the data suitable for the purpose of the test. There was a problem that a sufficient inspection could not be performed. Further, the reception state is not constant due to the weather, weather conditions, satellite position, etc., so that there is a problem that the test data cannot be stably supplied.

Further, when an encoder is used, the encoder itself is large-scaled and expensive, so that it is difficult to prepare a large number of units for inspection or program development. It was

The present invention has been made in view of such circumstances, and it is possible to easily and surely provide desired test data.

[0009]

A test data generator according to the present invention comprises first storage means for storing MPEG-encoded video data and audio data.
It is characterized by comprising a second storage means for storing the electronic program guide data, and an output means for packetizing the data stored in the first storage means and the second storage means and outputting it as test data. .

[0010]

In the test data generator having the above structure,
The first storage means stores video data and audio data encoded by the MPEG system, and the second storage means stores electronic program guide data. The output means packetizes these data and outputs them as test data.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG.
The structural example of a V (Audio Video) system is shown. In the case of this embodiment, the AV system 1 is composed of an IRD 2 for demodulating a signal received by a parabolic antenna 3 via a satellite (broadcast satellite or communication satellite) not shown, and a monitor device 4. Monitor device 4 and IRD
2 are connected to each other by an AV line 11 and a control line 12.

For the IRD 2, the remote commander 5
It is possible to input an instruction by an infrared (IR: Infrared) signal. That is,
When a predetermined one of the button switches of the remote commander 5 is operated, an infrared signal corresponding to the button is transmitted to the IR transmitter 51.
And is incident on the IR receiver 39 (FIG. 4) of the IRD 2.

FIG. 2 shows an electrical connection state of the AV system 1 of FIG. The parabolic antenna 3 is an LNB
(Low Noise Block downconv
The signal from the satellite is converted into an IF signal having a predetermined frequency (950 MHz to 1450 MHz) and supplied to the IRD 2. The IRD 2 outputs its output to, for example, a composite video signal line or an audio L.
The signal is supplied to the monitor device 4 via an AV line 11 composed of three lines of a signal line and an audio R signal line.

Further, the IRD 2 has an AV device control signal transmission / reception unit 2A, and the monitor device 4 has an AV device control signal transmission / reception unit 4A. These are wired S
IRCS (Wired Sony Infrared)
They are connected to each other by a control line 12 composed of a Remote Control System.

FIG. 3 shows an example of the front structure of the IRD 2. On the left side of IRD2 is the power button switch 111
Is provided. This power button switch 111 is
Operated when turning the power on or off. The LED 112 lights up when the power is turned on. LEDs 113 and 114 are provided on the right side of the LED 112, and the LED 113 lights up when the DSS mode in which a signal from a satellite is received and output is selected, and, for example, an RF signal input from a cable box to an RF input terminal, It is turned off when the television (TV) mode in which the output from the RF output terminal is performed via the RF modulator 41 (FIG. 4) is selected. The LED 114 is adapted to turn on when a predetermined message is transmitted to the IRD 2 via the satellite. When the user outputs and displays this message on the monitor device 4 and confirms it, the LED 114 is turned off.

When the TV / DSS button switch 115 is turned on, the DSS mode is set, and when it is turned off, the TV mode is set. Also, the menu button switch 121
Is operated when the menu is displayed on the monitor device 4.

An up button switch 117, a down button switch 118, a left button switch 119 and a right button switch 120 are arranged on the upper, lower, left and right sides of the select button switch 116, respectively. The up button switch 117, the down button switch 118, the left button switch 119, and the right button switch 120 are operated when moving the cursor in the vertical and horizontal directions. Also, select button switch 1
16 is operated when confirming the selection (when selecting).

FIG. 4 shows an example of the internal structure of the IRD 2 for receiving a signal in the above-mentioned DSS mode. R output from the LNB 3a of the parabolic antenna 3
The F signal is supplied to the tuner 21 of the front end 20 and demodulated. The output of the tuner 21 is supplied to the QPSK demodulation circuit 22 and QPSK demodulated. The output of the QPSK demodulation circuit 22 is supplied to the error correction circuit 23,
Errors are detected and corrected using convolutional codes and Reed-Solomon codes, and corrected as needed.

I consisting of CPU, ROM, RAM, etc.
CAM (Conditi) composed of C card
The key required for deciphering the cipher is stored in the onal access module 33 together with the deciphering program. If the signal transmitted via the satellite is encrypted, a key and a decryption process are required to decrypt this encryption. Therefore, this key is read from the CAM 33 via the card reader interface 32,
It is supplied to the demultiplexer (transport block) 24. The demultiplexer 24 uses this key to decrypt the encrypted signal.

The CAM 33 also stores billing information and the like in addition to the key and the decryption program necessary for decryption.

The demultiplexer 24 receives the signal output from the error correction circuit 23 of the front end 20 and outputs it to a data buffer memory (SRAM: Stat).
icRandom Access Memory) 35
Make it remember once. Then, this is read out as appropriate, the decoded video signal is supplied to the MPEG video decoder 25, and the decoded audio signal is supplied to the MPEG audio decoder 26.

The MPEG video decoder 25 appropriately stores the input digital video signal in the DRAM 25a and executes the decoding process of the video signal compressed by the MPEG2 system. The decoded video signal is supplied to the NTSC encoder 27 and converted into a luminance signal (Y), a chroma signal (C), and a composite signal (V) of the NTSC system. The luminance signal and the chroma signal are output as S video signals via the buffer amplifiers 28Y and 28C, respectively. Further, the composite signal is output via the buffer amplifier 28V.

As the MPEG video decoder 25, SGS-Thomson Microselect is used.
tronics MPEG2 decoding LSI (STi35
00) can be used. The outline is, for example, “Nikkei Electronics” 1994. 3.14, Nikkei BP.
(No. 603) pp. 101-110, Mart.
Introduced by Mr. in Bolton.

Also, MPEG2-Transports
As for stream, ASCII Corporation August 1994
"Latest MPEG Textbooks," issued March 1, pages 231 to 2
An explanation is given on page 53.

The MPEG audio decoder 26 appropriately stores the digital audio signal supplied from the demultiplexer 24 in the DRAM 26a and executes the decoding process of the audio signal compressed by the MPEG2 system. The decoded audio signal is D / A converted in the D / A converter 30, and the left channel audio signal is output via the buffer amplifier 31L.
The audio signal of the right channel is the buffer amplifier 31.
It is output via R.

The RF modulator 41 converts the composite signal output by the NTSC encoder 27 and the audio signal output by the D / A converter 30 into an RF signal and outputs the RF signal. Further, the RF modulator 41 allows an NTSC-type RF signal input from an AV device such as a cable box to pass through when the TV mode is set,
VCR (Video Cassette Record)
er) and other AV equipment.

In the case of this embodiment, these video signals and audio signals are supplied to the monitor device 4 via the AV line 11.

CPU (Central Process)
or Unit) 29 executes various processes according to programs stored in the ROM 37. For example, the tuner 21, the QPSK demodulation circuit 22, the error correction circuit 2
Control 3 and so on. Also, the AV device control signal transmitting / receiving unit 2
A is controlled, and another A is controlled through the control line 12.
It outputs a predetermined control signal to the V device (in this embodiment, the monitor device 4) and receives a control signal from another AV device.

A predetermined command can be directly input to the CPU 29 by operating the operation button switch (FIG. 3) on the front panel 40. Further, when the remote commander 5 is operated, an infrared signal is emitted from the IR transmitter 51, the infrared signal is received by the IR receiver 39, and the light reception result is supplied to the CPU 29. Therefore,
The CPU can also be operated by operating the remote commander 5.
A predetermined command can be input to 29.

Further, the demultiplexer 24 uses the data supplied from the front end 20 to determine the MPG (Mas).
EP included in ter Program Guide)
G (Electrical Program Guid)
e: Electronic program guide) Takes in data, supplies it to the EPG area 35A of the data buffer memory 35, and stores it. The EPG information includes information (for example, program channel, broadcast time, title, category, etc.) about programs on each broadcast channel from the current time to several tens of hours later. Since this EPG information is transmitted frequently, E
The latest EPG can always be held in the PG area 35A. Further, the CPU creates a sort table from the EPG data stored in the EPG area 35A, and SR
Store in AM36.

EEPROM (Electrically)
Erasable Programmable Rea
In the d Only Memory) 38, the data (for example, the reception history of the tuner 21 for four weeks, the channel number (last channel) received immediately before the power-off) which is desired to be retained after the power-off is appropriately stored in the d Only Memory 38. To be done.
Then, for example, when the power is turned on, the same channel as the last channel is received again. ROM 37 when the last channel is not stored
The channel stored as the default is received.

Further, when the sleep mode is set, the CPU 29 activates the minimum circuits such as the front end 20, the demultiplexer 24, the data buffer memory 35, etc. even when the power is off, and receives the received signal. It also measures the current time from the time information included in, and controls each circuit to perform a predetermined operation at a predetermined time. For example, timer automatic recording is executed in conjunction with an external VCR.

Further, the CPU 29 has a predetermined OSD (O
When it is desired to generate n-Screen Display data, the MPEG video decoder 25 is controlled. MP
The EG video decoder 25 generates predetermined OSD data in response to this control, writes it in the OSD area of the DRAM 25a, further reads it out, and outputs it. As a result, a program guide (FIG. 7) including predetermined characters and figures can be appropriately output to the monitor device 4 and displayed.

FIG. 5 shows an example of the configuration of a test data generator that generates test data to be supplied to the IRD 2 in the process of manufacturing the IRD 2. This test data generator 200 generates a block 201 for generating and multiplexing video data and audio data, and a block 2 for generating data other than video data and audio data.
And 02.

The video ROM 211 of the block 201 stores test video data, and the audio ROM 212 stores test audio data (audio 1). Furthermore, the data ROM 21
In this embodiment, other audio data (audio 2) for testing is stored in 3. This is because the audio data received by the IRD 2 includes two types of audio data. For example, the audio ROM 212 stores stereo English audio data, and the data ROM 2
In 13, stereo Spanish audio data is stored. The data stored in the data ROM 213 can be changed to data other than audio. The data stored in these ROMs 211, 212, 213 are encrypted data, unencrypted data,
Or both.

The prefix ROM 214 stores the header information of the packet when these data are packetized. For example, PLD (Program
The timing control circuit 215 composed of an Able Logic Device is a video ROM
211, audio ROM 212, data ROM 213
And an address for reading the data stored in the prefix ROM 214 at a predetermined timing, and a process of packetizing these is executed.

The flat cable connector 216 and the serial / parallel conversion / level conversion circuit 217 are connected to the video ROM via a signal generator bus.
211, audio ROM 212, data ROM 21
3, the prefix ROM 214, the timing control circuit 215, and the flat cable connector 2
16 converts the supplied packet data into, for example, 8-bit parallel data of TTL and supplies it to the demultiplexer (transport block) 24 of the IRD 2. Serial / parallel and level conversion circuit 217
Inputs the input data into PECL (Positive)
It is converted into serial data of Emitter-Coupled Logic) level and output to the modulator 201 (FIG. 6).

On the other hand, the ROM 231 of the block 202 stores the program of the CPU 235 and MPG data. This MPG data includes EPG data (channel number, title, start time, etc.) for creating an on-screen program guide, and SCID (ServiceC) corresponding to each channel.
channel (Identifier). This SCID is used to identify a data packet, and video data, two audio data, conditional access data, etc. of a predetermined channel have their own SCID, and each channel and SCID
The relationship is not fixed. Which data is which SCI
Whether it corresponds to D is described in MPG. IRD2
Receives the MPG and grasps the SCID correspondence before decoding the video data and audio data. The SCID of the MPG itself is fixed and is always set to 1. The MPG having the same content is transmitted from any transponder of each satellite, and the IRD 2 can receive the MPG.

The RAM 232 functions as a working memory required for the CPU 235 to perform various processes.

The interface 234 receives an input from a keyboard (not shown), for example, and the CPU 235.
Output a signal corresponding to. Alternatively, it receives a signal from the CPU 235 and outputs it to a monitor device (not shown) or the like.

The computer 241 is connected to the serial port of the CPU 235.
CWP (Control Word Pac)
ket) or CAP (Conditional Acc)
Ess packet) is received in real time, packetized, supplied to the block 201 via the FIFO 233, multiplexed with video data and audio data packets, and output.

The control word (C
control Word) is a key required to decrypt encrypted data, and CAP is an IRD.
It is used to give access right to predetermined video data and audio data, prohibit access, send a message, and rewrite the data of the CAM 33 for each two.

DSS (Direct Satelite)
In the System system, video data and audio data are encoded in the MPEG2 format, and the IRD2 decodes the DSS system transmission data.
The data stored in M is data in accordance with this DSS transmission format.

FIG. 6 shows a connection example when the IRD 2 is inspected by using the test data generator (packet injector) having such a configuration. As shown in the figure, the data output from the flat cable connector 216 of the test data generator 200 is supplied to the demultiplexer (transport block) 24 of the IRD 2. The demultiplexer 24 processes the test data supplied from the test data generator 200, and supplies the data obtained as a result of the processing to the MPEG video decoder 25 and the MPEG audio decoder 26. The MPEG video decoder 25 and the MPEG audio decoder 26 decode these data and supply them to the test monitor device 203 for display. As a result, it is possible to test whether each circuit after the demultiplexer 24 is operating normally.

On the other hand, the data output from the serial / parallel and level conversion circuit 217 of the test data generator 200 is supplied to the modulator 201 and QPSK modulated according to the DSS method. The modulator 201 is a QPS
The K-modulated signal is converted into an IF signal in the band of 950 MHz to 1450 MHz and supplied to the front end 20 of the IRD 2. The front end 20 is a modulator 201.
The supplied IF signal is demodulated, and the demodulation result is output to the demultiplexer 24. The demultiplexer 24 demultiplexes the data supplied from the front end 20, and then supplies the video data and audio data to the MPEG video decoder 25 and the MPEG audio decoder 26, respectively. The MPEG video decoder 25 and the MPEG audio decoder 26 decode the input data, and the decoding result is monitored by the monitor device 2.
Output to 03. In this way, the MPEG video decoder 25 and the MPE from the front end 20 of the IRD 2
It is possible to check whether the circuits up to the G audio decoder 26 are operating normally.

Next, the test data generator 200 shown in FIG.
The operation of will be described.

When a command to generate test data is issued from the keyboard to the CPU 235 via the interface 234,
The CPU 235 controls the timing control circuit 215. At this time, the timing control circuit 215 determines that the video R
Video data is read from OM211 and audio R
The audio data is read from the OM 212 and the data ROM 213 and packetized. Then, the prefix ROM 21 is added to the header of each packet.
The header information read from 4 is added.

As a result, for example, as shown in FIG. 7, the S of the header of the video packet of the 100th channel, for example.
10 is described as the CID. Also, audio RO
11 is described as the SCID of the header of the audio packet of the audio data read from M212, and 12 is described as the SCID of the header of the audio data read from the data ROM 213.

When testing the circuits after the demultiplexer 24, these packet data are supplied to the demultiplexer 24 of the IRD 2 via the flat cable connector 216.

The CPU 235 also reads the MPG data stored in the ROM 231. In this MPG data, as shown in FIG. 7, data necessary for generating an on-screen program guide, video packets of each channel, and SCIDs of video packets of audio 1 and audio 2 are described. (For example, the SCID of the video packet of channel 100, audio 1, audio 2 is 10, respectively.
11 and 12).

This MPG data is read from the ROM 231 and packetized by the CPU 235. Then, it is supplied to the flat cable connector 216 via the FIFO 233, and further supplied from there to the demultiplexer 24.

When the CPU 29 issues an instruction to receive, for example, the 100th channel, the demultiplexer 24 sends an MP
SCI of video packet of channel 100 from G and audio packets of audio 1 and audio 2
Read D (10, 11 and 12 in this case). Then, a packet with SCID 10, 11, or 12 is extracted, video data is extracted from the packet with SCID = 10, and this is supplied to the MPEG video decoder 25.

Further, the demultiplexer 24 selects one of the audio 1 and the audio 2 which is instructed by the CPU 29, and when the selection of the audio 1 is instructed, the audio data of the packet of SCID = 11 is selected. Are separated and supplied to the MPEG audio decoder 26. When the selection of the audio 2 is instructed, the audio data of the packet of SCID = 12 is taken out and supplied to the MPEG audio decoder 26.

The MPEG video decoder 25 decodes the input video data, and the NTSC encoder 2
7. Monitor device 203 via buffer amplifier 28V
Output to. In addition, the MPEG audio decoder 26
The input audio data is decoded, the decoding result is D / A converted by the D / A conversion circuit 30, and then supplied to the monitor device 203 via the buffer amplifiers 31L and 31R.

In this way, by checking the image displayed on the monitor device 203 and the audio signal output from the image, it is possible to test whether the circuits after the demultiplexer 24 are operating normally. be able to.

In the case of inspecting whether each circuit including the front end 20 is operating normally, the video packet and the audio packet output from the serial / parallel and level conversion circuit 217 are modulated by the modulator 20.
1 and is QPSK modulated. And 950M
It is converted to an IF signal of Hz to 1450 MHz and supplied to the front end 20.

The front end 20 selectively receives an IF having a predetermined frequency in response to a command from the CPU 29 and supplies the demodulated output to the demultiplexer 24 at the subsequent stage. Hereinafter, in IRD2, the same operation as that described above is performed. Therefore, even in this case, it is possible to inspect whether or not each circuit after the front end 20 is normally operating by listening to the image and the sound output from the monitor device 203.

On the other hand, in the case of checking whether or not the encrypted data can be properly decrypted, the encrypted video data and audio data from the video ROM 211, audio ROM 212 and data ROM 213 are Read out. At this time, the CPU 235 from the computer 241
The CWP containing the control word necessary for decrypting this encrypted data is input to. CPU2
The packet 35 packetizes the conditional access data including the CWP and supplies the packet to the block 201 via the FIFO 233. The flat cable connector 216 of the block 201 or the serial / parallel and level conversion circuit 217 transfers these packet data to the IRD.
Output to 2.

When the conditional access data is supplied, the demultiplexer 24 of the IRD 2 supplies the conditional access data to the CAM 33 via the card reader interface 32. In the CAM 33, a CAP indicating whether or not to give an access right from the computer 241 has been transmitted and stored in advance. When storing the access right, the CAM 33 returns the fetched control word to the demultiplexer 24. The demultiplexer 24 is
This control word is used to decrypt the encrypted data, and the MPEG video decoder 25 or MP
Output to the EG audio decoder 26. Hereinafter, the same processing as that described above is performed, and by viewing the output on the monitor device 203, it is possible to check whether or not the decoding is properly performed.

When the access prohibition is described in the CAM 33, the correct decoding is not performed and the monitor device 203 cannot obtain the correct output.
By appropriately updating the contents relating to the access right of the CAM 33, it is possible to check whether or not the correct decryption is performed when the access right is possessed, and whether or not the decryption is mistakenly performed when the access right is not possessed. .

The contents of the CAM 33 are updated by the CAP. Since the CAP can be loaded from the computer 241 to the CPU 235 in real time, rapid inspection is possible.

Further, by making it possible to update the conditional access data in real time in this manner, various conditions can be given and the result can be obtained immediately, especially when developing software. Since it is possible, it is convenient to develop software for processing each part of the IRD 2.

As described above, the MPG data includes data for displaying the program guide,
When the demultiplexer 24 detects this data, it stores it in the EPG area 35A of the data buffer memory 35. When the instruction to display the program guide is input from the CPU 29, the demultiplexer 24 reads the program guide stored in the EPG area 35A,
The data is output to the MPEG video decoder 25.
The MPEG video decoder 25 generates and outputs OSD data corresponding to this data. As a result, a program guide as shown in FIG. 7 is displayed on the monitor device 203. The user moves the cursor displayed in this program guide (in FIG. 7, the cursor is located on NEWS) to the remote controller 5 to move to a predetermined program and perform a predetermined operation. By instructing, reception of the program is instructed. CPU29 of IRD2
When this command is input, will control the front end 20 to receive the program corresponding to the command.

[0064]

As described above, according to the test data generator of the present invention, predetermined data is stored in advance in the first storage means and the second storage means, and this is read out and packetized appropriately. Since the output means outputs the test data, it is possible to easily and reliably generate the test data at low cost.

[Brief description of drawings]

FIG. 1 is a perspective view showing a configuration example of an AV system.

FIG. 2 is a block diagram showing a connection state of the example of FIG.

FIG. 3 is a diagram showing an external configuration of a front surface of the IRD 2 of FIG.

FIG. 4 is a block diagram showing an internal configuration example of an IRD 2 in FIG.

FIG. 5 is a block diagram showing a configuration example of a test data generator of the present invention.

FIG. 6 is a block diagram showing a connection state in a use state of the embodiment of FIG.

FIG. 7 is a diagram for explaining the operation of the embodiment of FIG.

[Explanation of symbols]

1 AV system 2 IRD 3 parabolic antenna 4 Monitor device 4A CRT 5 Remote Commander 21 tuner 23 Error correction circuit 24 demultiplexer 25 MPEG Video Decoder 25a DRAM 26 MPEG Audio Decoder 26a DRAM 29 CPU 35 data buffer memory 35A EPG area 36 SRAM 37 ROM 38 EEPROM 39 IR receiver 200 test data generator 201,202 block 211 Video ROM 212 Audio ROM 213 data ROM 214 prefix ROM 215 Timing control circuit 231 ROM 232 RAM 233 FIFO 235 CPU 241 computer

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References Japanese Patent Laid-Open No. 8-77707 (JP, A) Actual Development 1-132145 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 17/00 H04N 7/24

Claims (5)

(57) [Claims] 1. A test data generator for generating test data for testing a decoder for decoding MPEG-encoded video data and audio data, which stores MPEG-encoded video data and audio data. First storage means, second storage means for storing electronic program guide data, and output means for packetizing the data stored in the first storage means and the second storage means and outputting it as test data And a test data generator. 2. The test data generating apparatus according to claim 1, further comprising a fetching unit that fetches conditional access data defining a condition for accessing at least one of the video data and the audio data. . 3. The test data generating apparatus according to claim 2, wherein the fetching unit fetches the conditional access data in real time. 4. The video data, audio data,
The test data generating apparatus according to claim 3, further comprising a third storage unit that stores an identification ID that identifies the conditional access data. 5. The test data generating apparatus according to claim 1, further comprising a modulation unit that modulates the data output from the output unit.