JP3488098B2 - Optical semiconductor device and manufacturing method thereof - Google Patents

Optical semiconductor device and manufacturing method thereof

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Publication number
JP3488098B2
JP3488098B2 JP28414398A JP28414398A JP3488098B2 JP 3488098 B2 JP3488098 B2 JP 3488098B2 JP 28414398 A JP28414398 A JP 28414398A JP 28414398 A JP28414398 A JP 28414398A JP 3488098 B2 JP3488098 B2 JP 3488098B2
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Japan
Prior art keywords
layer
semiconductor
mesa
support structure
oxide
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JP28414398A
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Japanese (ja)
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JP2000114590A (en
Inventor
文彦 黒田
光弘 櫛部
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Toshiba Corp
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Toshiba Corp
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  • Led Devices (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、Al含有層の選
択酸化を用いた光半導体素子及びその製造方法に関す
る。
TECHNICAL FIELD The present invention relates to an optical semiconductor device using selective oxidation of an Al-containing layer and a method for manufacturing the same.

【0002】[0002]

【従来の技術】選択酸化とは、Al高濃度層を含む半導
体基体を水蒸気雰囲気中で熱処理すると、Al高濃度層
のみが選択的に酸化されるという技術である。熱処理の
温度や時間を制御することにより、またはその他の方法
により、Al高濃度層を部分的に酸化することも全面を
酸化することも可能である。酸化された層は絶縁体とな
り、かつ屈折率が低下するため、例えば半導体レーザ
(LD)の電流および光の閉じ込め層を容易に形成する
ことが可能であることなどから、近年脚光を浴びてい
る。
2. Description of the Related Art Selective oxidation is a technique in which when a semiconductor substrate containing a high Al concentration layer is heat-treated in a steam atmosphere, only the high Al concentration layer is selectively oxidized. It is possible to partially oxidize the Al high concentration layer or to oxidize the entire surface by controlling the temperature and time of the heat treatment or by other methods. Since the oxidized layer serves as an insulator and has a lowered refractive index, it is possible to easily form a current and light confinement layer of a semiconductor laser (LD), and thus has been in the spotlight in recent years. .

【0003】以下、図1にAlGaAs系LDを例にと
って説明する。n型GaAs等の半導体基板1上に、n
型Alx Ga1-x As下部クラッド層2、GaAs等の
活性層3、p型Alx Ga1-x As中間クラッド層4、
AlyGa1-y As(0<x<y≦1)被酸化層5、p
型Alx Ga1-x As上部クラッド層6、GaAsキャ
ップ層7を積層する。この半導体基体をメサエッチング
してAly Ga1-y As被酸化層5の端部を露呈させ、
水蒸気雰囲気中で400〜500℃の熱処理を行なう。
その後、p側電極8、n側電極9を形成する。
Hereinafter, an AlGaAs LD will be described as an example in FIG. On a semiconductor substrate 1 such as n-type GaAs, n
Type Al x Ga 1-x As lower cladding layer 2, active layer 3 such as GaAs, p-type Al x Ga 1-x As intermediate cladding layer 4,
AlyGa 1-y As (0 <x <y ≦ 1) Oxidized layer 5, p
A type Al x Ga 1-x As upper clad layer 6 and a GaAs cap layer 7 are laminated. This semiconductor substrate is mesa-etched to expose the end of the Al y Ga 1-y As oxidized layer 5,
Heat treatment is performed at 400 to 500 ° C. in a steam atmosphere.
Then, the p-side electrode 8 and the n-side electrode 9 are formed.

【0004】AlGaAsは水蒸気により酸化されてA
2 3 に変化し、誘電体となる。但し、その酸化速度
はAl組成により著しく変化するため、例えば上記x、
yをx<y=0.9〜1とすることで、クラッド層やG
aAsの層にはほとんど影響を与えずに、被酸化層5の
みを選択的に酸化することができる。熱処理の温度と時
間を適宜調整することで、AlGaAs被酸化層の一部
は酸化されない開口部10として残り、電流狭搾ができ
る。開口部10直下の活性層のみに電流が注入されてゲ
インを持ち、活性領域11となる。
AlGaAs is oxidized by water vapor to
It changes to l 2 O 3 and becomes a dielectric. However, since its oxidation rate remarkably changes depending on the Al composition, for example, the above x,
By setting y such that x <y = 0.9 to 1, the cladding layer and G
Only the layer 5 to be oxidized can be selectively oxidized with almost no influence on the layer of aAs. By appropriately adjusting the temperature and time of the heat treatment, part of the AlGaAs oxidized layer remains as the opening 10 that is not oxidized, and the current can be narrowed. A current is injected only into the active layer immediately below the opening 10 to have a gain and become the active region 11.

【0005】また、活性層やクラッド層などの半導体の
屈折率が3.0〜3.5であるのに対して、酸化された
Al2 3 の屈折率は1.5程度に低下するため、活性
領域以外の等価屈折率も低下し、光を活性領域11内に
閉じ込めることが可能となる。尚、波長650nmとい
った赤色光レーザの場合は、活性層3をInGaPと
し、上下のクラッド層2、4、6をInGaAlPとす
ることもできる。
Further, the refractive index of semiconductors such as the active layer and the clad layer is 3.0 to 3.5, whereas the refractive index of oxidized Al 2 O 3 is lowered to about 1.5. Also, the equivalent refractive index outside the active region is lowered, and it becomes possible to confine light in the active region 11. In the case of a red light laser having a wavelength of 650 nm, the active layer 3 may be made of InGaP and the upper and lower cladding layers 2, 4, 6 may be made of InGaAlP.

【0006】この様に簡単な工程で低電流動作のLDが
製造可能となるが、尚いくつかの課題が残されている。
先ず、図の様に順メサを形成した場合、p側電極8を広
くとることができないため、抵抗が増加し、発熱により
素子の性能や寿命を低下させるという問題がある。この
問題に関しては、図2の様に逆メサとすることで、電極
面積を広くとることができる。しかしこの場合、特にマ
ウント時やワイヤボンディング時にメサ基部21やメサ
エッジ22にストレスが集中し、素子性能の劣化や、甚
だしくは素子の破壊をもたらす。
Although it is possible to manufacture an LD operating at a low current with such a simple process, some problems still remain.
First, when the forward mesa is formed as shown in the figure, the p-side electrode 8 cannot be wide, and therefore the resistance increases and heat generation reduces the performance and life of the element. With respect to this problem, an inverted mesa as shown in FIG. 2 can increase the electrode area. However, in this case, stress is concentrated on the mesa base portion 21 and the mesa edge 22 particularly during mounting or wire bonding, which leads to deterioration of element performance or even destruction of the element.

【0007】また電極パッド32を広く取るためには、
図3の様に絶縁膜31を介して隣接するメサ上に配線膜
33を延伸することが必要であるが、これは逆メサや垂
直メサでは容易ではない。また順メサであっても、メサ
端部34や半導体ヘテロ界面の段差35により配線膜3
3が途切れる、いわゆる段切れが起こる恐れがあるとい
う問題があった。
In order to make the electrode pad 32 wider,
As shown in FIG. 3, it is necessary to extend the wiring film 33 on the adjacent mesa via the insulating film 31, but this is not easy with the reverse mesa or the vertical mesa. Even in the case of a forward mesa, the wiring film 3 is formed by the mesa end portion 34 and the step 35 at the semiconductor hetero interface.
There is a problem that there is a possibility that so-called step disconnection may occur, which is a break in 3.

【0008】[0008]

【発明が解決しようとする課題】この発明は、電極面積
が広く抵抗の低い光半導体素子を、簡単な工程で再現性
良く製造できることを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to manufacture an optical semiconductor element having a large electrode area and a low resistance with a simple process and good reproducibility.

【0009】[0009]

【課題を解決するための手段】この発明では、基部にA
l酸化層が挟まれた複数の半導体メサ構造体を並列し、
かつ該メサ構造体の上部同士を半導体接合層により機械
的かつ電気的に接合させることにより解決する。
According to the present invention, the base portion has an A
a plurality of semiconductor mesa structures sandwiching an oxide layer are arranged in parallel,
The problem is solved by mechanically and electrically bonding the upper parts of the mesa structure to each other by the semiconductor bonding layer.

【0010】その製造方法は、半導体基板上に、少なく
ともAl含有半導体層を積層し、該Al含有層を部分的
に除去し、該除去された領域に犠牲層を埋め込み、前記
Al含有層および犠牲層上に半導体接合層を積層し、前
記犠牲層を選択的に除去した後、前記Al含有層を選択
的に酸化する工程を含む
In the manufacturing method, at least an Al-containing semiconductor layer is laminated on a semiconductor substrate, the Al-containing layer is partially removed, a sacrificial layer is buried in the removed region, and the Al-containing layer and the sacrificial layer are formed. Stacking a semiconductor junction layer on the layer, selectively removing the sacrificial layer, and then selectively oxidizing the Al-containing layer

【0011】[0011]

【発明の実施の形態】この発明の基本となる工程を、A
lGaInP系赤色LDに適用した場合を例にとって、
図4に示す。先ず同図(a)の様に、n型GaAs基板
41上に、例えば厚さ1.1μmのn型InGaAlP
の下部クラッド層42、厚さ0.17μmのi型35A
(オングストローム)のInGaAlPをバリアとし、
厚さ40AのInGaP量子井戸を複数設けた活性層4
3、厚さ0.2μmのp型InGaAlPからなる中間
クラッド層44、厚さ50AのInGaPエッチストッ
プ層45、厚さ0.1μmのAlx Ga1-x As被酸化
層46、厚さ0.9μmのInGaAlP上部クラッド
層47、厚さ500AのInGaP通電容易層48、厚
さ2μmのGaAsキャップ層49を結晶成長する。こ
こで被酸化層46のAl組成Xは、X=0.9とする。
BEST MODE FOR CARRYING OUT THE INVENTION
Taking as an example the case of being applied to a 1GaInP-based red LD,
As shown in FIG. First, as shown in FIG. 4A, an n-type InGaAlP film having a thickness of 1.1 μm, for example, is formed on the n-type GaAs substrate 41.
Lower cladding layer 42, i-type 35A with a thickness of 0.17 μm
(Angstrom) InGaAlP as a barrier,
Active layer 4 having a plurality of 40 A thick InGaP quantum wells
3, an intermediate cladding layer 44 made of p-type InGaAlP having a thickness of 0.2 μm, an InGaP etch stop layer 45 having a thickness of 50 A, an Al x Ga 1-x As oxidized layer 46 having a thickness of 0.1 μm, and a thickness of 0. A 9 μm InGaAlP upper cladding layer 47, a 500 A thick InGaP conducting layer 48, and a 2 μm thick GaAs cap layer 49 are crystal-grown. Here, the Al composition X of the layer 46 to be oxidized is X = 0.9.

【0012】この基板にSiO2 膜400を装着し、フ
ォトリソグラフィ工程により図4(b)の様にメサ加工
する。GaAsキャップ層49およびInGaP通電容
易層48はBr系のエッチャントで除去可能であり、そ
の後、燐酸でエッチングするとInGaPエッチストッ
プ層45でエッチングは停止する。結晶方位を選ぶこと
により、図の様に逆メサ状のメサ構造体401、402
が形成される。
A SiO 2 film 400 is mounted on this substrate, and a mesa process is performed as shown in FIG. 4B by a photolithography process. The GaAs cap layer 49 and the InGaP easy-current-carrying layer 48 can be removed with a Br-based etchant, and thereafter, when etching is performed with phosphoric acid, the etching is stopped at the InGaP etch stop layer 45. By selecting the crystal orientation, the inverted mesa-shaped mesa structures 401 and 402 as shown in FIG.
Is formed.

【0013】このまま結晶成長を行なうと、SiO2
には結晶が成長しないため、隣接するメサ構造体間のエ
ッチング溝には、図4(c)の様にAlAs犠牲層40
3、GaAs第二キャップ層404を埋め込むことがで
きる。この様な埋め込み成長は、LDの電流ブロック層
形成によく用いられるが、その場合リーク電流を減らす
ために、埋め込み成長界面やブロック層自身の結晶性、
ドーピングレベルなどを厳密に制御する必要があり、成
長条件の制約が大きい。しかし今の場合、後で述べる様
に犠牲層は除去されるものであるため制約は少なく、容
易に結晶成長することができる。
If the crystal is grown as it is, no crystal grows on the SiO 2 , so that the AlAs sacrificial layer 40 is formed in the etching groove between the adjacent mesa structures as shown in FIG. 4C.
3. The GaAs second cap layer 404 can be embedded. Such buried growth is often used for forming a current block layer of an LD. In this case, in order to reduce the leak current, the crystallinity of the buried growth interface or the block layer itself,
It is necessary to strictly control the doping level and the like, and the growth conditions are largely restricted. However, in this case, since the sacrificial layer is removed as described later, there are few restrictions and crystal growth can be easily performed.

【0014】その後、図4(d)の様にSiO2 膜40
0を除去して全面にGaAs接合層405を成長した
後、更にフォトリソグラフィ工程によりGaAs接合層
405にエッチング孔406を設ける。この孔は、Ga
As/AlAs界面で止まっている必要はなく、AlA
s犠牲層403まで突き抜けていてよい。
Then, as shown in FIG. 4D, the SiO 2 film 40 is formed.
After 0 is removed and a GaAs junction layer 405 is grown on the entire surface, an etching hole 406 is further provided in the GaAs junction layer 405 by a photolithography process. This hole is Ga
It is not necessary to stop at the As / AlAs interface, AlA
The sacrificial layer 403 may be penetrated.

【0015】通常、埋込み層の界面には表面に段差が生
じるため、エッチング孔406の大きさはメサ構造体の
間隔よりも小さいものとしておけば、特にマーカ等を設
けておかなくとも、充分なマージンをもってエッチング
孔を設けることができる。硫酸系や臭素系のウエットエ
ッチングを用いてもよいが、反応性イオンビームエッチ
ング(RIE)を用いれば垂直な孔を設けることがで
き、マージンは拡大する。
Usually, a step is formed on the surface of the interface of the burying layer. Therefore, if the size of the etching hole 406 is smaller than the space between the mesa structures, it is sufficient without providing a marker or the like. The etching hole can be provided with a margin. Sulfuric acid-based or bromine-based wet etching may be used, but if reactive ion beam etching (RIE) is used, vertical holes can be formed and the margin is expanded.

【0016】この孔を通してAlAs犠牲層403を除
去することにより、犠牲層のあった領域には空洞が生じ
る。つまり、メサ構造体401、402の上部同士が、
GaAs接合層405により接合された形となる。
By removing the AlAs sacrificial layer 403 through this hole, a cavity is formed in the region where the sacrificial layer was present. That is, the upper parts of the mesa structures 401 and 402 are
The GaAs junction layer 405 forms a junction.

【0017】犠牲層403はAlAsであり、かつ厚さ
が1μm以上あるため、例えばフッ化アンモン液で容易
に除去できる。エッチング孔406の一辺を、例えば5
μm以上としておくことによりエッチャントの回り込み
も充分となり、犠牲層の除去も容易である。
Since the sacrificial layer 403 is made of AlAs and has a thickness of 1 μm or more, it can be easily removed with an ammonium fluoride solution, for example. One side of the etching hole 406 is, for example, 5
By setting the thickness to be at least μm, the wrapping of the etchant will be sufficient and the removal of the sacrificial layer will be easy.

【0018】このときAlGaAs被酸化層も僅かに溶
かされるが、エッチングレートはAlAsよりも小さい
ことに加えて、厚さも犠牲層に比べて小さいため、影響
は少ない。
At this time, the oxidized layer of AlGaAs is also slightly dissolved, but since the etching rate is smaller than that of AlAs and the thickness is smaller than that of the sacrificial layer, the influence is small.

【0019】その後、図4(e)の様に水蒸気雰囲気中
でメサ構造体基部のAlGaAs被酸化層46を選択酸
化して、Al酸化層407を形成する。このとき、メサ
構造体401と402の幅を違えておけば、細い方のメ
サの基部は完全に酸化して通電をなくした支持構造体4
02となり、太い方のメサの基部には開口部10を設け
て、ここにのみ電流を流すことが可能な素子構造体40
1となる。
After that, as shown in FIG. 4E, the AlGaAs oxidized layer 46 at the base of the mesa structure is selectively oxidized in a water vapor atmosphere to form an Al oxide layer 407. At this time, if the widths of the mesa structures 401 and 402 are different, the base of the narrower mesa is completely oxidized and the support structure 4 is deenergized.
02, the element structure 40 in which the opening 10 is provided at the base of the thicker mesa and a current can flow only there
It becomes 1.

【0020】p側電極8は、GaAs接合層405上全
面に形成することができ、従来構造のLDよりも広い面
積が確保できるため、抵抗は小さく、素子の性能や信頼
性が向上する。
Since the p-side electrode 8 can be formed on the entire surface of the GaAs junction layer 405 and a larger area can be secured as compared with the LD having the conventional structure, the resistance is small and the device performance and reliability are improved.

【0021】このようにして製造された赤色LDの断面
斜視図を図5に示す。但し、一部を切り欠いて示した。
また、詳細な層構造は省略し、要部のみを示す。番号は
これまでに説明したものと同じである。この例では、ス
トライプ状の素子構造体401を中心として、支持構造
体402が複数配置され、広い電極面積が確保されてい
る。尚、同程度の幅を持つ複数の素子構造体を並列配置
すれば、同時に給電されるアレイレーザとなる。
FIG. 5 is a sectional perspective view of the red LD thus manufactured. However, a part is cut away.
Further, the detailed layer structure is omitted and only the main part is shown. The numbers are the same as described above. In this example, a plurality of support structures 402 are arranged around the stripe-shaped element structure 401, and a wide electrode area is secured. By arranging a plurality of element structures having the same width in parallel, an array laser can be supplied with electric power at the same time.

【0022】いずれの場合でも、エッチング孔406は
矩形に限られるものではなく、円形や多角形でも構わな
い。また孔を広く取って、メッシュ状の接合層がメサ構
造体の上部同士を接合した形としてもよい。更には、犠
牲層が除去された空洞部に、ポリイミドなどの誘電体を
充填してもよい。
In any case, the etching hole 406 is not limited to the rectangular shape, but may be a circular shape or a polygonal shape. Alternatively, the holes may be wide, and the mesh-shaped bonding layer may bond the upper portions of the mesa structures together. Further, the cavity from which the sacrificial layer has been removed may be filled with a dielectric material such as polyimide.

【0023】素子構造体や支持構造体もストライプ状に
限られるものではなく、円形や矩形でも構わない。ま
た、支持構造体は必ずしも素子構造体と同じ長さを持つ
必要はなく、途中で途切れていても島状のものであって
も構わない。更にそれぞれの構造体は必ずしも逆メサに
限られるものではなく、垂直メサや純メサでもこの発明
の趣旨は生かされるであろう。
The element structure and the support structure are not limited to the stripe shape, and may be circular or rectangular. In addition, the support structure does not necessarily have to have the same length as the element structure, and may be discontinuous or island-shaped. Further, each structure is not necessarily limited to the reverse mesa, and the gist of the present invention can be applied to a vertical mesa or a pure mesa.

【0024】図6(a)には、矩形の素子構造体401
を支持構造体402が取り囲んだ例を示す。支持構造体
の幅が素子構造体の幅より小さければ、開口部10を残
して支持構造体基部を完全に酸化することができる。こ
の図では省略したが、やはり構造体401、402の上
部は結合層で結合されている。開口部10の下に光を発
する活性層があれば発光ダイオード(LED)となり、
更に上下に多層反射膜を装着すれば面発光レーザとな
る。
FIG. 6A shows a rectangular element structure 401.
An example in which the support structure 402 surrounds the above is shown. If the width of the support structure is smaller than the width of the device structure, the base of the support structure can be completely oxidized leaving the opening 10. Although omitted in this figure, the upper portions of the structures 401 and 402 are also bonded by a bonding layer. If there is an active layer that emits light under the opening 10, it becomes a light emitting diode (LED),
Further, by mounting a multilayer reflective film on the upper and lower sides, it becomes a surface emitting laser.

【0025】この場合、素子構造体上に電極金属が装着
されると光の放出が遮られるため、同図(b)の斜線で
示すように、電極金属は素子構造体401上で開口部を
持たねばならない。この場合でも、電極金属は結合層と
広い面積で接しているため、抵抗は低い。
In this case, since the emission of light is blocked when the electrode metal is mounted on the element structure, the electrode metal has an opening on the element structure 401 as shown by the hatched portion in FIG. Must have Even in this case, since the electrode metal is in contact with the bonding layer over a wide area, the resistance is low.

【0026】言うまでもないが、この例に於いても支持
構造体402は必ずしも素子構造体を完全に取り囲んで
いる必要はなく、途中で途切れていても島状のものであ
っても構わない。
Needless to say, in this example as well, the support structure 402 does not necessarily have to completely surround the element structure, and it may be discontinuous or island-shaped.

【0027】以上はInGaAlP系半導体レーザにA
lGaAs被酸化層を用いることを想定して説明してき
たが、この発明の適用はこれに限られるものではない。
例えば被酸化層にはAlGaP、AlInAs、AlI
nP、AlSb、AlN等のAlを高濃度に含むあらゆ
る化合物に適用可能であるし、クラッド層などの酸化さ
れない層は、GaAs、InP、InGaAsP、In
GaSb、InGaN等、Al濃度の低いあらゆる化合
物でよい。更に半導体結合層はGaAsに限る必要はな
く、電極金属との電気抵抗が低くなるものであれば何で
もよい。
The above is applicable to InGaAlP semiconductor lasers.
Although description has been made assuming that the 1GaAs oxidized layer is used, the application of the present invention is not limited to this.
For example, the oxidized layer is made of AlGaP, AlInAs, AlI.
It can be applied to any compound containing Al at a high concentration, such as nP, AlSb, and AlN, and non-oxidized layers such as the clad layer are GaAs, InP, InGaAsP, In
Any compound having a low Al concentration such as GaSb or InGaN may be used. Further, the semiconductor coupling layer is not limited to GaAs, and may be any as long as it has a low electric resistance with the electrode metal.

【0028】犠牲層も、必ずしもAlAsの様な半導体
である必要はない。例えばGaN系で近年盛んに研究さ
れている横方向成長技術を用いて、図4(b)の状態で
エッチング溝にSiO2 を埋め込み、逆に表面のSiO
2 膜400を除去して結晶成長を行なう。これにより、
半導体結合層405までを2回の結晶成長で形成するこ
とができる。犠牲層はSiO2 であるため埋め込みは容
易であり、かつ除去も容易である。
The sacrificial layer does not necessarily have to be a semiconductor such as AlAs. For example, using a lateral growth technique that has been actively studied in GaN-based materials in recent years, SiO 2 is buried in the etching groove in the state of FIG.
2 The film 400 is removed and crystal growth is performed. This allows
The semiconductor coupling layer 405 can be formed by crystal growth twice. Since the sacrificial layer is SiO 2 , it is easy to embed and also easy to remove.

【0029】 半導体素子はレーザに限る必要もなく、
発光ダイオード、フォトダイオード等の光半導体素子
も適用可能である。
The semiconductor element need not be limited to the laser,
It is also applicable to optical semiconductor elements such as light emitting diodes and photodiodes .

【0030】[0030]

【発明の効果】この発明により、電極面積が広く抵抗の
低い半導体素子を、簡単な工程で再現性良く製造できる
According to the present invention, a semiconductor element having a wide electrode area and a low resistance can be manufactured with good reproducibility in a simple process.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の半導体素子の断面図である。FIG. 1 is a cross-sectional view of a conventional semiconductor device.

【図2】従来の半導体素子の断面図である。FIG. 2 is a cross-sectional view of a conventional semiconductor device.

【図3】従来の半導体素子の断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor device.

【図4】この発明の実施例を示す断面工程図である。FIG. 4 is a sectional process drawing showing an embodiment of the present invention.

【図5】この発明の実施例を示す断面斜視図である。FIG. 5 is a sectional perspective view showing an embodiment of the present invention.

【図6】この発明の実施例を示す断面斜視図および平面
図である。
FIG. 6 is a sectional perspective view and a plan view showing an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

401,402: メサ構造体 405: 半導体接合層 407: Al酸化層 8: 電極金属 46: Al含有半導体層 403: 犠牲層 401, 402: Mesa structure 405: Semiconductor junction layer 407: Al oxide layer 8: Electrode metal 46: Al-containing semiconductor layer 403: Sacrificial layer

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01S 5/00 - 5/50 H01L 33/00 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01S 5/00-5/50 H01L 33/00

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板上にメサ構造体が複数形成さ
れてなると共に、前記メサ構造体中にAl酸化層が成層
されてなるものであって、前記メサ構造体は、該メサ構
造体の横断面に前記Al酸化層が部分的に設けられるよ
う成層された素子構造体と、該メサ構造体の横断面に前
記Al酸化層が全面にわたるよう成層された支持構造体
とで構成され、かつ前記素子構造体と支持構造体の上部
同士が半導体接合層により機械的かつ電気的に接合して
いることを特徴とする光半導体素子
1. A plurality of mesa structures are formed on a semiconductor substrate.
And an Al oxide layer is formed in the mesa structure.
And the mesa structure has a structure similar to that of the mesa structure.
The Al oxide layer is partially provided on the cross section of the structure.
A layered device structure and a cross-section of the mesa structure
A support structure in which an Al oxide layer is layered over the entire surface
The optical semiconductor element characterized by being configured, and upper portions of the element structure and the support structure is mechanically and electrically joined by the semiconductor junction layer between.
【請求項2】 前記支持構造体のAl酸化層成層部分
が、前記素子構造体のAl酸化層成層部分よりも細く形
成されていることを特徴とする請求項1記載の光半導体
素子
2. An Al oxide layered portion of the support structure.
Is thinner than the Al oxide layered portion of the device structure.
The optical semiconductor according to claim 1, wherein the optical semiconductor is formed.
Element .
【請求項3】 前記支持構造体上方の半導体接合層上部
には、金属電極が全面に装着されており、前記素子構造
体上方の半導体接合層上部には、開口部を設けて金属電
極が装着されていることを特徴とする請求項1記載の
半導体素子
3. A semiconductor junction layer upper portion above the support structure.
In the device structure, a metal electrode is mounted on the entire surface.
The light according to claim 1, wherein a metal electrode is attached to the upper part of the semiconductor bonding layer above the body by providing an opening.
Semiconductor device .
【請求項4】 半導体基板上に、少なくとも1層のAl
含有半導体層を含む複数の半導体層を積層する工程、
記複数の半導体層を上面側から部分的にエッチングによ
り除去して前記Al含有半導体層を有するメサ構造の素
子構造体と支持構造体を形成する工程、前工程で除去さ
れた前記構造体間の領域に犠牲層を埋め込む工程、前記
素子構造体及び支持構造体、前記犠牲層上に半導体接合
層を積層する工程、前記半導体接合層を積層した後に
記犠牲層を除去する工程、前記犠牲層を除去した後、前
記素子構造体のAl含有半導体層を部分的に酸化し、前
記支持構造体のAl含有半導体層を全酸化する工程を含
むことを特徴とする光半導体素子の製造方法。
4. At least one layer of Al on a semiconductor substrate
A step of stacking a plurality of semiconductor layers including a containing semiconductor layer, before
The semiconductor layers are partially etched from the top surface side.
Of the mesa structure having the Al-containing semiconductor layer
Forming a child structure and a supporting structure , burying a sacrificial layer in a region between the structures removed in the previous step,
An element structure and a support structure, a step of stacking a semiconductor bonding layer on the sacrificial layer, a step of removing the sacrificial layer after stacking the semiconductor bonding layer, and a step of removing the sacrificial layer, Previous
The Al-containing semiconductor layer of the element structure is partially oxidized,
A method for manufacturing an optical semiconductor element , comprising a step of completely oxidizing the Al-containing semiconductor layer of the support structure .
JP28414398A 1998-10-06 1998-10-06 Optical semiconductor device and manufacturing method thereof Expired - Fee Related JP3488098B2 (en)

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JP28414398A JP3488098B2 (en) 1998-10-06 1998-10-06 Optical semiconductor device and manufacturing method thereof

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JP3488098B2 true JP3488098B2 (en) 2004-01-19

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Publication number Priority date Publication date Assignee Title
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