JP3485793B2 - Nonvolatile memory and microcomputer incorporating the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory such as a flash memory and a microcomputer incorporating the same (hereinafter referred to as a microcomputer), and more particularly to a nonvolatile memory added with a function for efficiently testing a memory. About sex memory.

[0002]

2. Description of the Related Art An electrically erasable programmable ROM (EEPROM: E) whose memory cell is a single transistor
lectricaly Erasable Programmable ROM)
2 with floating gate and control gate
Each memory cell is composed of a transistor having a double gate structure. In the case of such a transistor having a double-gate structure, information is written by accelerating hot electrons generated on the drain side of the floating gate toward the source side, passing through the gate insulating film and injecting into the floating gate, Erasing is performed by extracting the injected hot electrons from the floating gate. Then, information is read by detecting a difference in operating characteristics of the memory cell transistor depending on whether or not electric charge is injected into the floating gate.

Particularly, a non-volatile memory capable of batch erasing and writing for each sector (128 bytes) is called a flash memory. The flash memory may be built in as a memory in which a program of a microcomputer is written, and this is called a flash microcomputer. The write, erase, and read operations as described above are performed by externally applied control signals * CE (chip enable), * WE (write enable), and * O.
It is controlled by E (output enable).

FIG. 3 is a partial block diagram of a non-volatile memory showing a conventional example for performing the above control. In the figure, an oscillator circuit 1 is a ring oscillator for generating a clock signal CLK, and its output is applied to a timer counter 2. The timer counter 2 is composed of a binary counter, and outputs A1 and A2 of a predetermined stage are applied to the control circuit 3. The control circuit 3 controls the control signal * CE,
* OE and * WE signals and timer counter 2 output A1
And A2, an internal write signal WRT for the nonvolatile memory cell, an erase mode signal ERASE, and a write mode signal PROGRAM are generated.

FIG. 4 is a timing chart for writing data in sector units in the circuit shown in FIG.
The operation of the control circuit 3 will be described. When the control signals * CE and * WE are set to the “L” level while the externally applied control signal * OE is set to the “H” level, the control circuit 3 sets the internal write signal WRT to the “H” level. This puts the non-volatile memory in a writable state. Then, by clocking the control signals * CE and * WE, one sector (128) is stored in the buffer (not shown) of the nonvolatile memory specified by the applied address.
(Byte) of data is written. Control signal * CE,
Based on the end of * WE clocking 128 times, the control circuit 3 sets the erase mode signal ERASE to the “H” level to start the erase operation for one sector of the nonvolatile memory. On the other hand, the control circuit 3 resets the timer counter 2 in synchronization with the generation of the erase mode signal “H”. The erasing operation of the non-volatile memory is an operation of drawing out the charges injected into the floating gate to the control gate, and the erasing of the memory cells of one sector is performed collectively.
The erase time also varies depending on the variation of each memory cell. Therefore, the timer counter 2 sets a time sufficient to complete the erasing of all memory cells. For example, when the frequency-divided output A1 is generated 1.6 msec after the reset, the control circuit 3 sets the erase mode signal ERASE to the “L” level. This allows
The erase operation ends. In response to the end of the erase mode signal ERASE, the control circuit 3 causes the write mode signal PR
The OGRAM is set to the “H” level to start the write operation of the erased sector. Also, the timer counter 2 is reset in synchronization with the start of writing. In this write operation, the 128-byte data held in the buffer is written all at once, but it takes a sufficient time to complete the write because the write characteristics of the memory cells vary. Therefore, the writing time is, for example,
The control circuit 3 sets the write mode signal PROGRA by the frequency division output A2 which is set to 3.2 msec and is output 3.2 msec after the reset of the timer counter 2.
M is set to "L" level, and the write operation is completed. This completes writing in sector units. A so-called flash microcomputer has been developed which incorporates such a non-volatile memory as a program memory or a data memory of the microcomputer. FIG. 5 is a schematic block diagram of a flash microcomputer, which includes a CPU portion 4 of the microcomputer and a non-volatile memory 5. Control signals * CE, * OE, * WE and address signal AD of the non-volatile memory 5
Is applied from the CPU part 4 and the data DATA
Is also exchanged with the CPU part 4.

In the normal operating state, the program of the microcomputer writes the nonvolatile memory 5 as needed. In this case, the control signals * CE, * OE,
* CPU part 4 controls non-volatile memory 5 by WE. Further, in such a microcomputer, in order to test the non-volatile memory 5, writing and testing can be performed directly from the outside by a PROM writer. That is, when the microcomputer is put in the test state, the input / output terminal I / 0 directly causes the control signal * CE of the nonvolatile memory 5,
Since it is connected to * OE, * WE, address AD and data DATA, the non-volatile memory 5 can be directly controlled from the outside.

[0007]

When manufacturing and shipping the above-mentioned non-volatile memory, a tester is used.
A sector unit write test is performed as shown in. At this time, the erase time and the write time are set to be sufficiently long according to the variation of the memory cells, so the test time becomes long, which is an obstacle to the improvement of the production success rate.

[0008]

The present invention has been made in view of the above-mentioned points, and an internal clock signal generation circuit, a counter for counting clocks from the internal clock signal generation circuit, and an externally applied signal. In a non-volatile memory provided with a control circuit for applying a control signal for controlling writing and reading and generating an erase mode signal and a write mode signal of a non-volatile memory cell based on an end signal from the counter, A first gate circuit for switching and outputting a first output signal of the counter applied to the control circuit and a timing signal applied to a first external terminal as an erase mode end signal, and applied to the control circuit The second output signal of the counter and the timing signal applied to the second external terminal are switched as the write mode end signal. And a second gate circuit for inputting the write mode signal is provided so that the generation period of the erase mode signal and the generation period of the write mode signal can be set independently.

Further, when the gate circuit is composed of a switching circuit, a switching signal for controlling the switching circuit is applied to an external terminal in a test mode for testing a nonvolatile memory cell, and an end signal from a counter is output. It is switched to the timing signal. As a result, in the test of the nonvolatile memory, the erase time and the write time can be controlled from the outside, and the test time can be shortened. On the other hand, in a microcomputer including a non-volatile memory, the non-volatile memory includes an internal clock signal generation circuit, a counter for counting a clock from the internal clock signal generation circuit, an end signal from the counter, and the end signal. A control circuit for generating an erase mode signal and / or a write mode signal of a nonvolatile memory cell based on a control signal for controlling writing and reading generated inside the microcomputer, and an output of the counter and an external terminal. An erase mode signal output from the control circuit according to a timing signal from the outside for terminating the erase mode signal and / or the write mode signal, the gate circuit switching the applied timing signal and applying it to the control circuit. And / or control of termination of write mode signal In a test mode for testing the non-volatile memory, the control signal and the timing signal for controlling the writing and reading are directly applied from an external input / output terminal of the microcomputer, and are directly externally applied to the non-volatile memory. Testing is possible.

As a result, the test of the nonvolatile memory built in the microcomputer can be directly controlled from the outside, and the erase and write times can be shortened.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention and shows a part of a nonvolatile memory. In the figure, the oscillator circuit 1, the timer counter 2, and the control circuit 3 are the same circuits as in the block diagram shown in FIG.
The figure numbers are matched. The feature of this embodiment lies in that outputs A1 and A2 of a predetermined stage of the timer counter 2
The switching circuits 6 and 7 are provided between the control circuit 3 and the control circuit 3, respectively. The switching operation of the switching circuits 6 and 7 is controlled by the control signals CTL1 and CTL2 applied to the external terminals, and the control signals CTL1 and CTL2 are controlled.
Becomes "H" level, the switching circuits 6 and 7 respectively supply the timing signal TIMG1 or TIMG2 applied to the external terminal from the frequency division output A1 to the control circuit 3. The control signals CTL1 and CTL2 and the timing signals TIMG1 and TIMG2 are configured to be input from external terminals in the test mode. That is, although not shown, an external terminal for setting the test mode is provided, and a test signal is applied to this terminal to enter the test mode, and in this state, input from the terminal is possible. Next, the write operation in sector units will be described. In normal operation, the control signals CTL1 and CTL2 are at “L” level, and the switching circuits 6 and 7 output the frequency-divided outputs A1 and A2 of the timer counter 2 to the control circuit 3. Therefore, the write operation in this case is the same as the operation described in FIG. On the other hand, in the test mode, the non-volatile memory tester sets the control signals CTL1 and CTL2 to “H”.
As the level, timing signals TIMG1 and TIMG
2 can be applied to the control circuit 3. Therefore, in the timing chart of FIG. 4, when one sector of data is written in the buffer and the erase mode signal ERASE is set to the “H” level to perform the erase operation, normally, there is a sufficient margin. The erase operation is ended by the frequency-divided output A1 output as
When the scheduled time, which is considered to complete the erasing of the non-volatile memory, has passed, an external tester causes a timing signal TIM.
By setting G1 to "H" level, the erase mode signal ERASE becomes "L" level, and the erase operation is completed. For example, the normal erase operation period is 1.6 msec.
However, in the test mode, half of that is 0.8m
It becomes possible to set to sec. Similarly, due to the completion of the erase mode signal ERASE, the write mode signal P
When the ROGRAM is set to the “H” level and the write operation is performed, in the test mode, the external tester causes the timing signal to be output when the time when the write is considered to have ended, in consideration of the write variation of the memory cells. By setting TIMG2 to "H" level, the write mode signal PROGRAM becomes "L" level,
The write operation ends. Therefore, normally, the write time set with a sufficient margin, for example, 3.2 ms.
ec can be set to 1.6 msec. As described above, in the test mode, the erase time or the write time, which is set with a sufficient margin in the normal operation, can be freely set from the outside in the test mode, so that the operation can be ended without any particular margin.

FIG. 2 is a block diagram showing another embodiment of the present invention. In FIG. 2, gate circuits 8 and 9 are composed of AND gates and OR gates, respectively, and have timing signals TIMG1 and TIMG2 applied to external terminals.
Are respectively applied to OR gates, and their inverted signals are AN
It is applied to the D gate. Timing signal TIMG1
Alternatively, the TIMG2 is at the "L" level in the normal state, so the frequency-divided outputs A1 and A2 of the timer counter 2 are output to the control circuit 3. On the other hand, in the test mode, the non-volatile memory tester changes the timing signal TIM.
G1 and TIMG2 can be applied to the control circuit 3. Therefore, similar to the above, when the timing signal TIMG1 or TIMG2 is set to the “H” level at the timing of ending the erase operation or the write operation, the erase mode signal ERASE or the write mode signal PROGRAM becomes the “L” level and the mode is changed. Ends. Also,
When the nonvolatile memory shown in FIG. 1 is built in a microcomputer as shown in FIG. 5, the terminals to which the control signals CTL1 and CTL2 are applied and the terminals to which the timing signals TIMG1 and TIMG2 are applied are the input / output terminals I / I of the microcomputer. It is used in common with O, and when the microcomputer is in the test mode, the signal applied to the input / output terminal I / O is directly supplied to the nonvolatile memory. Therefore,
Even when testing the nonvolatile memory of the microcomputer, the test can be performed in the same manner as the standalone nonvolatile memory. The same applies when the nonvolatile memory shown in FIG. 2 is built in the microcomputer.

[0013]

As described above, according to the present invention, in the test mode, the erasing time or the writing time set with a sufficient margin in the normal operation can be freely set from the outside. The operation can be ended without having. Therefore, the total time of erasing and writing can be shortened, which contributes to the improvement of productivity.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a timing diagram showing a sector write operation of the nonvolatile memory.

FIG. 5 is a block diagram of a microcomputer including a nonvolatile memory.

[Explanation of symbols]

1 oscillator circuit 2 timer counter 3 control circuit 4 CPU 5 Non-volatile memory 6, 7 switching circuit 8, 9 Gate circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ identification code FI G11C 17/00 631 (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 29/00 G11C 16/06-16 / 34

Claims (6)

(57) [Claims] 1. An internal clock signal generation circuit, a counter for counting clocks from the internal clock signal generation circuit, and a control signal applied from the outside for controlling writing and reading is applied to terminate the output from the counter. In a nonvolatile memory including a control circuit that generates an erase mode signal and a write mode signal of a nonvolatile memory cell based on a signal, a first output signal of the counter and a first output signal applied to the control circuit are provided. A first gate circuit that switches and outputs a timing signal applied to an external terminal as an erase mode end signal, a second output signal of the counter applied to the control circuit, and a timing applied to a second external terminal. A second gate circuit for switching and outputting the signal as a signal for ending the write mode, and a generation period of the erase mode signal. A non-volatile memory characterized in that the interval and the generation period of the write mode signal can be set independently. 2. The non-volatile memory according to claim 1, wherein the output of the first gate circuit is switched by a switching signal applied to a third external terminal. 3. The nonvolatile memory according to claim 1, wherein the output of the second gate circuit is switched by a switching signal applied to a fourth external terminal. 4. In a test mode for testing a nonvolatile memory cell, the switching signal for controlling the first gate circuit is applied to the third external terminal,
3. The non-volatile memory according to claim 2, wherein the output of the gate circuit is switched from the output of the counter to the timing signal. 5. In a test mode for testing a non-volatile memory cell, the switching signal for controlling the second gate circuit is applied to the fourth external terminal,
4. The nonvolatile memory according to claim 3, wherein the output of the gate circuit is switched from the output of the counter to the timing signal. 6. A microcomputer including the nonvolatile memory according to claim 1.