JP2002108716A - Nonvolatile semiconductor memory and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory which has constitution capable of protecting stored data almost completely by being combined with constitution for performing, specially, ciphering processing and its control method. SOLUTION: The nonvolatile semiconductor memory and its control method are characterized by that the readout frequencies of data stored in memory cells at respective addresses are limited to a preset specific readout frequency and data in a memory cell at an address where data are read out at the specific readout frequency are erased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device and a control method thereof.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory devices that retain stored data even when the power is turned off have been widely used for various purposes.

In addition, various types of nonvolatile semiconductor memory devices having a configuration in which a security area is provided in a device and a password is collated to perform an encryption process for prohibiting unauthorized access to a memory cell in the device are provided. Things are used depending on the application.

[0004]

However, no matter what encryption processing is performed, there is a possibility that data may be read or copied by unauthorized access as long as the stored data is retained. Still exists.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a structure capable of almost completely protecting stored data by combining it with a structure for performing an encryption process. An object of the present invention is to provide a nonvolatile semiconductor memory device and a control method thereof.

[0006]

According to the nonvolatile semiconductor memory device of the present invention, the number of times of reading data stored in a memory cell at each address is limited to a predetermined number of times of reading. The method is characterized in that data of a memory cell at an address at which data reading of a predetermined number of times has been completed is erased.

According to the first specific configuration of the nonvolatile semiconductor memory device according to the present invention, the number of address signals provided corresponding to the addresses of the memory cells, respectively, designates the addresses of the respective memory cells. Is input, a chip enable signal for controlling whether or not access to the memory cell is possible, and an output enable signal for controlling whether or not data read from the memory cell is output to the outside. And an OR logic gate that is activated by the input of the decode address signal and outputs an output signal corresponding to the chip enable signal and the output enable signal, and that data reading from the memory cell is completed. An output enable signal changes from a first logic level to a second logic level Thereby, in response to an input as a trigger of a pulse edge at which the output signal of the OR logic gate changes from the first logic level to the second logic level, boosting for erasing data of the memory cell at the address is performed. A logic circuit for outputting a voltage generation command signal, a boosted voltage generation circuit for generating a boosted voltage for erasing data in the memory cell at the address according to the boosted voltage generation command signal, and completion of one data read A memory cell array in which data is erased from the memory cell by the boosted voltage, and a transfer gate that outputs data read from the memory cell to a data output node in response to the output enable signal. It is characterized by having.

[0008] This configuration can protect the stored data almost completely, especially when combined with a configuration for performing an encryption process.

According to the second specific configuration of the nonvolatile semiconductor memory device according to the present invention, the number of address signals provided corresponding to the addresses of the memory cells, respectively, designates the addresses of the respective memory cells. Is input, a chip enable signal for controlling whether or not access to the memory cell is possible, and an output enable signal for controlling whether or not data read from the memory cell is output to the outside. An OR logic gate that is activated by the input of the decode address signal and outputs an output signal corresponding to the chip enable signal and the output enable signal; and a plurality of OR logic gates corresponding to the addresses of the memory cells. , The data reading from each of the memory cells is completed, and the When the reset enable signal changes from the first logic level to the second logic level, the output signal of the OR logic gate changes from the first logic level to the second logic level. A counter that counts up and outputs a count value, a read count setting register that sets the number of times data can be read from each of the memory cells, a read count setting register that outputs the count value, A comparator for comparing the read count set in the read count setting register and outputting a match or mismatch comparison result signal; and a data eraser for erasing data in the memory cell at the address according to the input of the match comparison result signal. And a logic circuit for outputting a boosted voltage generation command signal, and the address corresponding to the boosted voltage generation command signal. A boosted voltage generating circuit for generating a boosted voltage for erasing data from a memory cell; a memory cell array for performing data erasing by the boosted voltage on a memory cell after the completion of data reading of the read number; and an output enable signal. And a transfer gate for outputting data read from the memory cell to a data output node.

[0010] With this configuration, it is possible to set an appropriate number of times of reading according to the application, and it is possible to almost completely protect the stored data by combining it with a configuration that particularly performs an encryption process.

According to the method of controlling a nonvolatile semiconductor memory device of the present invention, the number of times of reading data stored in the memory cell at each address is limited to a predetermined number of times of reading, and It is characterized by erasing data in a memory cell at an address where data reading has been completed a number of times.

According to a first specific configuration of the method for controlling a nonvolatile semiconductor memory device according to the present invention, a step of reading data from a memory cell at an address designated by a decode address signal; Generating a boosted voltage for erasing data from the memory cell at the address after ending data reading from the memory cell, and erasing data by applying a data erase voltage pulse based on the boosted voltage to the memory cell at the address. And a step.

This configuration can protect the stored data almost completely, especially in combination with the configuration for performing the encryption process.

According to a second specific structure of the method for controlling a nonvolatile semiconductor memory device according to the present invention, a step of reading data from a memory cell at an address designated by a decode address signal; After the completion of the data reading, the step of counting up the count value of the number of times of reading data from the memory cell at the address by one, and comparing the count value with a predetermined number of times of reading set in advance. Generating a boosted voltage for erasing data from the memory cell at the address when the data match, and applying a data erase voltage pulse based on the boosted voltage to the memory cell at the address to erase data. It is characterized by having.

According to this configuration, it is possible to set an appropriate number of times of reading according to the application, and it is possible to almost completely protect stored data by combining it with a configuration for performing an encryption process.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a nonvolatile semiconductor memory device and a control method therefor according to the present invention will be described below with reference to the drawings.

A nonvolatile semiconductor memory device and a method of controlling the same according to the present invention limit the number of times of reading data stored in a memory cell to a predetermined number of times, and when the number of times of reading reaches the predetermined number of times, The feature is that data is erased.

FIG. 1 is a block diagram showing a configuration of a main part (FIG. 1A) and a whole (FIG. 1B) of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. .

FIG. 1 is a block diagram showing the entire configuration of the nonvolatile semiconductor memory device according to the first embodiment of the present invention, including the essential parts.
As shown in (b), the input address signal ADDRESS
From an address decoder 11 which decodes an address signal specifying the address of a memory cell, a chip enable signal CE for controlling whether or not to access the memory cell, and a memory cell. An output enable signal OE that controls whether read data can be output to the outside, a write enable signal WE that controls whether data can be written into and erased from each memory cell, and batch data writing and writing can be performed on all memory cells. A control circuit 12 for outputting a control signal for controlling the operation of the entire device in response to the input of a bulk enable signal BE for controlling whether batch data erasure is possible and a clock signal CLK for controlling each operation timing; Depending on the input, data write and data erase Boosted voltage V for generating a voltage VPP
It comprises a PP generation circuit 13 and a memory cell array 14 in which data writing, data reading and data erasing are performed in accordance with the input of a decode address signal, a control signal and a boosted voltage VPP.

The overall configuration of the nonvolatile semiconductor memory device shown in FIG. 1B is similar to that of a normal nonvolatile semiconductor memory device. The structural features of the nonvolatile semiconductor memory device according to the first embodiment of the present invention are as follows.
This is shown in the configuration of the main part of FIG.

The main parts of the nonvolatile semiconductor memory device according to the first embodiment of the present invention shown in FIG. 1A are provided in a number corresponding to the address of the memory cell.
A decode address signal obtained by decoding an address signal designating the address of each memory cell, a chip enable signal CE for controlling whether or not the memory cell can be accessed, and whether or not data read from the memory cell can be output to the outside And an OR logic gate 1 which is activated by the input of the decode address signal and outputs an output signal corresponding to the chip enable signal CE and the output enable signal OE, When the data reading of
That is, when the output enable signal OE changes from the first logic level (here, L (Low) level) to the second logic level (here, H (High) level), the output signal of the OR logic gate 1 is changed. In response to an input as a trigger of a pulse edge changing from the first logic level to the second logic level, a boosted voltage VPP generation command signal for erasing data of a memory cell at an address designated by a decode address signal is output. Flip-flop 2
A boosted voltage VPP generating circuit 13 for generating a boosted voltage VPP for erasing data from the memory cell at the above address in response to a boosted voltage VPP generation command signal, and a boosted voltage VPP for a memory cell after one data read is completed. And a transfer gate 3 that outputs data read from a memory cell to a data output node OUT in response to an output enable signal OE.

OR logic gate 1 and flip-flop 2
Is, for example, the control circuit 12 in FIG.
Can be included.

In the nonvolatile semiconductor memory device and the control method therefor according to the first embodiment of the present invention, the number of times of reading data stored in a memory cell is limited to one, and after one data reading is completed, It is characterized in that data in a memory cell is erased.

FIG. 2 shows a procedure of a method for controlling the nonvolatile semiconductor memory device according to the first embodiment of the present invention, that is, the operation of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 3 is a timing chart showing main signal waveforms at the time of data reading and data erasing after data reading in the nonvolatile semiconductor memory device and the control method thereof according to the first embodiment of the present invention. It is a chart.

Hereinafter, referring to FIGS. 1, 2 and 3, the procedure of the control method of the nonvolatile semiconductor memory device according to the first embodiment of the present invention, that is, the first embodiment of the present invention will be described. An operation of the nonvolatile semiconductor memory device according to the embodiment will be described.

At timing A, when a decode address signal decoded by the address decoder 11 is input to the control circuit 12 and the chip enable signal CE and the output enable signal OE go to L level (step S1), the decoded address becomes Data is read from the memory cell at the address specified by the signal (step S2). When the output enable signal OE goes low, the transfer gate 3 is turned on, and data read from the memory cell is output to the data output node OUT via the transfer gate 3. The data read operation is
The process is performed until the data reading from the memory cell at the above address is completely completed (step S3).

At this time, the OR logic gate 1 corresponding to the decode address signal is activated and the chip enable signal CE and the output enable signal OE are at the L level, so that the output signal of the OR logic gate 1 is It is at L level. In addition, flip-flop 2
Is also at the L level, so that the boosted voltage VPP
The output of the generation circuit 13 is a non-boosted voltage (here, for example, 5
V).

When the output enable signal OE changes from the L level to the H level at the timing B after the data reading from the memory cell is completed, the output signal of the OR logic gate 1 activated by the decode address signal changes to the L level. Level to the H level, and the rising edge of the clock node CLKF of the flip-flop 2
Is input as a trigger to the flip-flop 2
Outputs to the boosted voltage VPP generation circuit 13 a boosted voltage VPP generation command signal for erasing data from the memory cell at the address specified by the decode address signal. In response to the boosted voltage VPP generation command signal, the boosted voltage VPP generation circuit 13 generates a boosted voltage VPP (here, for example, 12 V), and erases data based on the boosted voltage VPP in a memory cell at an address specified by the decode address signal. When data erase is performed by applying a voltage pulse (step S4),
The procedure of the method for controlling the nonvolatile semiconductor memory device according to the first embodiment of the present invention, that is, the operation of the nonvolatile semiconductor memory device according to the first embodiment of the present invention ends.

As described above, the nonvolatile semiconductor memory device and the control method thereof according to the first embodiment of the present invention limit the number of times of reading data stored in a memory cell to one, and Since the data in the memory cell is erased after the completion of the data reading, the stored data can be almost completely protected by combining it with a configuration for performing an encryption process in particular.

FIG. 4 is a block diagram showing a configuration of a main part of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. Note that the entire configuration of the nonvolatile semiconductor memory device according to the second embodiment of the present invention is the same as that shown in FIG.

The essential parts of the nonvolatile semiconductor memory device according to the second embodiment of the present invention shown in FIG. 4 are provided in a number corresponding to the address of the memory cell, and each designates the address of each memory cell. Address signal obtained by decoding an address signal to be read, a chip enable signal CE for controlling whether or not access to a memory cell is possible, and an output enable signal for controlling whether or not data read from the memory cell can be externally output OE is entered,
An OR logic gate 1 that is activated by the input of the decode address signal and outputs an output signal corresponding to the chip enable signal CE and the output enable signal OE;
The number corresponding to the address of the memory cell is provided,
When the data read from the memory cell is completed, that is, when the output enable signal OE is changed from the first logical level (here, L (Low) level) to the second logical level (here, H (High) level). And a counter 4 that counts up and outputs a count value in response to an input as a trigger of a pulse edge at which the output signal of the OR logic gate 1 changes from the first logic level to the second logic level. The number-of-reads setting register 5 that sets the number of times that data can be read from each memory cell is set, and the count value output from the counter 4 is compared with the number of reads set in the number-of-reads setting register 5, Or a comparator 6 that outputs a mismatched comparison result signal
A flip-flop 2 for outputting a boosted voltage VPP generation command signal for erasing data from a memory cell at an address designated by a decode address signal in response to the input of a match comparison result signal; In response to the above, a boosted voltage VPP generating circuit 13 for generating a boosted voltage VPP for erasing data of the memory cell at the address, and data erasing by the boosted voltage VPP is performed on the memory cell after the completion of the data reading of the number of times of reading. In response to the memory cell array 14 and the output enable signal OE, the data read from the memory cell is output to the data output node O.
And a transfer gate 3 for outputting to the UT.

The OR logic gate 1, counter 4, read count setting register 5, comparator 6, and flip-flop 2 are, for example, the control circuit 1 shown in FIG.
2 can be configured.

The nonvolatile semiconductor memory device and the method of controlling the same according to the second embodiment of the present invention reduce the number of times of reading data stored in a memory cell to the number of times of reading set in advance in the number-of-reads setting register 5. The feature is that data is erased from the memory cell after the data reading of the number of times of reading is completed.

FIG. 5 shows a procedure of a method for controlling a nonvolatile semiconductor memory device according to the second embodiment of the present invention, that is, an operation of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. It is a flowchart shown.

Note that the main signal at the time of the last data reading and the data erasing after the data reading set in the nonvolatile semiconductor memory device and the control method thereof according to the second embodiment of the present invention. The timing chart showing the waveform is similar to the timing chart of FIG. As will be described later, at the end of data reading other than the last of the set reading times, the timing B shown in FIG.
As shown in (2), the boosted voltage VPP is not boosted from the non-boosted voltage to the boosted voltage.

Hereinafter, the procedure of the control method of the nonvolatile semiconductor memory device according to the second embodiment of the present invention, that is, the second embodiment of the present invention will be described with reference to FIGS. An operation of the nonvolatile semiconductor memory device according to the embodiment will be described.

At timing A, when the decoded address signal decoded by the address decoder 11 is input to the control circuit 12 and the chip enable signal CE and the output enable signal OE go to L level (step S11), the decoded address becomes Data is read from the memory cell at the address specified by the signal (step S12). When the output enable signal OE goes low, the transfer gate 3 is turned on, and data read from the memory cell is output to the data output node OUT via the transfer gate 3. The data read operation is performed until the data read from the memory cell at the above address is completely completed (step S13).

At this time, the OR logic gate 1 corresponding to the decode address signal is activated, and the chip enable signal CE and the output enable signal OE are at the L level. It is at L level. Also, as described later, unless a comparison result signal of a match is input from the comparator,
Since the output signal of the flip-flop 2 is also at the L level, the output of the boosted voltage VPP generation circuit 13 is a non-boosted voltage (here, for example, 5 V).

When the output enable signal OE changes from the L level to the H level at the timing B after the data reading from the memory cell is completed, the output signal of the OR logic gate 1 activated by the decode address signal changes to the L level. When the level changes from the level to the H level and the rising edge is input to the clock node CLKC of the counter 4 as a trigger, the counter 4 counts up the count value by 1 and outputs it to the comparator 6 (step S14).

The comparator 6 compares the number of readings set in the reading number setting register 5 in advance with the count value output from the counter 4 (step S15). If the comparison results in a mismatch, the comparison of the mismatch is performed. The output signal at L level, which is the result signal, is continuously output to flip-flop 2. Therefore, the output signal of flip-flop 2 also remains at L level, so that boosted voltage VPP generating circuit 13
Is a non-boosted voltage (here, for example, 5 V). The fact that the result of the comparison does not match means that the number of times of reading has already reached the set number of times of reading,
Since it means that data can still be read from the memory cell at the above address, the procedure of the device control method, that is, the operation of the device returns to the beginning and repeats the above steps 11 to 15 (step S16).

On the other hand, when the result of the comparison is a match, the comparator 6 switches the L-level output signal that is the mismatched comparison result signal to the H-level output signal that is the matched comparison result signal, and 2 is output (step S16). When the output signal of the comparator 6 switches from the L-level mismatched comparison result signal to the H-level matched comparison result signal, and its rising edge is input to the clock node CLKF of the flip-flop 2 as a trigger, the flip-flop 2 A boosted voltage VPP generation command signal for erasing data from the memory cell at the address specified by the decode address signal is output to boosted voltage VPP generation circuit 13. In response to the boosted voltage VPP generation command signal, the boosted voltage VPP generation circuit 13 generates a boosted voltage VPP (here, for example, 12 V), and erases data based on the boosted voltage VPP in a memory cell at an address specified by the decode address signal. When data is erased by applying a voltage pulse (step S17), the procedure of the method for controlling the nonvolatile semiconductor memory device according to the second embodiment of the present invention, that is, the second embodiment of the present invention The operation of the nonvolatile semiconductor memory device ends.

As described above, in the nonvolatile semiconductor memory device and the control method thereof according to the second embodiment of the present invention, the read number of data stored in the memory cell is stored in advance in the read number setting register 5. Since the data of the memory cell is erased after the data read of the set number of times is restricted, the appropriate number of times of read depending on the use can be set, and in particular, the encryption processing is performed. In combination, the stored data can be almost completely protected.

[0043]

According to the nonvolatile semiconductor memory device and the control method therefor of the present invention, the number of times of reading data stored in the memory cell at each address is limited to a predetermined number of times of reading. Since the data in the memory cell at the address at which the data reading for the predetermined number of readings has been completed is erased, the stored data can be almost completely protected by combining it with a configuration for performing the encryption process in particular.

[Brief description of the drawings]

FIG. 1 is an essential part (FIG. 1A) and an entire part (FIG. 1) of a nonvolatile semiconductor memory device according to a first embodiment of the present invention;
FIG. 3B is a block diagram illustrating the configuration of FIG.

FIG. 2 is a flowchart showing a procedure of a control method of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing main signal waveforms at the time of data reading and data erasing after data reading in the nonvolatile semiconductor memory device and the control method therefor according to the first embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of a main part of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a flowchart showing a procedure of a control method of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 OR logic gate 2 flip-flop 3 transfer gate 4 counter 5 read count setting register 6 comparator 11 address decoder 12 control circuit 13 boosted voltage VPP generation circuit 14 memory cell array

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 17/00 632Z

Claims (6)

[Claims] The number of times of reading data stored in a memory cell of each address is limited to a predetermined number of times of reading set in advance, and data of a memory cell of an address where data reading of the predetermined number of times of reading has been completed is limited. A nonvolatile semiconductor memory device characterized by erasing. A decoding address signal provided by decoding an address signal designating the address of each of the memory cells; and controlling whether or not the memory cell can be accessed. A chip enable signal, and an output enable signal for controlling whether or not data read from the memory cell can be output to the outside is input, activated by the input of the decode address signal, and the chip enable signal and An OR logic gate for outputting an output signal corresponding to the output enable signal; and when data reading from the memory cell is completed, the output enable signal changes from a first logic level to a second logic level. Whether the output signal of the OR logic gate is the first logic level A logic circuit for outputting a boosted voltage generation command signal for erasing data from the memory cell at the address in response to an input as a trigger of a pulse edge changing from the boosted voltage generation command to the second logic level; A boosted voltage generating circuit for generating a boosted voltage for erasing data in the memory cell at the address in accordance with a signal; and performing data erasing by the boosted voltage on the memory cell after one end of data reading. A nonvolatile semiconductor memory device, comprising: a memory cell array; and a transfer gate that outputs data read from the memory cell to a data output node in response to the output enable signal. 3. A decode address signal, which is provided in a number corresponding to the address of the memory cell, is provided by decoding an address signal designating the address of each memory cell, and controls whether the memory cell can be accessed. A chip enable signal, and an output enable signal for controlling whether or not data read from the memory cell can be output to the outside is input, activated by the input of the decode address signal, and the chip enable signal and An OR logic gate for outputting an output signal in accordance with the output enable signal; and a plurality of logic gates corresponding to the addresses of the memory cells, each of which is provided with data output from each of the memory cells. The enable signal changes from a first logic level to a second logic level A counter that counts up and outputs a count value in response to an input as a trigger of a pulse edge at which the output signal of the OR logic gate changes from the first logic level to the second logic level. A read count setting register for setting a read count at which data can be read from each of the memory cells, and comparing the count value output from the counter with the read count set in the read count setting register; A comparator that outputs a match or mismatch comparison result signal; a logic circuit that outputs a boost voltage generation command signal for erasing data from the memory cell at the address in response to the input of the match comparison result signal; A boosted voltage generator for generating a boosted voltage for erasing data in the memory cell at the address according to a voltage generation command signal A circuit, a memory cell array in which data is erased by the boosted voltage from the memory cell after the data read of the read number is completed, and a data output from the memory cell in response to the output enable signal And a transfer gate for outputting to a node. 4. The method according to claim 1, wherein the number of times of reading data stored in the memory cell at each address is limited to a predetermined number of times of reading, and the data of the memory cell at the address where the data reading of the predetermined number of times of reading is completed. A method for controlling a nonvolatile semiconductor memory device, characterized by erasing. 5. A step of reading data from a memory cell at an address designated by a decode address signal, and after finishing reading data from the memory cell, increasing a boosted voltage for erasing data in the memory cell at the address. Generating a data erasing voltage pulse based on the boosted voltage to a memory cell at the address to perform data erasing, and controlling the nonvolatile semiconductor memory device. 6. A step of reading data from a memory cell at an address specified by a decode address signal, and after finishing reading data from the memory cell, setting a count value of the number of times of reading data from the memory cell at the address to 1 Counting up, and comparing the count value with a predetermined number of readouts set in advance, and when the result of the comparison is equal, generating a boosted voltage for erasing data from the memory cell at the address. A method of erasing data by applying a data erasing voltage pulse based on the boosted voltage to a memory cell at the address.