JP3482762B2 - Power module stack - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial circuit 2 of a bridge circuit composed of high power semiconductor amplifying functional elements (power semiconductor elements) in an output circuit of an inverter.
The power module stack forming the side, in particular,
The present invention relates to a power module stack having improved high-speed switching characteristics of a large-power power module optimally connected in parallel for a large-capacity inverter.

[0002]

2. Description of the Related Art A general inverter circuit that outputs three-phase alternating current is formed as shown in FIG. In the DC / AC converter of the inverter, as shown in FIG. 3, for each phase of AC, the load is connected from the connection point of each pair of power semiconductor amplification functional elements (referred to as power amplification functional element) connected in series. When connecting in parallel to the power supply circuit of the corresponding phase and supplying power to the load, the conduction and non-conduction of the power amplification function element of the predetermined phase are alternately controlled according to the phase relationship of the AC frequency. There is. That is, in the case of a three-phase AC load, the U-phase power amplification function elements 1UU and 1UD are connected in series and connected between the positive power supply circuit P and the negative power supply circuit N, and the power amplification function elements 1UU and U of load 2 from the connection point of 1UD
1VU and 1VD for V phase power amplification function element connected to the phase
Are connected in series and are connected between the positive power supply circuit P and the negative power supply circuit N, and the power amplification function elements 1VU and 1VD are connected.
Is connected to the V phase of the load 2 from the connection point of, and the W phase power amplification function elements 1WU and 1WD are connected in series and connected between the positive power supply circuit P and the negative power supply circuit N to obtain the power amplification function. The connection point between the elements 1WU and 1WD is connected to the W phase of the load 2. Also, each power amplification function element 1UU, 1U
D, 1VU, 1VD, 1WU, and 1WD are respective power amplification function elements 1U connected in series by driver elements 3UU, 3UD, 3VU, 3VD, 3WU, and 3WD.
It is controlled so that U and 1UD, 1VU and 1VD, 1WU and 1WD do not turn on at the same time, and appropriate three-phase power is supplied to the load. Driver element 3UU, 3UD, 3V
U, 3VD, 3WU, and 3WD are controlled by the control circuit 4 so as to output the above-mentioned control signals. The control circuit 4 includes current command signals iUS, i for the load phases U, V, W.
Signal lines input to VS and iWS are connected from a host controller (not shown). Further, the inverter circuit is provided with a feedback circuit that detects the currents of the load phases U, V, and W and returns them to the control circuit 4.

In the above-mentioned circuit configuration, a general inverter uses a semiconductor switching element having a high-speed switching characteristic as a power amplification functional element, and outputs a pulse having a width proportional to the output amplitude of a sine wave shape. Is used, and a large-capacity electrolytic capacitor 5 is connected in parallel between the positive power supply circuit P and the negative power supply circuit N in the power supply circuit in order to reduce the influence of high power switching. That is, in the control circuit 4, the current command signal i
The US, iVS, and iWS values are compared with the load current value of each phase, and PWM is performed so that the load current value matches the value of the command signal.
The switching signal of the method is created, and each driver element 3
It supplies to UU, 3UD, 3VU, 3VD, 3WU and 3WD.

Next, an example of a high power inverter will be described with reference to FIG. 4, which shows in detail a part of the inverter circuit shown in FIG. In FIG. 4, 1U1 to 1U4 and 1D1 to 1
D4 is a power semiconductor amplification function element (hereinafter referred to as a power semiconductor element) 1UU, 1UD, 1VU, 1VD, 1WU, 1W for power supply having the three-phase high-speed switching characteristic shown in FIG.
The power semiconductor elements connected in series for one phase of D are shown. The power semiconductor element connected to the positive power supply circuit P side and the power semiconductor element connected to the negative power supply circuit N side are output power. In this example, four elements are connected in parallel in accordance with the power characteristics of the power semiconductor elements. 3U is a driver function element of four power semiconductor elements 1U1 to 1U4 connected in parallel, and 3D is a driver function element of four power semiconductor elements 1D1 to 1D4 connected in parallel. The illustration of the control circuit (reference numeral 4 shown in FIG. 3) connected to the 3D is omitted. Also, 5U1-5U5 and 5D1-5D5 are
An electrolytic capacitor is normally used as a capacitor connected between the positive power supply circuit P and the negative power supply circuit N. In this example, five electrolytic capacitors (in parallel with each other) are connected in correspondence with the power supply voltage and the required capacitance. (Hereinafter referred to as capacitors) will be connected in series. Each capacitor 5U1
A resistor 6 for voltage balancing is connected to each of ~ 5U5 and 5D1-5D5. Also, 7U1-7U
4 and 7D1 to 7D4 are power semiconductor elements 1U1 respectively.
The snubber module for stable operation compensation is connected in parallel between the collector and emitter terminals of 1U4 and 1D1 to 1D4. The high power inverter includes a fan 8 for preventing a temperature rise due to heat generation of each power semiconductor element.
Is provided. In addition, 8M is a motor for driving the fan 8. Descriptions other than the main functions described above will be omitted.

Power semiconductor devices 1UU, 1UD, 1VU, 1VD, 1WU used in the above-mentioned inverters, etc.
At present, a power module having an insulated gate bipolar transistor (hereinafter referred to as IGBT) having a shape as shown in FIG. 5 is used as an optimum semiconductor element for 1WD. In FIG. 5, FIG. 5A is an equivalent circuit of an IGBT which is a power semiconductor element having high-speed switching characteristics configured inside a power module, FIG. 5B is a plan view, and FIG. The figure and the same figure (D) are side views. In each figure, C is a collector terminal, E is an emitter terminal, G is a gate terminal, and e is an emitter terminal paired with the gate terminal G and connected to the driver element. or,
B indicates the bottom of the power module, which is bolted to a predetermined mounting mechanism having a heat sink structure forcibly cooled by the fan 8 by a mounting hole b.
A shown in FIG. 6 (C) is a nameplate indicating the name, main standard, etc. of this power module.

Next, a conventional example in which the power module shown in FIG. 5 is mounted on the circuit shown in FIG. 4 will be described with reference to FIG. As shown in FIG. 4, FIG. 6 configures a circuit for connecting one phase of the inverter output circuit in the bridge connection, which is connected in series and has a power amplification function element (IGBT shown in FIG. 5, hereinafter referred to as a power module) related circuit. A power module stack (hereinafter abbreviated as a stack) is shown, and the same reference numerals as those in FIG. FIG. 6 (A) is a side view showing the stack except the case, and FIG. 6 (B) is a sectional view taken along line XX ′ of FIG. 6 (A). In FIG. 6, 3 is a driver module in which the driver function element 3U of four power modules 1U1 to 1U4 connected in parallel and the driver function element 3D of four power modules 1D1 to 1D4 connected in parallel are integrally configured. is there. Also, 10 GU
1 to 10GU4 are twisted wires connecting the respective gate terminals G and emitter terminals e of the four power modules 1U1 to 1U4 connected in parallel to the corresponding output terminals of the driver module, and 10GD1 to 10GD4 are parallel wires. It is a twisted wire that connects the respective gate terminals G and emitter terminals e of the four connected power modules 1D1 to 1D4 and the corresponding output terminals of the driver module. 10R is four power modules 1U1 to 1U4 connected in parallel and four power modules 1D1 to 1D4 connected in parallel.
The output circuit connected to the load is a copper plate that constitutes a output circuit by connecting a series connection part of the and.
Also, the collector terminals C of the power modules 1U1 to 1U4
Is a positive power circuit P (not shown) made of a copper plate 10P,
The power modules 1D1 to 1D4 are connected to the positive terminals of the five capacitors 5U1 to 5U5 connected in parallel.
The emitter terminal E of is a copper plate 10N and a minus power supply circuit N (not shown), and five capacitors 5 connected in parallel.
It is connected to each minus terminal of D1-5D5. Furthermore, five capacitors 5D connected in parallel with the respective negative terminals of the five capacitors 5U1 to 5U5 connected in parallel.
The positive terminals 1 to 5D5 are connected by a copper plate 10C. Further, 11 is an insulating plate for preventing contact with the copper plates 10R, 10P and 10C formed in parallel with the copper plate 10N. Four power modules 1U1 to 1 connected in parallel at the top of the circuits shown in FIGS.
U4 and the bottom B of each of the four power modules 1D1 to 1D4 connected in parallel at the bottom of the circuit are coupled to a structure 12 having a heat sink function, and the structure 12 is forcibly cooled by a fan 8. In FIG. 6 (A),
Reference numeral 1U indicates a row of power modules 1U1 to 1U4, 1D indicates a row of power modules 1D1 to 1D4, 7U indicates a row of snubber modules 7U1 to 7U4, and 7D indicates a row of snubber modules 7D1 to 7D4.

The structure of the power module as described above is disclosed in, for example, Japanese Patent Application Laid-Open Nos. 6-89954 and 7-.
2018895, JP-A-7-249716,
Each of them is described in JP-A-7-240497. Japanese Patent Laid-Open No. 6-89954 discloses a semiconductor module in which a heat diffusion plate and an insulating plate are laminated below a semiconductor chip, and the final support plate is laminated inside the semiconductor module. And 2.5 times or more of the maximum thickness of the insulating plate. In addition, JP-A-7
In the semiconductor device including a semiconductor element, a metal heat dissipation plate, a thermal stress relaxation material, an insulating substrate, a metal support plate, and the like, at least one member of the metal heat dissipation plate and the metal support plate is disclosed in JP-A-2018895. It is characterized by using a Cu alloy having a softening temperature of 350 ° C. or higher at which the material hardness at high heat is ½ of the hardness at room temperature. Further, in the one disclosed in Japanese Patent Laid-Open No. 7-249716, a semiconductor chip is directly fixed to the bottom surface of an external main electrode, and two external main electrodes made of copper having different polarities are arranged coaxially with each other with an insulating layer interposed therebetween. Has been done. JCR on the surface of the semiconductor chip
The heat dissipation plate made of copper faces each other with the encapsulation resin made of epoxy resin and the encapsulation resin of epoxy resin sandwiched, and the heat loss from the semiconductor chip is mainly radiated to the external main electrode and also from the surface of the semiconductor chip. The heat is dissipated to the heat sink. Since the external main electrode is coaxial, the inductance is canceled out. Further, the one disclosed in Japanese Patent Application Laid-Open No. 7-240497 has an insulating metal plate that supports semiconductor chips interconnected in a package with a high power semiconductor module, and the terminal plate is connected to the substrate in a snap action manner. For supporting a plurality of terminals, the terminals being arranged on each soldering pad on the insulating metal plate. The space between the insulating metal plate and the terminal plate is filled with soft silicon from the central opening of the terminal plate, and the terminal plate has a plurality of bosses that extend upward. It is surrounded by the upper part of the board.

[0008]

By the way, the stack structure as described with reference to FIG. 6 causes many problems as described below. The twisted wires 10GU1 to 10GU4 connecting the respective gates G of the power modules 1U1 to 1U4 on the side connected to the positive power supply circuit P and the driver function elements 3U are connected to the negative power supply circuit N on the side connected to the power modules 1D.
Since it passes each side of 1 to 1D4 and below the copper plate 10R connected to the load, it is susceptible to malfunction due to the influence of induced noise from the main circuit current. Since the direction of the cooling air by the fan is the same as the parallel direction of the power modules, the power modules on the leeward side are affected by the heat radiation on the windward side, and the power modules 1U1 to 1U4 and 1D1 to 1D4 connected in parallel are connected. Thermal imbalance occurs between the respective power modules, which may cause imbalance in the load current load of each power module due to the temperature characteristics of each power module. Since the twisted wires 10GU1 to 10GU4 connecting the respective gates G of the power modules 1U1 to 1U4 on the side connected to the plus power supply circuit P and the driver function element 3U are long, the inductance of the wiring is increased and the gate current is increased. It is easy to vibrate and malfunction. The copper plate 10R connected to the load is each power module 1U
1 to 1U4 and 1D1 to 1D4 are connected to each power module 1U1 so as to be connected outward from the respective arrangement directions.
~ 1U4 and 1D1 to 1D4 cause imbalance in respective output currents. As described above, if there is a risk of imbalance in the load current load of each power module, a characteristic change inevitably occurs due to the difference in heat generation. Therefore, power modules connected in parallel corresponding to all load current values It is necessary to increase the number. An object of the present invention is to solve the above-mentioned problems (problems) of conventional ones and to provide a power module stack having the following functions. (1) Ensure that the input line connected to the gate of each power module is not affected by the main circuit current. (2) Prevent thermal imbalance in each power module by the cooling air. (3) Make the input line connected to the gate of each power module short and uniform. (4) Allow the external connection from the center of the output copper plate to be connected to the load.

[0009]

In order to solve the above-mentioned problems, in a power module stack according to the present invention, a plurality of parallel connections forming each of two series sides of a bridge circuit in an output circuit of a large capacity inverter are connected. In a power module stack including a power semiconductor element and a peripheral circuit thereof, the power semiconductor elements connected in series are arranged in two rows with collector terminals facing each other and gate terminals opposite to each other. did. In this case, in the power module stack, it is preferable that the bottom of each power semiconductor is formed such that the ventilation direction of the heat sink structure, which is forcedly ventilated by the fan, is orthogonal to the power semiconductor element array. In addition, in the power module stack, an emitter terminal of each power semiconductor element forming an upper part of one side of each circuit connected in parallel by bridge connection and a lower part connected in series to each power semiconductor element forming the upper part are formed. The power semiconductor element has a gate connected to each collector terminal of the power semiconductor element, a copper plate forming an output circuit is connected in parallel to the surface of the power semiconductor element, and the output side of the output copper plate is connected to each emitter terminal. On the side, it is preferable that the heat sink structure is bent in the opposite direction to converge into an equilateral trapezoidal shape, and the external connection terminal portion is formed on the convergent portion.

In addition, a plurality of electrolytic capacitors connected in parallel between the positive power source and the negative power source are aligned in parallel with the power semiconductor element row, and each terminal of the electrolytic capacitors constitutes the negative power circuit. A structure formed by connecting to a copper plate that forms a positive power circuit and a copper plate that forms a positive power circuit,
A configuration in which a snubber module corresponding to each power semiconductor element is connected and formed via a conduit between the collector terminal and the emitter terminal of each power semiconductor element, and the driver element of each power semiconductor element is provided with each power semiconductor element. Various configurations are conceivable, such as a configuration in which the element array is formed outside on the gate terminal side. The power semiconductor element is preferably an IGBT (Insulated Gate Bipolor Transistor). Since the present invention is configured as described above, the input line connected to the gate of each power module will not be affected by the main circuit current, and the cooling air will not cause thermal imbalance in each power module. As a result, the input line connecting to the gate of each power module has become short and uniform, and it has become possible to connect from the center of the copper plate for output that connects to the load to the outside.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment to which the present invention is applied will be described in detail with reference to FIGS. 1 shows the structure of a stack in which the power module shown in FIG. 6 is mounted on the circuit shown in FIG. 5, and FIG. 2 is an exploded perspective view of the components shown in FIG. In FIG. 1, FIG. 1A is a side view of the stack, FIG. 1B is a side view seen from the right side of FIG. The illustration of the mounting structure is omitted because the description of the configuration based on the invention is complicated. 1 and 2,
Power modules 1U1 to 1U1 forming an upper side of a plurality of eight power semiconductor elements connected in parallel and forming two sides in series of a bridge circuit forming an inverter
U4 and power modules 1D1 to 1B that form the lower side
The bottom B of each 1D4 is coupled to a structure 22 having a heat sink function, and the structure 22 is forcedly ventilated by a fan 8. That is, the heat sink of the structure 22 has a fin structure so as to be cooled by the air blown in the lateral direction by the fan 8 as shown by the arrow in FIG. Therefore, the arrangement direction of the power module and the ventilation direction are orthogonal to each other. 1U and 1D shown in FIG. 1 (A) respectively show four power modules configured in parallel, and FIG. 1 (B) shows the power modules 1U1 to 1U4.
Are not shown hidden behind the front power modules 1D1-1D4. 3U is a driver module of four power modules 1U1 to 1U4 connected in parallel, and 3D is four power modules 1D1 to 1D4 connected in parallel.
Driver module. 20 GU is a twisted wire that connects the respective gate terminals G and the emitter terminals e of the four power modules 1U1 to 1U4 connected in parallel to the corresponding output terminals of the corresponding driver module, that is,
Of the input signal lines of the power modules 1U1 to 1U4, the one that appears closest to the front is shown in the figure. Similarly,
20GD is 4 power modules 1D connected in parallel
A twisted wire connecting each of the gate terminals G and emitter terminals e of 1 to 1D4 and the corresponding output terminals of the driver module, that is, one of the input signal wires of the power modules 1D1 to 1D4 which is the most visible in the figure. Is shown. That is, the driver module is arranged near the gate terminal on the gate terminal side of the corresponding power module. Eight power modules 1U1 to 1U4 and 1D1 each
The snubber modules 7U1 to 7U4 and 7D1 to 7D4 connected between the collector and the emitter of 1D4 respectively correspond to the power modules by passing through copper holes for connection and the insulating plate described later by copper conduits. It is connected to the terminal. 7A and 7D shown in FIG. 1 (A) show four snubber modules configured in parallel. In FIG. 1 (B), the snubber modules 7U1 to 7U4 correspond to the front snubber modules 7D1 to 7D4. Not shown hidden. In FIG. 2, illustrations other than the frontmost snubber modules 7U1 and 7D1 shown in FIG. 2 are omitted.

Reference numeral 20R is a copper plate forming an output circuit, and four power modules 1U1 to 1U4 connected in parallel,
Four power modules 1D1 to 1D4 connected in parallel
Bend at a right angle in the direction opposite to the structure 22 having the heat sink function on the side opposite to the power module from the surface connecting the series connection parts of the power modules to each power module,
It is formed in a trapezoidal shape of equal sides toward the terminal lead-out portion 30R. In FIG. 2, the illustration of the output circuit terminal lead-out portion 30R is omitted. Reference numeral 32 denotes a hole for penetrating the conduit 31 provided in the copper plate 20R, which has an inner diameter such that the conduit 31 does not come into contact with the hole. Two
0N is a copper plate forming a negative power supply circuit, and is connected to the emitter terminals E of the power modules 1D1 to 1D4, the negative power supply circuit N, and the respective negative terminals of the capacitors 5D1 to 5D5 forming five second capacitor rows connected in parallel. It is connected. The copper plate 20N is on the opposite side of the copper plate 20R that constitutes the output circuit for the power module,
From the surface connected to each power module, a terminal lead-out portion 30N that is bent at a right angle in a direction opposite to the structure 22 having a heat sink function and connected to each negative terminal of the capacitors 5D1 to 5D5 to connect a negative power supply circuit is provided. It is provided at a predetermined location. In FIG. 2, illustration of the minus power supply circuit terminal lead-out portion 30N is omitted. 33 is a copper plate 20
The connection portion provided at N is connected to each negative terminal of the capacitors 5D1 to 5D5. Reference numeral 34 is an opening portion provided so that each terminal of the capacitors 5U1 to 5U5 forming the first capacitor array and each plus terminal of the capacitors 5D1 to 5D5 do not come into contact with each other. 5U and 5D are five capacitors respectively arranged in parallel as shown in FIG.
In FIG. 2, the condenser 5 mounted at the farthest position in FIG.
Illustrations other than U5 and 5D5 are omitted.

Reference numeral 20P is a copper plate forming a positive power supply circuit, and is a collector terminal C of the power modules 1U1 to 1U4.
And a copper plate 20R which is connected to the plus power supply circuit P and each plus terminal of the five capacitors 5U1 to 5U5 connected in parallel and which constitutes an output circuit for the power module.
On the opposite side, from the surface connected to each power module, bend at a right angle to the direction opposite to the structure 22 having a heat sink function, and connect to each positive terminal of the capacitors 5U1 to 5U5 to connect a positive power supply circuit. Terminal extension 30
P is provided at a predetermined position. In FIG. 2, the illustration of the positive power supply circuit terminal lead-out portion 30P is omitted. Copper plate 20P
And collector terminal C of each power module 1U1 to 1U4
And are connected at a connecting portion 35 via a conduit 31, and further,
The corresponding terminals of the snubber module are connected. Reference numeral 36 denotes a connection portion provided on the copper plate 20P, which is capacitors 5U1 to 5U.
5 is connected to each positive terminal. Reference numeral 37 denotes an open hole portion, which is a power module 1D1 to 1D4 and a snubber module 7D.
The conduits 31 connecting 1 to 7D4 are provided so as not to come into contact with each other. 21A and 21B are insulating plates, which are a copper plate 20R forming an output circuit and a copper plate 20N forming a negative power source.
And to prevent the copper plate 20P forming a positive power source from coming into contact with each other. The insulating plates 21A and 21B have through holes 3 for penetrating a conduit connecting the collector terminals C of the power modules 1U1 to 1U4 and the snubber modules 7U1 to 7U4.
8. Opening hole 39a for penetration of a conduit connecting the snubber modules 7U1 to 7U4 of the power modules 1D1 to 1D4
And 39b, an opening 40 through which the negative terminals of the capacitors 5D1 to 5D5 pass, and an opening 41 through which the positive terminals of the capacitors 5D1 to 5D5 and the negative terminals of the capacitors 5U1 to 5U5 pass.

Reference numeral 20C is a copper plate, and five capacitors 5 are connected to the copper plate 20P forming the positive power supply circuit P.
Negative terminals of U1 to 5U5 and negative power supply circuit N
The positive terminals of the five capacitors 5D1 to 5D5 connected to the copper plate 20N forming the above are connected. Note that the connection copper plate 20C is not shown in FIG.

In each of the above drawings, only the range for explaining the basic technical idea of the present invention is described, and the parts such as the resistor 6 shown in FIG. 5 which may complicate the explanation of the basic structure of the present invention. Illustration is omitted. Therefore, for example, as described above, in FIG. 2, the negative terminals of the capacitors 5U1 to 5U5 forming the first capacitor row and the positive terminals of the capacitors 5D1 to 5D5 forming the second capacitor row are connected. The illustration of the copper plate 20C is also omitted. The above description shows the basic configuration for implementing the technical idea of the present invention and the embodiment for explaining the operation thereof, and was invented corresponding to the structure of the power module shown in FIG.
The above technical idea may be applied to other power modules having similar shapes.

[0016]

Since the present invention has the element functions as described above, it has the following excellent effects. Since the input line connected to the gate of each power module is arranged outside, the input line to the gate does not pass between the power modules and there is no fear of being affected by the main circuit current. Therefore, the input signal is not affected by noise and the inverter operates stably. Since the copper plate for output is bent and the input line to the gate is arranged outside, the gate circuit can be arranged close to the element, and therefore the input line connected to the gate of each power module can be made short and uniform. As a result, the impedance of the input circuit was low and uniform. Therefore, the input timing of the input signal to each power module connected in parallel to form an inverter matches the waveform, and the operation of each power module is balanced. Since the output copper plate connected to the load can be connected to the outside from the center, the current of the output circuit of each power module connected in parallel is balanced, and the operation of each power module is balanced. By bending the copper plate for output, the electrolytic capacitor can be arranged above the heat sinks, so that the ventilation for cooling the heat sinks is in the direction orthogonal to each power module row, and the cooling of each power module is uniform.
Therefore, since the operation of each power module is balanced, an efficient inverter can be formed. The inverter can be compactly configured with a small number of auxiliary functions for each element.

[Brief description of drawings]

FIG. 1 is a schematic assembly view showing a structure of a power module stack according to the present invention, FIG. 1 (A) is a front view of the power module stack, and FIG. 1 (B) is a right side view of the power module stack. .

FIG. 2 is an exploded perspective view of main parts constituting the power module stack shown in FIG.

FIG. 3 is a schematic circuit diagram illustrating a structure of an inverter for explaining the present invention and a conventional technique.

FIG. 4 is a schematic circuit diagram showing a configuration circuit of a power module stack which is a main function of an inverter for explaining the present invention and a conventional technique.

FIG. 5 is an explanatory diagram of a power module which is a main function of an inverter for explaining the present invention and a conventional technique, and FIG. 5A is an IGBT configured inside the power module.
FIG. 2B is a plan view, FIG. 2C is a front view, and FIG. 2D is a side view.

FIG. 6 is a schematic assembly view showing the structure of a conventional power module stack, FIG. 6 (A) is a side view of the power module stack, and FIG. 6 (B) is a sectional view taken along line XX ′ of FIG. It is a figure.

[Explanation of symbols]

1U (1U1 to 1U4); 1D (1D1 to 1D4): Power module 2: Load 3U (3U1 to 3U4); 3D (3D1 to 3D4): Driver module 5U (5U1 to 5U5); 5D (5D1 to 5D5): Electrolysis Capacitor 7U (7U1 to 7U4); 7D (7D1 to 7U4): Snubber module 8: Fan 22: Structure (heat sink function) 20GU, 20GD: Power module input signal line 20N: Copper plate 20P forming a negative power supply circuit: Positive power supply Copper plate 20R forming a circuit: Copper plates 21A, 21B forming an output circuit: Insulating plate 30N: Negative power supply circuit terminal lead-out portion 30P: Positive power supply circuit terminal lead-out portion 30R: Output circuit terminal lead-out portion 31: Conduit 36: Connection part to connect to the positive terminal of the capacitor

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 25/07 H01L 25/18

Claims (9)

(57) [Claims] 1. A plurality of parallel-connected power semiconductor elements (1U1), (1D1); (1) forming each of two series sides of a bridge circuit in an output circuit of a large capacity inverter.
U2), (1D2); (1U3), (1D3); (1U
4), (1D4) and power semiconductor devices (1U1), (1D1); (1U2), (1D) that are connected in series in a power module stack configured by its peripheral circuits.
2); (1U3), (1D3); (1U4), (1D
4) A power module stack characterized in that the collector terminals (C) face each other and the gate terminals (G) face each other and are arranged in two rows. 2. The power module stack according to claim 1, wherein a bottom portion (B) of each power semiconductor is forcedly ventilated by a fan (8).
A power module stack in which the ventilation direction of 2) is formed in a direction orthogonal to the power semiconductor element array. 3. The power module stack according to claim 1, wherein each power semiconductor element (1U) forms an upper part of one side of each circuit connected in parallel by bridge coupling.
1) to (1U4) emitter terminals (E) and power semiconductor elements (1U1) to (1U4) forming the above-mentioned upper portion, a power semiconductor element (1D1) forming a lower portion connected in series
To (1D4) each collector terminal (C) connection point, a copper plate (20R) forming an output circuit is connected in parallel with the surface of the power semiconductor element, and the output side of the output copper plate (20R) is connected to each emitter. On the gate side of the power semiconductor element connected to the terminal (E), the power module is bent in the opposite direction of the heat sink structure (22) and converges into an equilateral trapezoidal shape, and the external connection terminal portion (30R) is formed in the convergence portion. stack. 4. The power module stack according to claim 1, wherein a power semiconductor forming a lower portion of a series-connected power semiconductor element forming one side of each circuit connected in parallel by bridge coupling. Element (1D
1) to (1D4) emitter terminals (E) are respectively connected with copper plates (20N) forming a negative current circuit in parallel with the surface of the power semiconductor element, and the above-mentioned copper plates (20N) forming the negative power supply circuit are connected. The opposite side of the connection side is bent in the opposite direction of the heat sink structure (22) on the opposite side of the copper plate (20R) forming the output circuit to form an external connection terminal portion (30N) at a predetermined position, and the bridge is formed. To the collector terminals (C) of the power semiconductor elements (1U1) to (1U4) forming the upper part of the power semiconductor elements connected in series that form one side of each circuit that is coupled and connected in parallel,
A copper plate (20P) forming a positive power supply circuit is connected in parallel with the surface of the power semiconductor element, and the opposite side of the connection side of the copper plate (20P) forming the positive power supply circuit is a copper plate forming the output circuit. The opposite side of (20R) is bent in the opposite direction of the heat sink structure (22) to form an external connection terminal portion (30P) at a predetermined position, and a copper plate (20N) and a positive power supply circuit which constitute the negative power supply circuit are formed. Insulating plate (21) between the copper plate (20P)
A, 21B) sandwiching and forming a power module stack. 5. The power module stack according to claim 1, wherein a plurality of electrolytic capacitors (5U1) to (5U5) and (5D1) are connected in parallel between the positive power source and the negative power source. ) To (5D5) are arranged in parallel with the power semiconductor element row and each terminal of the electrolytic capacitor is a copper plate (20N) that constitutes the minus power supply circuit and a copper plate (20P) that constitutes a plus power supply circuit.
Power module stacks formed by connecting to each. 6. The power module stack according to claim 1, wherein each power semiconductor element (1U1), (1D1); (1U2), (1D2);
(1U3), (1D3); snubber modules corresponding to (1U4) and (1D4) are connected via a conduit between the collector terminal (C) and the emitter terminal (E) of each power semiconductor element. Formed power module stack. 7. The power module stack according to claim 1, wherein the driver element of each power semiconductor element is arranged outside the gate terminal (G) side of each power semiconductor element row. Power module stack formed in. 8. A plurality of electrolytic capacitors (5U1) to (5U5) and (5D1) to (5D5) according to claim 5.
Is a first electrolytic capacitor (5U1) connected in parallel to
(5U5) column and second electrolytic capacitors (5D1) to (5D5) column connected in parallel are aligned in parallel with the positive side terminals being the power semiconductor element side, respectively, to form a first electrolytic capacitor column. Capacitors (5U1) to (5U
Each positive terminal of 5) is connected to the copper plate (20P) that constitutes the above-mentioned positive power supply circuit, and each negative terminal of the electrolytic capacitors (5D1) to (5D5) that constitutes the second electrolytic capacitor array is connected to the above-mentioned negative power source. Each negative terminal of the electrolytic capacitors (5U1) to (5U5) that is connected to a copper plate (20N) that forms a circuit and that forms a first electrolytic capacitor line and an electrolytic capacitor (5D1) that forms a second electrolytic capacitor line A power module stack formed by connecting each of the positive terminals of (5D5) to (5D5) with a copper plate (20C) for intermediate connection. 9. A copper plate (20R) forming the output circuit according to claim 3, and a copper plate (20 forming a minus power supply circuit.
N), the copper plate (20P) and the insulating plates (21A), (21B) that compose the positive power supply circuit.
0R), (20N), and (20P), the terminal portions of the electronic components and the respective copper plates (20R), (20P), (20)
N), the penetrating part of the terminal not connected to N) and the insulating plate (21A),
(21B) A power module stack in which holes having a predetermined shape and a predetermined size are provided in the penetrating portions of the respective terminals (21B).