JP3482179B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device (hereinafter referred to as "memory"), and more particularly to a memory in which operation analysis from the outside is difficult.

[0002]

2. Description of the Related Art An IC card used for a financial card, a prepaid card, a point card, etc. causes a malfunction by applying a high voltage or a low voltage or applying a high-speed clock signal in order to decrypt an encryption key. It is exposed to various attacks such as performing behavior analysis. Recently, the operation flow is analyzed by comparing the operating current of the IC with the input / output data, and the change of the current with respect to the input data is captured and the value of the encryption key is estimated by a statistical method for analysis.
Finally, a method of stealing the private key has also appeared.

FIG. 2 is a circuit diagram showing an example of a conventional memory. This memory comprises a 4 × 4 (ie 16 bits) memory block 10. Memory block 10
Are four bit line pairs (BLi, /
BLi) (where i = 0 to 3 and “/” means inversion) and 4 arranged to intersect these bit line pairs.
It has book word lines WLj (where j = 0 to 3). Bit line pair (BLi, / BLi) and word line WLj
A memory cell (MC) 11 _{i, j} is provided at each crossing point. Each memory cell 11 _{i, j} has a latch circuit in which the input side and the output side of two inverters are connected, and a word select signal provided from the word line WLj to connect the latch circuit and the bit line pair (BLi, / BLi). It is composed of a transistor that is turned on / off according to WSj.

Each bit line pair (BLi, / BLi) is a P channel MOS transistor (hereinafter referred to as "PMOS") 12 _i , 13 controlled by a precharge signal / PC.
It is connected to the power supply potential VCC via _i and is connected to the data lines DL and / DL via N channel MOS transistors (hereinafter referred to as “NMOS”) 14 _i and 15 _i controlled by the bit selection signal BSi. ing.

The memory block 10 further has a driver 16 for writing data and a sense amplifier (SA) 17 for reading data. When the write control signal WR applied to the enable terminal E is at level “H”, the driver 16 outputs complementary data signals according to the input data DI applied to the data terminal D on the data lines DL, /.
It is output to the DL. The sense amplifier 17 receives the data line D when the write control signal WR is at level “L”.
The output data DO is output by detecting the level difference between L and / DL.

In addition to the memory block 10, this memory includes a row decoder 20, a column decoder 30, and a logical product gate (hereinafter referred to as "AND") 40. The row decoder 20 and the column decoder 30 have the same configuration, and when the enable terminal E is "H", the two signals applied to the input terminals A and B are given.
"H" is output to any one of the output terminals Q0 to Q3 corresponding to the base number, and when the enable terminal E is "L", all the output terminals Q0 to Q3 are set to "L". Lower address signals A0 and A1 are applied to the input terminals A and B of the row decoder 20, and upper address signals A2 and A3 are applied to the input terminals A and B of the column decoder 30. . A precharge signal / PC and an enable signal CS are applied to the input side of the AND 40, and the output side of the AND 40 is connected to the enable terminals E of the row decoder 20 and the column decoder 30.

In such a memory, for example, the following operation is performed at the time of reading. The address signal to be read and the enable signal CS of "H" are given, and the precharge signal / PC of "L" is given only for the first fixed time. PMO while precharge signal / PC is "L"
S12 _i, 13 _i are all turned on. On the other hand, AN
The output signal of D40 becomes "L", and "L" is given to the enable terminals E of the decoder 20 and the column decoder 30,
The bit selection signal BSi and the word selection signal WSj are all "L". This allows all bit line pairs (B
Li, / BLi) is separated from the memory cell 11 _{i, j} and the data line DL, / DL and charged to the power supply voltage VCC.

After a certain period of time, the precharge signal / PC is switched to "H". This allows the PMOS
All of 12 _i and 13 _i are turned off, and the bit line pair (BLi, / BLi) is disconnected from the power supply voltage VCC. Further, the output signal of the AND 40 becomes "H", "H" is given to the enable terminals E of the decoder 20 and the column decoder 30, and the corresponding bit selection signal BSi and word selection signal corresponding to the address signals A0 to A3. WSj
Becomes "H".

[0009] Memory cell ₁₁ driven by the word selection signal WSj became _{"H" 0, j ~11 3} , j are respectively the bit line pair (BL0, / BL0) ~ ( BL3, / BL
3), and each memory cell 110 _{, j to} 113 _{, j}
Stored data of each bit line pair (BL0, / BL0) ~
It is output to (BL3, / BL3). Further, the NMOS1 controlled by the bit selection signal BSi which has become "H"
4 _i and 15 _i are turned on, and the bit line pair (BLi,
/ BLi) is connected to the data lines DL and / DL. As a result, the storage data of the memory cell 11 _{i, j} is given to the sense amplifier 17 via the data lines DL, / DL,
It is detected by this sense amplifier 17 and output as output data DO.

[0010]

However, the conventional memory has the following problems. During data reading, all the memory cells ₁₁ connected to the selected word line _{WLj 0, j} ~11 _3, j are respectively the bit line pairs at the same time (BL0, / BL0) ~ ( BL3, / BL3)
And the stored data is output to these bit line pairs. Therefore, the load current of the memory greatly changes each time data is read.

Therefore, the operating state of the memory can be grasped by externally monitoring the load current of the memory. In particular, in a memory used for an IC card or the like, there is a problem that a secret key stored inside is stolen by analyzing the operating state.

The present invention solves the problems of the prior art by changing the load current in a pseudo manner.
It provides a memory that is difficult to analyze from the outside.

[0013]

In order to solve the above-mentioned problems, a first invention of the present invention relates to a memory, wherein a plurality of bit lines arranged in parallel and a plurality of bit lines crossing the bit lines are arranged. A plurality of arranged word lines and a plurality of bit lines which are provided at respective intersections of the bit lines and the word lines and which are connected to the corresponding bit lines when driven by the corresponding word lines to input / output the storage data. Memory cell, a row decoder for decoding the lower bit signal of the address signal and selecting the bit line corresponding to the value of the lower bit, and a row decoder for the upper bit of the address signal when an enable signal is given. A column decoder for decoding a signal to drive the word line corresponding to the value of the upper bit, and one of the plurality of word lines when the enable signal is not applied.
And a pseudo drive circuit for driving the two.

According to the first aspect of the invention, since the memory is constructed as described above, the following operation is performed. When the enable signal is applied, the column decoder drives the word line corresponding to the upper bit of the address signal, and the memory cell connected to this word line is connected to the corresponding bit line. When no operable signal is given, one of the word lines is driven by the pseudo drive circuit, and the memory cell connected to this word line is connected to the corresponding bit line. On the other hand, in the row decoder, the bit line corresponding to the lower bit of the address signal is selected. As a result, the memory cell at the intersection of the word line and the bit line designated by the address signal is selected and connected. In this way, even if no operable signal is given, one memory cell is selected in a pseudo manner, so that it is difficult to analyze the operation from the outside.

According to a second aspect of the present invention, in a memory, a plurality of bit lines arranged in parallel, a plurality of word lines arranged so as to intersect the bit lines, and intersections of the bit lines and the word lines. Input / output of storage data by being divided into a plurality of groups in the word line direction, connected to different word lines in each group, and connected to corresponding bit lines when driven by the corresponding word line. A plurality of memory cells, a row decoder that decodes the lower bit signal of the address signal and selects the bit line corresponding to the lower bit value, and the address signal when the enable signal is applied. A column decoder that decodes and drives the word line corresponding to the address signal, and drives one of the plurality of word lines when the enable signal is not provided. And a similar drive circuit.

According to the second invention, the following operation is performed. When the enable signal is applied, the column decoder drives the word line corresponding to the address signal, and the memory cells divided into groups and connected to this word line are connected to the corresponding bit line. When no operable signal is given, one of the word lines is driven by the pseudo driving circuit, divided into groups, and the memory cells connected to this word line are connected to the corresponding bit line. On the other hand, in the row decoder, the bit line corresponding to the lower bit of the address signal is selected. As a result, the memory cell at the intersection of the word line and the bit line designated by the address signal is selected and connected. In this way, even if no operable signal is given, one memory cell is selected in a pseudo manner, so that it is difficult to analyze the operation from the outside. Further, since the word line is provided for each group of divided memory cells, the number of memory cells driven at the same time is reduced, and the load current is reduced.

According to a third aspect of the invention, the pseudo drive circuit in the memory according to the first or second aspect of the invention is configured to drive the word line according to the timing of the random signal when the operable signal is not applied. . According to the third invention, the word line is driven from the pseudo drive circuit in accordance with the timing of the random signal when the operable signal is not applied. This makes the operation analysis by the load current more difficult.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a circuit diagram of a memory showing a first embodiment of the present invention.
Elements that are the same as the elements inside have the same reference numerals.
This memory has m × n bits (here, m = n
= 4). The memory block 10 includes four bit line pairs (BLi, / BLi) (i = 0 to 3) arranged in parallel, and four words arranged so as to intersect these bit line pairs. Line W
Lj (where j = 0 to 3). A memory cell 11 _{i, j} is provided at each intersection of the bit line pair (BLi, / BLi) and the word line WLj. Each memory cell 11 _{i, j} has a latch circuit in which the input side and the output side of two inverters are connected, and a word select signal provided from the word line WLj to connect the latch circuit and the bit line pair (BLi, / BLi). It is composed of transistors for two switches controlled according to WSj.

Each bit line pair (BLi, / BLi) is connected to a PMOS 12 _i , 1 controlled by a precharge signal / PC.
It is connected to the power supply potential VCC via 3 _i and is connected to the data lines DL and / DL via NMOSs 14 _i and 15 _i controlled by the bit selection signal BSi.

The memory block 10 further includes a driver 16 for writing data and a sense amplifier 1 for reading data.
Have 7. The driver 16 outputs a complementary data signal to the data lines DL and / DL according to the input data DI given to the data terminal D when the write control signal WR given to the enable terminal E is "H". Is. In the sense amplifier 17, the write control signal WR is "L".
At this time, the level difference between the data lines DL and / DL is detected and the output data DO is output.

This memory includes a row decoder 20, a column decoder 30, and an AND 40 for selecting the memory cells 11 _{i, j} based on the address signals A0 to A3. The row decoder 20 and the column decoder 30 have the same configuration,
When the enable terminal E is "H", "H" is output to one of the output terminals Q0 to Q3 corresponding to the binary number given to the input terminals A and B, and the enable terminal E is "L". In the case of, all the output terminals Q0 to Q3 are set to "L". The lower bits A0 and A1 of the address signal are applied to the input terminals A and B of the row decoder 20, respectively,
The upper bits A2 and A3 of the address signal are applied to the input terminals A and B of the column decoder 30, respectively. Further, the precharge signal / PC and the operation enable signal CS are given to the input side of the AND 40, and this AND
The output side of 40 is connected to the enable terminals E of the row decoder 20 and the column decoder 30.

Further, in this memory, when the operation enable signal CS is not given, for example, the pseudo drive circuit 50 for driving the word line WL3 to perform the pseudo read operation.
Is equipped with. The pseudo drive circuit 50 includes an inverter 51,
AND52 and OR gate (hereinafter referred to as "OR")
It is composed of 53. The operable signal CS is given to the first input side of the AND 52 via the inverter 51,
The precharge signal / PC is applied to the second input side of the AND52. The output side of AND52 is connected to the first input side of OR53, and this OR5
The second input side of 3 is connected to the output terminal Q3 of the column decoder 30. The output side of the OR53 is connected to the word line WL3.

FIG. 3 is a signal waveform diagram showing the operation of FIG. The operation of FIG. 1 will be described below with reference to FIG. For example, at the time of reading, at time t1 in FIG. 3, the address signals A0 to A3 to be read and the enable signal CS of "H" are given, and the precharge signal / PC of "L" is given. Since the precharge signal / PC is “L”, the PMOSs 12 _i and 13 _i are all turned on. On the other hand, the output signal of the AND 40 is "L", the enable terminals E of the decoder 20 and the column decoder 30 are given "L", and the output signals of these decoder 20 and the column decoder 30 are all "L". Also, A
The dummy signal DM output from ND52 also becomes "L", and the word selection signal WS3 applied to the word line WL3.
Becomes "L". This allows all bit line pairs (B
Li, / BLi) is separated from the memory cell 11 _{i, j} and the data line DL, / DL, and is charged to the power supply voltage VCC as time passes.

At time t2, the bit line pair (BLi,
/ BLi) is charged to the power supply voltage VCC, the precharge
Image signal / PC is switched to "H". This allows
PMOS 12_i, 13_iAre all off and
The line pair (BLi, / BLi) is disconnected from the power supply voltage VCC.
To be done. On the other hand, the output signal of AND40 becomes "H",
To the enable terminals E of the decoder 20 and the column decoder 30
"H" is given. As a result, the address signals A0 to A0
Corresponding to A3, the corresponding bit selection signal BSi and word
The selection signal WSj (for example, WS3) becomes "H".
Memory cell 11 to which word selection signal WS3 is applied
_0,3~ 11_3,3Are bit line pairs (BL0,
/ BL0) to (BL3, / BL3) connected to each memo
Resel 11_{0, Three}~ 11_3,3Stored data of each bit
Appear on line pairs (BL0, / BL0) to (BL3, / BL3)
I will be forced. In addition, the bit selection signal BSi of "H" is used for NM
OS14 _i, 15_iIs turned on, and the bit line pair (B
Li, / BLi) is connected to the data lines DL, / DL
It Thereby, for example, the memory cell 11_{i, 3}Memory de
If the data is "1", the bit line BLi is in the "H" state.
The bit line / BLi changes to "L". these
The state of the bit line pair (BLi, / BLi) of
It is given to the sense amplifier 17 via DL and / DL,
The detection result of the sense amplifier 17 is output data DO.
Is output.

At time t3, when the read operation for the memory is completed and the next read operation is not performed,
The ready signal CS changes to "L". On the other hand, the precharge signal / PC periodically changes to "L" regardless of the presence or absence of the read operation. This allows PMOS1
All 2 _i and 13 _i are turned on, and all bit line pairs (BLi, / BLi) are charged to the power supply voltage VCC as time passes, as in the case of time t1.

At time t4, the bit line pair (BLi,
/ BLi) is charged to the power supply voltage VCC, the precharge
Image signal / PC is switched to "H". At this time,
Since the enable signal CS is "L", the decoder 20 and the column
“L” is given to the enable terminal E of the decoder 30.
Output signals of these decoder 20 and column decoder 30
Are all "L". On the other hand, output from AND52
The dummy signal DM that becomes "H" becomes "H", and the dummy signal DM becomes
The word line WL3 is driven. As a result, the word line WL
Memory cell 11 connected to 3_0,3~ 11_3,3Is
Bit line pairs (BL0, / BL0) to (BL3,
/ BL3) and each memory cell 11 _0,3~ 11
_3,3Stored data of each bit line pair (BL0, / BL
0) to (BL3, / BL3). By this
For example, the memory cell 11_{i, 3}Stored data is "0"
, The bit line / BLi is kept at "H",
The bit line BLi changes to "L".

Similarly, when the operation enable signal CS is "H", the word line WLj is driven by the word selection signal WSj designated by the address signals A0 to A3, and the memory cell 11i _{, j} is set to each bit line pair. (BLi, / BL
i) is connected. Further, when the operation enable signal CS is "L", the dummy signal DM drives the word line WL3, and the memory cell 11 _{i, 3} causes each bit line pair (BL
i, / BLi).

On the other hand, at the time of writing, the memory cell 11 _{i, j} to be written is selected by the operation enable signal CS and the address signals A0 to A3, and the write control signal WR is "H".
At the same time, the input data DI for writing is given. As a result, from the driver 16 to the data lines DL, / D
A data signal complementary to L is output and the selected NMO
The stored data of the memory cell 11 _{i, j} to be written is rewritten via S14 _i , 15 _i and the bit line pair BLi, / BLi.

As described above, the memory according to the first embodiment has the pseudo drive circuit 50 which generates the dummy signal DM and drives the word line WL3 when the enable signal CS is not applied. There is. As a result, the memory cell 11
Regardless of whether or not _{i and j} are actually accessed, the same load current as at the time of access can be passed at the same timing. Even if the load current of the memory is externally monitored, it becomes difficult to analyze the internal operation.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
2 is a circuit diagram of the memory showing the embodiment of the present invention, in which elements common to those in FIG. 1 are designated by common reference numerals. This memory is provided with a memory block 10A having a slightly different configuration in place of the memory block 10 in FIG. 1, and decoders 31 to 34 for subdividing the output side of the column decoder 30.
Is provided.

In the memory block 10A, the memory cells 110 _{, j} to 113 _{, j} arranged in the word line direction are divided into a plurality of (for example, 2) blocks, and the memory cell 11 is divided.
_{0, j 1} , 11 _{1, j} are driven by the word line WAj, and memory cells 11 _{2, j} , 11 _{3, j} are driven by the word line WBj.

When the signal applied to the enable terminal E is "H", each of the decoders 31 to 34 outputs "H" to one of the output terminals Q0 and Q1 based on the signal applied to the input terminal A. Is output. The address signal A1 is commonly applied to the input terminal A of each of the decoders 31 to 34. The enable terminal E of the decoder 31 is connected to the output terminal Q0 of the column decoder 30, and the output terminals Q0 and Q1 of the decoder 31 are connected to the word lines WA0 and WB0, respectively. The enable terminal E of the decoder 32 is the output terminal Q of the column decoder 30.
1 and the output terminals Q0, Q1 of this decoder 32
Are connected to word lines WA1 and WB1, respectively. The enable terminal E of the decoder 33 is the column decoder 30.
Of the decoder 33. Output terminals Q0 and Q1 of the decoder 33 are connected to word lines WA2 and WB2, respectively. Further, the enable terminal E of the decoder 34
Is connected to the output side of OR53, and the output terminals Q0 and Q1 of this decoder 34 are word lines WA3 and WB3, respectively.
It is connected to the.

In such a memory, the address signals A1 to A3 are decoded by the column decoder 30 and the four decoders 31 to 34 connected to the output side thereof, and the eight word lines WA0, WB0, WA1, ... Any one of WB3 is driven. Other operations are the same as those in FIG.

As described above, the memory according to the second embodiment has the dummy drive circuit 50 for generating the dummy signal DM and driving the word line when the enable signal CS is not applied. Therefore, there are advantages similar to those of the first embodiment. Further, the memory cells arranged in the word line direction are divided into two blocks, the word lines are separated for each block, and the decoders 31 to 35 for individually driving the separated word lines are provided. As a result, the number of memory cells driven at the same time can be reduced, and power consumption can be reduced.

(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
5 is a circuit diagram of a memory showing the embodiment of the present invention, in which elements common to those in FIG. 4 are designated by common reference numerals. This memory is provided with a pseudo drive circuit 50A having a slightly different configuration in place of the pseudo drive circuit 50 in FIG.

The pseudo drive circuit 50A has an operation enable signal CS.
And an AND signal to which the output signal of the inverter 51 and the precharge signal / PC are applied.
52. The output side of AND52 is AND5
It is connected to the first input side of 4,55. AND54
The address signal A1 is applied to the second input side of
The address signal A1 is inverted by the inverter 56 and applied to the second input side of D55. A
The output sides of the NDs 54 and 55 are AND 57 and 58, respectively.
Connected to the first input side of these AND 57, 58
The random signal RN is commonly applied to the second input side of the. The random signal RN is a signal whose level switches to “H” and “L” at irregular timing. The output side of AND57 and 58 is OR5 respectively.
Connected to the first input side of
The second input side of 9, 60 is the output terminal Q of the decoder 34.
0 and Q1 respectively. In addition, OR59,
The output side of 60 is the word line WA of the memory block 10A.
3 and WB3, respectively. Other configurations are the same as those in FIG.

In such a memory, the enable signal CS
Is not applied, the word lines WA3 and WB3 of the memory block 10A are randomly driven by the random signal RN. Other operations are the same as those in FIG.

As described above, in the memory according to the third embodiment, the word lines WA3 and WB are irregularly generated by the random signal RN when the enable signal CS is not applied.
Since it has the pseudo driving circuit 50A for driving No. 3, it is possible to make the operation analysis more difficult in addition to the same advantages as those of the second embodiment.

The present invention is not limited to the above embodiment, and various modifications can be made. Examples of this modification include the following (a) to (d). (A) The configurations of the memory blocks 10 and 10A are not limited to those illustrated. For example, the same can be applied to the case where the precharge is not performed.

(B) The structure of the pseudo drive circuit 50 in FIG. 1 is not limited to that shown in the drawing. Any circuit can be similarly applied as long as it can output a signal for driving one of the word lines WLj when the operable signal CS is not applied.

(C) Column decoder and decoder 3 in FIG.
The configurations of 1 to 34 are not limited to the illustrated ones. For example, 3 inputs 8 using the address signals A1 to A3 as input signals
An output decoder can also be used.

(D) The structure of the pseudo drive circuit 50A in FIG. 5 is not limited to that shown in the drawing. Ready signal CS
Is not applied to any of the word lines WLj
Any circuit can be similarly applied as long as it outputs a signal for randomly driving the signal according to the random signal RN.

[0043]

As described in detail above, according to the first aspect of the present invention, the pseudo drive circuit drives any one word line when the operable signal is not applied. With this, regardless of whether or not there is an operable signal,
One memory cell is always selected, which makes it difficult to analyze the operation from the outside.

According to the second aspect of the invention, the pseudo drive circuit drives any one of the word lines when the enable signal is not applied. Thereby, the same effect as the first aspect of the invention can be obtained. Further, the memory cells arranged in the direction of the word lines are divided into a plurality of groups, and each group has a word line for driving and a column decoder for individually driving these word lines. As a result, the number of memory cells driven at the same time is reduced, and power consumption can be reduced.

According to the third aspect of the invention, the pseudo drive circuit of the first or second aspect of the invention is configured to drive the word line irregularly at the timing of the random signal. As a result, it is possible to make the operation analysis from the outside more difficult.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a memory showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional memory.

FIG. 3 is a signal waveform diagram showing the operation of FIG.

FIG. 4 is a circuit diagram of a memory showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a memory showing a third embodiment of the present invention.

[Explanation of symbols]

10, 10A memory block 11 _{i, j} memory cell 20 row decoder 30 column decoder 31-34 decoder 50, 50A pseudo drive circuit BLi, / BLi bit line DL, / DL data line WLj word line

─────────────────────────────────────────────────── --Continued from the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 11/401-11/419 G11C 16/00-16/34 G06F 12/14 G06K 19/073

Claims (3)

(57) [Claims] 1. A plurality of bit lines arranged in parallel, a plurality of word lines arranged so as to intersect the bit lines, and provided at respective intersections of the bit lines and the word lines,
A plurality of memory cells connected to corresponding bit lines to input / output stored data when driven by corresponding word lines, and decode the signal of the lower bit of the address signal to correspond to the value of the lower bit. A row decoder for selecting the bit line; a column decoder for decoding a signal of the upper bit of the address signal and driving the word line corresponding to the value of the upper bit when an enable signal is given; A semiconductor memory device comprising: a pseudo drive circuit which drives any one of the plurality of word lines when an operable signal is not applied. 2. A plurality of bit lines arranged in parallel, a plurality of word lines arranged crossing the bit lines, and a plurality of word lines in the word line direction at intersections of the bit lines and the word lines. A plurality of memory cells that are divided into groups and are connected to different word lines for each group, and are connected to corresponding bit lines when driven by the corresponding word lines to input / output storage data. A row decoder that decodes the lower bit signal of the address signal and selects the bit line corresponding to the lower bit value; and a row decoder that decodes the address signal when an enable signal is given A column decoder that drives the corresponding word line; and a pseudo drive circuit that drives any one of the plurality of word lines when the enable signal is not applied. And a semiconductor memory device. 3. The semiconductor memory device according to claim 1, wherein the pseudo drive circuit drives the word line in accordance with the timing of a random signal when the operable signal is not applied.