JP2002042475A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory in which the analysis of internal operation is hard from the outside. SOLUTION: When an operation enable-signal CS is 'H', corresponding memory cells 11i,j in a memory block 10 are selected based on address signals A0-A3 decoded by a row decoder 20 and a column decoder 30, and connected to bit lines BLi, /BLi. On the other hand, when the operation enable-signal CS is 'L', a specific word line (e.g. WL3) is driven by a pseudo drive circuit 50, and memory cells 11i,3 are connected to the bit lines BLi, /BLi. Thereby, either of memory cells 11i,j is selected independently of the operation enable- signal CS, variation of a load current is not caused. Therefore, the analysis of the internal operation is made hard even if a load current is monitored from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device (hereinafter referred to as a "memory"), and more particularly to a memory which makes it difficult to analyze the operation from the outside.

[0002]

2. Description of the Related Art An IC card used for a financial card, a prepaid card, a point card or the like causes a malfunction by applying a high voltage or a low voltage or applying a high-speed clock signal in order to decrypt an encryption key. It is exposed to various attacks, such as performing motion analysis. Recently, the operation flow has been analyzed by comparing the operating current of the IC with the input / output data, and the change in the current with respect to the input data has been captured and analyzed while estimating the value of the encryption key by a statistical method.
Finally, techniques for stealing secret keys have emerged.

FIG. 2 is a circuit diagram showing an example of a conventional memory. This memory includes a 4 × 4 (ie, 16-bit) memory block 10. Memory block 10
Are four bit line pairs (BLi, //
BLi) (where i = 0 to 3, and “/” means inversion), and 4 arranged crossing these bit line pairs.
The word lines WLj (where j = 0 to 3) are provided. Bit line pair (BLi, / BLi) and word line WLj
_Are provided with memory cells (MC) 11 _{i, j} at each intersection. Each of the memory cells 11 _{i, j} has a latch circuit connecting the input side and the output side of two inverters, and a word selection signal supplied from a word line WLj to connect the latch circuit and the bit line pair (BLi, / BLi). It is composed of a transistor that is turned on / off according to WSj.

Each bit line pair (BLi, / BLi) includes P-channel MOS transistors (hereinafter referred to as "PMOS") 12 _i , 13 controlled by a precharge signal / PC.
_i and to the data lines DL and / DL via N-channel MOS transistors (hereinafter referred to as “NMOS”) 14 _i and 15 _i controlled by a bit selection signal BSi. ing.

[0005] The memory block 10 further has a driver 16 for writing data and a sense amplifier (SA) 17 for reading data. When the write control signal WR applied to the enable terminal E is at the level "H", the driver 16 supplies a complementary data signal to the data lines DL, / in accordance with the input data DI applied to the data terminal D.
Output to DL. When the write control signal WR is at the level “L”, the sense amplifier 17
It detects the level difference between L and / DL and outputs the output data DO.

This memory includes a row decoder 20, a column decoder 30, and an AND gate (hereinafter, referred to as "AND") 40 in addition to the memory block 10. The row decoder 20 and the column decoder 30 have the same configuration. When the enable terminal E is at “H”, the two terminals supplied to the input terminals A and B
"H" is output to any one of the output terminals Q0 to Q3 corresponding to the base number, and when the enable terminal E is "L", all the output terminals Q0 to Q3 are set to "L". The input terminals A and B of the row decoder 20 are supplied with lower address signals A0 and A1, and the input terminals A and B of the column decoder 30 are supplied with upper address signals A2 and A3. . The input side of the AND 40 is supplied with a precharge signal / PC and an operation enable signal CS. The output side of the AND 40 is connected to the enable terminal E of the row decoder 20 and the column decoder 30.

In such a memory, for example, the following operation is performed at the time of reading. The address signal to be read and the operable signal CS of "H" are supplied, and the precharge signal / PC of "L" is supplied only for the first fixed time. While the precharge signal / PC is "L", PMO
S12 _i and _13i are all turned on. On the other hand, AN
The output signal of D40 becomes "L", and "L" is given to the enable terminals E of the decoder 20 and the column decoder 30.
The bit selection signal BSi and the word selection signal WSj all become "L". Thereby, all bit line pairs (B
Li, / BLi) are disconnected from the memory cells 11 _{i, j} and the data lines DL, / DL, and charged to the power supply voltage VCC.

After a lapse of a predetermined time, the precharge signal / PC is switched to "H". This allows PMOS
12 _i and 13 _i are all turned off, and the bit line pair (BLi, / BLi) is disconnected from the power supply voltage VCC. The output signal of the AND 40 becomes "H", "H" is given to the enable terminals E of the decoder 20 and the column decoder 30, and the corresponding bit selection signal BSi and word selection signal corresponding to the address signals A0 to A3. WSj
Becomes “H”.

[0009] Memory cell ₁₁ driven by the word selection signal WSj became _{"H" 0, j ~11 3} , j are respectively the bit line pair (BL0, / BL0) ~ ( BL3, / BL
3), and each of the memory cells 110 _{, j to} 113 _{, j}
Is stored in each bit line pair (BL0, / BL0) to
(BL3, / BL3). Further, the NMOS 1 controlled by the bit selection signal BSi that has become “H”
4 _i and 15 _i are turned on, and the bit line pair (BLi,
/ BLi) is connected to data lines DL and / DL. As a result, the data stored in the memory cells 11 _{i, j} is given to the sense amplifier 17 via the data lines DL, / DL,
The data is detected by the sense amplifier 17 and output as output data DO.

[0010]

However, the conventional memory has the following problems. During data reading, all the memory cells ₁₁ connected to the selected word line _{WLj 0, j} ~11 _3, j are respectively the bit line pairs at the same time (BL0, / BL0) ~ ( BL3, / BL3)
And the stored data is output to these bit line pairs. Therefore, the load current of the memory fluctuates greatly every time data is read.

Therefore, by monitoring the load current of the memory from the outside, it becomes possible to grasp the operating state of the memory. Particularly, in a memory used for an IC card or the like, there is a problem that a secret key stored inside is stolen by analyzing an operation state.

The present invention solves the problems of the prior art by changing the load current in a pseudo manner.
It is intended to provide a memory which is difficult to analyze the operation from the outside.

[0013]

According to a first aspect of the present invention, there is provided a memory, comprising: a plurality of bit lines arranged in parallel with each other; A plurality of word lines arranged and a plurality of word lines provided at each intersection of the bit line and the word line, connected to the corresponding bit line when driven by the corresponding word line, and inputting / outputting storage data. A memory cell, a row decoder that decodes a signal of a lower bit of an address signal and selects the bit line corresponding to the value of the lower bit, and a higher-order bit of the address signal when an operation enable signal is given. A column decoder that decodes a signal to drive the word line corresponding to the value of the upper bit, and one of the plurality of word lines when the operable signal is not supplied;
And a pseudo drive circuit for driving one of them.

According to the first aspect, since the memory is configured as described above, the following operation is performed. When an operable signal is applied, a word line corresponding to the upper bit of the address signal is driven by the column decoder, and a memory cell connected to this word line is connected to a corresponding bit line. When no operable signal is given, one of the word lines is driven by the pseudo drive circuit, and the memory cell connected to this word line is connected to the corresponding bit line. On the other hand, in the row decoder, a bit line corresponding to the lower bits of the address signal is selected. Thereby, the memory cell at the intersection of the word line and the bit line specified by the address signal is selected and connected. As described above, even if no operable signal is given, one memory cell is selected in a pseudo manner, so that it becomes difficult to analyze the operation from the outside.

According to a second aspect of the present invention, in the memory, a plurality of bit lines arranged in parallel, a plurality of word lines arranged intersecting the bit lines, and an intersection of the bit lines and the word lines Are provided in a plurality of groups in the direction of the word line, connected to different word lines for each group, and connected to the corresponding bit line when driven by the corresponding word line to input / output storage data. A plurality of memory cells, a row decoder that decodes a signal of a lower bit of an address signal and selects the bit line corresponding to the value of the lower bit, and converts the address signal when an operation enable signal is given. A column decoder for decoding and driving the word line corresponding to the address signal; and driving one of the plurality of word lines when the operable signal is not supplied. And a similar drive circuit.

According to the second aspect, the following operation is performed. When the operable signal is supplied, the word line corresponding to the address signal is driven by the column decoder, and the memory cell divided into groups and connected to the word line is connected to the corresponding bit line. When the operable signal is not supplied, any one of the word lines is driven by the pseudo drive circuit, divided into groups, and the memory cells connected to this word line are connected to the corresponding bit lines. On the other hand, in the row decoder, a bit line corresponding to the lower bits of the address signal is selected. Thereby, the memory cell at the intersection of the word line and the bit line specified by the address signal is selected and connected. As described above, even if no operable signal is given, one memory cell is selected in a pseudo manner, so that it becomes difficult to analyze the operation from the outside. In addition, since the word line is provided for each group of divided memory cells, the number of memory cells driven simultaneously decreases, and the load current decreases.

According to a third aspect of the present invention, the pseudo drive circuit in the memory according to the first or second aspect of the present invention is configured to drive a word line according to the timing of a random signal when no operable signal is given. . According to the third aspect, when no operable signal is given, the word line is driven from the pseudo drive circuit in accordance with the timing of the random signal. This makes it even more difficult to analyze the operation based on the load current.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a circuit diagram of a memory showing a first embodiment of the present invention.
Elements common to those in the middle are denoted by common reference numerals.
This memory has m × n bits (here, m = n
= 4). The memory block 10 includes four pairs of bit lines (BLi, / BLi) (i = 0 to 3) arranged in parallel, and four words arranged intersecting these bit line pairs. Line W
Lj (where j = 0 to 3). At each intersection of the bit line pair (BLi, / BLi) and the word line WLj, a memory cell _{11i, j} is provided. Each of the memory cells 11 _{i, j} has a latch circuit connecting the input side and the output side of two inverters, and a word selection signal supplied from a word line WLj to connect the latch circuit and the bit line pair (BLi, / BLi). It is composed of two switching transistors controlled according to WSj.

Each bit line pair (BLi, / BLi) is connected to a PMOS 12 _i , 1 controlled by a precharge signal / PC.
3 _i is connected to the power supply potential VCC via a are connected via the NMOS 14 _i, 15 _i which is controlled by the bit selection signal BSi data lines DL, the / DL.

The memory block 10 further includes a driver 16 for writing data and a sense amplifier 1 for reading data.
7. The driver 16 outputs a complementary data signal to the data lines DL and / DL according to the input data DI applied to the data terminal D when the write control signal WR applied to the enable terminal E is "H". It is. The sense amplifier 17 sets the write control signal WR to “L”
At this time, the level difference between the data lines DL and / DL is detected to output the output data DO.

This memory includes a row decoder 20, a column decoder 30, and an AND 40 for selecting a memory cell 11i _{, j} based on address signals A0 to A3. The row decoder 20 and the column decoder 30 have the same configuration,
When the enable terminal E is at "H", "H" is output to one of the output terminals Q0 to Q3 corresponding to the binary number given to the input terminals A and B, and the enable terminal E is at "L". In this case, the output terminals Q0 to Q3 are all set to "L". The lower bits A0 and A1 of the address signal are applied to input terminals A and B of the row decoder 20, respectively.
The input terminals A and B of the column decoder 30 are supplied with the upper bits A2 and A3 of the address signal, respectively. A precharge signal / PC and an operation enable signal CS are applied to the input side of the AND 40.
The output side of 40 is connected to the enable terminal E of the row decoder 20 and the column decoder 30.

Further, when the operable signal CS is not supplied, this memory drives, for example, the word line WL3 to perform a pseudo read operation.
It has. The pseudo drive circuit 50 includes an inverter 51,
AND52 and OR gate (hereinafter referred to as "OR")
53. The operation enable signal CS is supplied to a first input side of the AND 52 via the inverter 51,
A precharge signal / PC is supplied to a second input side of the AND 52. The output of AND 52 is connected to the first input of OR 53 and this OR 5
3 is connected to the output terminal Q3 of the column decoder 30. The output side of the OR 53 is connected to the word line WL3.

FIG. 3 is a signal waveform diagram showing the operation of FIG. Hereinafter, the operation of FIG. 1 will be described with reference to FIG. For example, at the time of reading, at time t1 in FIG. 3, the address signals A0 to A3 to be read and the operable signal CS of "H" are supplied, and the precharge signal / PC of "L" is supplied. Since the precharge signal / PC is "L", the PMOSs 12 _i and 13 _i are all turned on. On the other hand, the output signal of the AND 40 becomes "L", "L" is given to the enable terminal E of the decoder 20 and the column decoder 30, and all the output signals of the decoder 20 and the column decoder 30 become "L". Also, A
The dummy signal DM output from the ND 52 also becomes “L”, and the word selection signal WS 3 applied to the word line WL 3
Also becomes “L”. Thereby, all bit line pairs (B
Li, / BLi) are disconnected from the memory cells 11 _{i, j} and the data lines DL, / DL, and charged to the power supply voltage VCC over time.

At time t2, bit line pair (BLi,
/ BLi) is charged to the power supply voltage VCC.
Message / PC is switched to "H". This allows
PMOS12_i, 13_iAre all turned off and the bit
Line pair (BLi, / BLi) is disconnected from power supply voltage VCC
Is done. On the other hand, the output signal of the AND 40 becomes “H”,
To the enable terminal E of the decoder 20 and the column decoder 30
"H" is given. Thereby, the address signals A0 to A0
A3, the corresponding bit selection signal BSi and the word
The node selection signal WSj (for example, WS3) becomes “H”.
Memory cell 11 to which word select signal WS3 is applied
_0,3~ 11_3,3Are bit line pairs (BL0, BL0,
/ BL0)-(BL3, / BL3)
Recell 11_{0, 3}~ 11_3,3Is stored in each bit
Exit to line pair (BL0, / BL0)-(BL3, / BL3)
Is forced. Further, NM is selected by a bit selection signal BSi of “H”.
OS14 _i, 15_iIs turned on, and the bit line pair (B
Li, / BLi) are connected to the data lines DL, / DL.
You. Thereby, for example, the memory cell 11_{i, 3}The memory of
When the data is “1”, the bit line BLi is in the “H” state.
The bit line / BLi changes to "L". these
Of the bit line pair (BLi, / BLi) is the data line
DL, / DL to the sense amplifier 17,
Of the sense amplifier 17 is output data DO
Is output.

At time t3, when the read operation for the memory is completed and the next read operation is not performed,
The operable signal CS changes to “L”. On the other hand, the precharge signal / PC periodically changes to "L" regardless of the presence or absence of the read operation. Thereby, the PMOS1
2 _i and 13 _i are all turned on, and all bit line pairs (BLi, / BLi) are charged to the power supply voltage VCC as time passes, as in the case of time t1.

At time t4, the bit line pair (BLi,
/ BLi) is charged to the power supply voltage VCC.
Message / PC is switched to "H". At this time,
Since the ready signal CS is “L”, the decoder 20 and the column
"L" is applied to the enable terminal E of the decoder 30.
And the output signals of these decoder 20 and column decoder 30
Are all "L". On the other hand, output from AND52
The dummy signal DM becomes “H”, and the dummy signal DM
The word line WL3 is driven. Thereby, the word line WL
3 connected to the memory cell 11_0,3~ 11_3,3Is
Bit line pairs (BL0, / BL0) to (BL3,
/ BL3) and each memory cell 11 _0,3~ 11
_3,3Is stored in each bit line pair (BL0, / BL
0) to (BL3, / BL3). This
For example, the memory cell 11_{i, 3}Is “0”
In this case, the bit line / BLi is kept at the "H" state,
The cut line BLi changes to “L”.

Similarly, when the operation enable signal CS is "H", the word line WLj is driven by the word selection signal WSj specified by the address signals A0 to A3, and the memory cell 11i _{, j} is connected to each bit line pair. (BLi, / BL
i). When the operable signal CS is "L", the word line WL3 is driven by the dummy signal DM, and the memory cell 11i _{, 3} is connected to each bit line pair (BL).
i, / BLi).

On the other hand, at the time of writing, the memory cell 11i _{, j} to be written is selected by the operation enable signal CS and the address signals A0 to A3, and the write control signal WR is set to "H".
And input data DI for writing is supplied. As a result, data lines DL, / D
A data signal complementary to L is output, and the selected NMO
The data stored in the memory cell 11 _{i, j} to be written is rewritten via S14 _i , 15 _i and the bit line pair BLi, / BLi.

As described above, the memory of the first embodiment has the pseudo drive circuit 50 that generates the dummy signal DM when the operable signal CS is not supplied and drives the word line WL3. I have. Thereby, the memory cell 11
Regardless of the presence or absence of actual access to _{i and j} , the same load current as at the time of access can flow at the same timing. Even if the load current of the memory is externally monitored, it becomes difficult to analyze the internal operation.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 2 is a circuit diagram of a memory according to the first embodiment, in which elements common to those in FIG. 1 are denoted by common reference numerals. This memory is provided with a memory block 10A having a slightly different configuration in place of the memory block 10 in FIG. 1, and decoders 31 to 34 for subdividing the output side of the column decoder 30.
Is provided.

The memory block 10A divides the memory cells 110 _{, j} to 113 _{, j} arranged in the direction of the word line into a plurality of (for example, two) blocks, and
_{0, j} , 11 _{1, j} are driven by a word line WAj, and the memory cells 11 _{2, j} , 113 _{, j} are driven by a word line WBj.

When the signal applied to the enable terminal E is "H", each of the decoders 31 to 34 outputs "H" to one of the output terminals Q0 and Q1 based on the signal applied to the input terminal A. Is output. An address signal A1 is commonly supplied to the input terminals A of the decoders 31 to 34. The enable terminal E of the decoder 31 is connected to the output terminal Q0 of the column decoder 30, and the output terminals Q0 and Q1 of the decoder 31 are connected to word lines WA0 and WB0, respectively. The enable terminal E of the decoder 32 is connected to the output terminal Q of the column decoder 30.
1 and output terminals Q0, Q1 of the decoder 32
Are connected to word lines WA1 and WB1, respectively. The enable terminal E of the decoder 33 is connected to the column decoder 30
The output terminals Q0 and Q1 of the decoder 33 are connected to word lines WA2 and WB2, respectively. Further, the enable terminal E of the decoder 34
Is connected to the output side of OR53, and output terminals Q0 and Q1 of decoder 34 are connected to word lines WA3 and WB3, respectively.
It is connected to the.

In such a memory, the address signals A1 to A3 are decoded by the column decoder 30 and four decoders 31 to 34 connected to its output side, and the eight word lines WA0, WB0, WA1,. One of the WB3s is driven. Other operations are the same as those in FIG.

As described above, the memory of the second embodiment has the dummy drive circuit 50 for generating the dummy signal DM when the operable signal CS is not supplied and driving the word line. Therefore, there is an advantage similar to that of the first embodiment. Further, memory cells arranged in the direction of the word line are divided into two blocks, word lines are separated for each block, and decoders 31 to 35 for individually driving the separated word lines are provided. Thus, the number of memory cells driven simultaneously can be reduced, and power consumption can be reduced.

(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
FIG. 5 is a circuit diagram of a memory according to the first embodiment, in which elements common to those in FIG. 4 are denoted by common reference numerals. This memory is provided with a pseudo drive circuit 50A having a slightly different configuration instead of the pseudo drive circuit 50 in FIG.

The pseudo drive circuit 50A is provided with an operation enable signal CS
, And an AND signal to which an output signal of inverter 51 and precharge signal / PC are applied.
52. The output side of AND52 is AND5
4, 55 are connected to the first input side. AND54
Are supplied with an address signal A1 at a second input side thereof, and
The address signal A1 is inverted and supplied to the second input side of D55 by the inverter 56. A
The output sides of the NDs 54 and 55 are AND 57 and 58, respectively.
AND 57, 58
, A random signal RN is commonly supplied to the second input side. The random signal RN is a signal whose level switches between “H” and “L” at irregular timing. The output sides of AND57 and 58 are OR5
9,60 connected to the first inputs of these OR5
9, 60 are connected to the output terminal Q of the decoder 34.
0 and Q1. OR59,
60 is connected to the word line WA of the memory block 10A.
3 and WB3. Other configurations are the same as those in FIG.

In such a memory, the operation enable signal CS
Is not supplied, the word lines WA3 and WB3 of the memory block 10A are driven irregularly by the random signal RN. Other operations are the same as those in FIG.

As described above, in the memory of the third embodiment, when the operation enable signal CS is not supplied, the word lines WA3 and WB are irregularly controlled by the random signal RN.
3 has the same pseudo-drive circuit 50A as that for driving the third embodiment, and in addition to the same advantages as those of the second embodiment, the operation analysis can be made more difficult.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (d). (A) The configurations of the memory blocks 10 and 10A are not limited to those illustrated. For example, the present invention can be similarly applied to a case where no precharge is performed.

(B) The configuration of the pseudo drive circuit 50 in FIG. 1 is not limited to the illustrated one. Any circuit that can output a signal for driving any of the word lines WLj when the operable signal CS is not supplied can be similarly applied to any circuit.

(C) Column decoder and decoder 3 in FIG.
The configurations 1 to 34 are not limited to those illustrated. For example, three inputs 8 using address signals A1 to A3 as input signals
An output decoder can also be used.

(D) The configuration of the pseudo drive circuit 50A in FIG. 5 is not limited to the illustrated one. Operable signal CS
Is not given, any word line WLj
Can be similarly applied to any circuit that outputs a signal for driving irregularly according to the random signal RN.

[0043]

As described above in detail, according to the first aspect, the pseudo drive circuit for driving any one of the word lines when the operable signal is not supplied is provided. As a result, regardless of the presence or absence of the enable signal,
One memory cell is always selected, which makes it difficult to analyze the operation from the outside.

According to the second aspect, there is provided a pseudo drive circuit for driving any one of the word lines when no operable signal is given. This has the same effect as the first invention. Furthermore, the memory cells arranged in the direction of the word lines are divided into a plurality of groups, and a word line for driving each group is provided, and a column decoder for individually driving these word lines is provided. Thus, the number of memory cells driven simultaneously is reduced, and power consumption can be reduced.

According to the third aspect, the pseudo drive circuit according to the first or second aspect is configured to drive the word line irregularly at the timing of the random signal. This makes it even more difficult to analyze the operation from the outside.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a memory according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional memory.

FIG. 3 is a signal waveform diagram showing the operation of FIG.

FIG. 4 is a circuit diagram of a memory according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a memory according to a third embodiment of the present invention.

[Description of Signs] 10, 10A memory block 11 _{i, j} memory cell 20 row decoder 30 column decoder 31-34 decoder 50, 50A pseudo drive circuit BLi, / BLi bit line DL, / DL data line WLj word line

Claims (3)

[Claims] A plurality of bit lines arranged in parallel with each other; a plurality of word lines arranged to intersect the bit lines; and a plurality of word lines arranged at intersections of the bit lines and the word lines,
A plurality of memory cells connected to a corresponding bit line when driven by a corresponding word line and inputting / outputting storage data, and decoding a signal of a lower bit of an address signal to correspond to a value of the lower bit A row decoder that selects the bit line; a column decoder that decodes a signal of an upper bit of the address signal when an operation enable signal is supplied and drives the word line corresponding to the value of the upper bit; And a pseudo drive circuit for driving any one of the plurality of word lines when an operable signal is not supplied. 2. A plurality of bit lines arranged in parallel, a plurality of word lines arranged crossing the bit lines, and a plurality of word lines arranged at intersections of the bit lines and the word lines in the word line direction. A plurality of memory cells connected to different word lines for each group, connected to corresponding bit lines when driven by corresponding word lines, and connected to corresponding bit lines for input / output of storage data. A row decoder for decoding a lower bit signal of the address signal and selecting the bit line corresponding to the value of the lower bit; and a decoder for decoding the address signal when an operation enable signal is given to convert the address signal into the address signal. A column decoder for driving the corresponding word line, and a pseudo drive circuit for driving any one of the plurality of word lines when the operable signal is not supplied. A semiconductor memory device characterized by the following. 3. The semiconductor memory device according to claim 1, wherein said pseudo drive circuit drives said word line according to a timing of a random signal when said enable signal is not supplied.