JP3479196B2 - DSP memory address control device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a DSP (Digital Sign).
al Prosessor) external memory and / or internal memory memory address controller.

[0002]

2. Description of the Related Art In recent years, it is possible to perform highly accurate processing as compared with analog signal processing, and by setting parameters such as a coefficient, arbitrary characteristics can be stably and uniformly obtained, and no adjustment is required. Due to its characteristics, the DSP capable of processing analog signals by a digital method is used in a wide range of fields such as voice signal processing, communication signal processing, measurement signal processing, image signal processing, seismic wave signal processing, and underwater acoustic signal processing. It became so.

[0003]

An ordinary DSP is not designed on the premise that a plurality of independent programs are processed in a time-division manner within one sampling time, and therefore, each program or coefficient has an internal function. Used areas of the data memory (D-RAM) and the external memory (X-RAM) are divided and used. However, when multiple jobs are executed in parallel, the memory address is not managed independently for each job, and there is a problem such as accessing the memory area of another job during execution of one job. It had occurred. Even if the jobs processed in parallel are the same, programs of the same contents must be stored separately for each job, which increases the job program amount of the host CPU, which causes the storage. The types of jobs to be performed will be limited. The present invention was devised in view of the above problems of the prior art, and makes it possible to manage memory addresses independently for each job during parallel processing of a plurality of jobs, and to provide a program of the same content. Aims to provide a memory address control device for a DSP which can prevent duplicated storage.

[0004]

DISCLOSURE OF THE INVENTION The inventors of the present invention pursued the cause of the above-mentioned problems and examined a new structure capable of solving the problems. The structure devised as a result of the examination is the present invention, and the development process thereof will be described below.

As described above, the conventional DSP is not designed on the premise that a plurality of independent programs are processed in a time-division manner within one sampling time. Therefore, each program and coefficient have an internal function. Data memory (D
-RAM) and the external memory (X-RAM) used areas are divided and used. For example, as shown in FIGS. 8 and 9, one DSP processes the chorus effect in the job EFF1 and the delay effect in the job EFF2 in a time-sharing manner, as shown in FIGS. If there is a system, job EFF
It has been sufficient to use a program and a coefficient that access only 0 to 7FFF of the external memory in 1 and a program and a coefficient that only access 8000 to FFFF of the external memory in job EFF2.

This method is capable of 100% independent time-division processing without any problem in carrying out regular ordinary arithmetic processing, but converts either EFF1 or EFF2 program during its use. Sometimes there are problems. For example, some general-purpose DSPs can change the corresponding coefficient only while the program is operating. In the case of such a DSP, the EFF in the instruction memory (I-RAM) is used.
When the program of No. 1 is replaced with a new one, the old coefficient for the program before replacement is stored in the coefficient memory (C-
It is still written in RAM), and EFF in this state
When the new program No. 1 is operated, the EFF1 program operates using the old coefficient. Therefore, the operation is performed by referring to the data from the unrelated memory address, and the operation result is stored in the memory address other than the one set by the program. It will be stored. Therefore, there is a possibility that the area of the external memory or the internal memory provided for the EFF1 is ignored and the area for the EFF2 is accessed. Then EFF
As for 1), C1a in FIG.
Gate as 0 (input IN1 is output as it is)
Although there is no problem with this, since the EFF2 continues to operate stably during that time, for example, if data is erroneously written in the external memory or the internal memory area for the EFF2 when switching the program of the EFF1 and the coefficient, the EFF2
After that, a problem occurs at the time of referring to the external memory, and as a result, noise is generated from the output of the EFF2.

As another cause, since the conventional DSP basically has no idea of partitioning the external memory and using it as a block, as shown in FIG.
The address pointer moves all over the external memory space. That is, the address pointer +
1 to use (EFF1 and 2 do not move the pointer independently, but as a common pointer for both, add +1
Then, as shown in FIG. 11, the external memory apparently seems to flow in the direction from FFFF to 0000. Eventually, the data written by EFF2 is EFF1.
Data written to EFF1 in the same way,
It goes around and flows into EFF2. This phenomenon itself has no problem when each EFF program is in a steady operation (for example, write delay in FFFF and read 9000, and write chorus in 7FFF and write 70).
As described above, when one of the programs is being rewritten, the own memory area cannot be accessed during the rewriting (during loading of a new program, about 200 ms), as shown in FIG. , The contents written by the other effect program will come into its own memory area. At this time, a simple effect program is used, and C1a and C shown in FIG. 8 are simply used without purposely clearing the external memory.
When a signal added with an effect is output by crossfading 1b (or C2a and C2b), unexpectedly large noise is output. In particular, when a large signal is written in the external memory of the other effect program, it comes into the memory area of the switched effect and becomes conspicuous. Even if the other effect is not a very large signal, the input signal (I
When N1orIN2) is 0, the sound that should not be output is produced, so it is clearly noticeable.

Still another problem is that EFF1 is generated in the DSP program flow chart as shown in FIG.
The job of EFF2 and the job of EFF2 can be arbitrarily combined from a plurality of effects, and the programs of those parts are stored in the host C each time an effect is newly selected.
Generally, the job is transferred again from the PU, but even when the same effect is selected by EFF1 and EFF2, different job programs must be transferred. That is, the host CPU needs to store the effect program and coefficient for EFF1 and the effect program and coefficient for EFF2 separately. The reason is that the access area of the external memory differs between EFF1 and EFF2, but there was no register or the like that can eliminate the problem and make the program and coefficient common.

Since the causes as described above have been clarified, next, a structure for solving these problems was examined. As a result, the present inventors have devised the following configuration of the present invention. That is, the configuration of the present invention relates to an offset register that stores an offset address, an address pointer that stores a memory address, and an address generated based on the value of the address pointer and the operand value or coefficient data on the program. An area register for designating an allowable range of memory addresses and a program for time-divisionally processing a plurality of jobs are provided, and these job programs use different offset registers and area registers, respectively, and share the above address pointer. These offset registers and area registers are set so as to indicate different memory areas before the respective job programs processed in the time division are executed, and the values of the address pointer and the program are set. Based on the operand value or coefficient data of By correcting the generated address value for each job to the address value in the memory area determined based on the offset register and area register used by the job, each job program basically accesses different memory areas. It has a feature.

In the above configuration, if the offset register in each job program is set to indicate the lower limit of the memory address and the area register in each job program is set to indicate the upper limit of the memory address,
It enables efficient memory allocation.

[0011]

[0012]

[0013]

[0014]

In the structure of claim 1, the offset register array is arranged.
The area register is set so as to point to different memory areas before each job program to be processed in a time-sharing manner is executed, and on the premise of that, the address pointer value and the operand value or coefficient data on the program are set. The address value generated based on each job is corrected to an address in the memory area determined by the offset register and area register used by the job, so that each job program accesses different memory areas. Will have the effect of becoming. Therefore, a different memory area can be assigned to each job, and even if a plurality of jobs that are time-divisionally processed have the same content, the other memory area cannot be accessed in each job. It is also possible.

[0015]

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Specific embodiments of the present invention will be described below. 1 to 3 show an embodiment configuration of a memory address control device of a DSP according to claim 1 of the present application. In this configuration, in the configuration of the part that performs address control for the internal memory and the external memory of the DSP, an offset register (illustrated in the figure) that stores each address of offset 1 (area bottom 1 in memory area) and offset 2 (also area bottom 2) None),
Area top 1 (corresponding to the area bottom 1 above) which is the allowable range of the memory address for the address pointer that stores the memory address and the address generated based on the value of the address pointer and the operand value or coefficient data on the program ) And area top 2 (corresponding to the area bottom 2) (not shown)
And a program (not shown) for processing the job EFF1 and the job EFF2 in a time-sharing manner. With the circuit configuration shown in FIG. 1, these job programs use different offset registers and area registers, respectively. Further, as shown in FIG. 3, the offset register and the area register are set to indicate the memory area for the sound effect program of the job EFF1 and the memory area for the sound effect program of the job EFF2.

In the circuit configuration of FIG. 1, with respect to basic address data which is performed by adding operand or coefficient data to the value of the address pointer, the value exceeds the area top input to the selector 1 (overflow). The case and the case where the value is below the area bottom (underflow) input to the selector 2 are checked, and if there is any of them, the upper limit correction (subtract the difference between the area top and the area bottom as shown in FIG. 2). Or lower limit correction (adding the difference between the area top and the area bottom) is time-shared (C
In the K1 cycle), the target data is made to approach the target value a plurality of times, and the address data obtained thereby is determined as the memory access address and output.

In the configuration of FIG. 1 described above, the area bottom 1 and the EF of the memory area for the EFF 1 are separated from each offset register.
The area bottom 2 of the memory area for F2 is input to A and B of the selector 2 as offset 1 and offset 2, respectively. On the other hand, the area top 1 of the memory area for EFF1 and the area top 2 of the memory area for EFF2 are input to A and B of the selector 1 from each area register, respectively. When the ACR flag of the address control register (not shown) = 0, the selectors 1 and 2 respectively select the input A to selectively output the area bottom 1 and the area top 1 of the memory area for the EFF1, and the AC
When the R flag = 1, the input B is selected and the area bottom 2 and the area top 2 of the memory area for the EFF2 are selectively output. These values are then input to the selector 3 and the differencer 6, respectively.

Configuration from selector 3 to comparator 4 and selector 5 (hereinafter referred to as flow check configuration)
Is a configuration for checking whether the value of the address data exceeds the area top (overflow) or falls below the area bottom (underflow). Further, the configuration from the differentiator 6 to the complement converter 7 and the selector 8 (hereinafter referred to as the difference calculation configuration) has a function of the area top and the area bottom required for performing the upper limit correction or the lower limit correction at the time of overflow or underflow. This is a configuration for obtaining a difference.

In the selector 3 in the flow check configuration, the input A is selected when the clock CK4 = 0, and the area top value (the area top 1 value when the A inputs are selected by the selectors 1 and 3) is set. Output to the B input of the comparator 4. Further, when the clock CK4 = 1, the input B is selected and the value of the area bottom (the value of the area bottom 1 when the A input is selected by the selectors 2 and 3) is output to the B input of the comparator 4. In the comparator 4, the value of the area top is input (input B) when the clock CK4 = 0, and the basic address data or the upper limit correction loop in the upper limit correction loop, which is the addition value of the address pointer and the operand value or the coefficient data, is input. The address data (input A) is compared, and the clock CK4 = 1
At this time, the value of the area bottom is input (input B) and is compared with the address data whose upper limit correction has been completed or the address data in the lower limit correction loop (input A) described later.
That is, the comparator 4 compares the input B value input from the selector 3 with the input A value which is address data, and when the input A value> the input B value, outputs a signal to the A input of the next selector 5. If the input A value is smaller than the input B value, a signal is output to the B input of the selector 5. In the selector 5, since the area top value is selected as the A input by the selector 3 when the clock CK4 = 0, the basic address data or the address data in the upper limit correction loop exceeds the area top value. Only when it is present, the selector signal is output to the selector 11 described later. Similarly, the clock CK
When 4 = 1, the area bottom value in the selector 3 is B
Since it is selected as the input, the selector signal is output to the selector 11 only when the address data whose upper limit correction is completed or the address data in the lower limit correction loop is below the value of the area bottom.

On the other hand, the difference calculator 6 in the difference calculation configuration calculates the difference between the input T value at the area top and the input B value at the area bottom. This difference is complemented in order to perform the upper limit correction by the addition operation in the adder 10 described later at the time of the upper limit correction at the time of overflow in which the difference is subtracted from the basic address data or the address data in the upper limit correction loop. It is converted to 2's complement by the device 7. In the next selector 8, when the clock CK4 = 0 (when it is determined by the above flow check configuration whether basic address data or address data in the correction loop overflows), it is input as the A input. The value of the two's complement of the coming difference is output to the adder 10 described later. Further, when the clock CK4 = 1 (when it is determined by the above flow check configuration whether the basic address data or the address data in the correction loop is underflowed), B
The difference value input as an input is output to the adder 10.

Further, the configuration of the adder 10, the selector 11, the latch 12, and the latch 13 from the selector 9 is as follows:
For the basic address data or the address data in the correction loop input as the input A to the basic address data or the upper limit thereof while repeatedly performing the upper limit correction or the lower limit correction when the above overflow or underflow is determined. The address data that has undergone the lower limit correction is finally determined and output as a memory access address.

The adder 10 uses the difference value or the two's complement value of the difference sent from the selector 8 as basic address data, address data after completion of upper limit correction, or address data in a correction loop. Addition operation (difference 2
The process of adding the complement value of is equivalent to the process of subtracting the difference), and outputs it as the B input to the next selector 11. Further, the selector 11 selects the operation value from the adder 10 as the B input when the selector signal is input from the selector 5 (that is, when the overflow determination or the underflow determination is made). If the selector signal is not input (that is, when there is neither overflow nor underflow, or when it disappears), A Select the input address data.

As shown in FIG. 2, the clock CK4 described above is used.
Is a clock obtained by dividing the clock CK1 into quarters. In the time slot of the clock CK4 = 0 (that is, when the input A is selected in each selector 3, 5 and 8), t1 = 0 continues for one cycle of CK1, and the selector 9 indicates the value of the address pointer and the operand value. Alternatively, the added value of the coefficient data (basic address data described above) is selectively output, and the comparator 4 compares the output value with the area top. This comparison result is A> B,
If overflow is determined, selector 1
1 selects the B input and performs upper limit correction by adding the value of the two's complement of the difference to the basic address data (subtracting the difference) (the output result of the addition processing performed by the adder 10 select). The correction value is 1 of the clock CK1.
It is latched in the latch 12 every clock. The latched address data is returned to the selector 9 and becomes its B input. Since t1 = 1 for the next cycle of CK1, the selector 9 selectively outputs the B input. Like this CK
The same process is repeated within the range permitted by cycle 1 to loop until the address overflows.

Next, in the time slot of the clock CK4 = 1 (that is, when the input B is selected in the selectors 3, 5 and 8), the upper limit corrected address data output from the selector 9 and the area bottom are output. To compare. If the comparison result is A <B and it is determined that there is an underflow, the selector 11 similarly selects the B input and performs the lower limit correction of adding the difference value to the address data for which the upper limit correction has been completed (( The output result of the addition process performed by the adder 10 is selected). These correction values are latched in the latch 12. This latched address data is returned to the selector 9 and becomes its B input, and CK1
For several cycles of t1 = 1, the selector 9
Select and output the input. In this way, the same processing is repeated within the range allowed by the CK1 cycle, and looped until there is no address underflow.

On the other hand, in the comparator 4, when the output address data of the selector 9 is between the area bottom and the area top to be paired (when it is not overflow or underflow), the selector 11 outputs the selection output of the A input. repeat. At the end of one cycle of the clock CK4, the value latched by the latch 12 is latched by the next latch 13 (latched before the result of the latch 12 is cleared), and the confirmed memory access is performed. It is output as an address.

When the next one cycle of the clock CK4 is started, the selector 9 selects the incremented address data by incrementing the address pointer and repeats the above processing. Since these processes are performed in parallel, as shown in FIG. 3, the memory area for job EFF1 and the memory area for job EFF2 can be instructed at the same time, and each job program can access each independent memory area. Will be done.

The above configuration was adopted as a DSP configuration for applying effects such as a chorus effect and a delay effect to a musical sound emitted from an electronic musical instrument. One D
In SP, these effects are applied to job EFF1 and job EF.
In the system configuration in which each processing is performed in time division as F2, the processing is performed according to the flow shown in FIG.

When the power is turned on, first, the offsets 1 and 2 (area bottoms 1 and 2) are set in the two offset registers, and the area tops 1 and 2 are set in the two area registers (S0). Next, the state becomes the sampling clock waiting state (S1). Since the Lch input is the same as the signal flow of the main routine in the conventional DSP shown in FIG. 8, the signal from IN1 and IN2 is transferred to the register I by referring to FIG.
Incorporated as In1 and In2 into 1 and I2, Lc
The h output outputs the signal data of Out1 and Out2 from the temporary registers O1 and O2 on the output side to OUT1 and OUT2 in the figure (S2).

Next, when the value of the ACR flag is 0, the area top 1 and the area bottom 1 are selected, and the job EFF1
The area area for use is designated (S3). And EF
Whether F1 is valid or not is determined, and the flow of the effect program for job EFF1 is passed through normally (effect addition processing is performed), or the acoustic effect program is executed for pre-processing by changing the acoustic effect. It is checked whether or not to pass through (S4). When the sound effect is changed, a part of the instruction memory is rewritten or pre-processing such as clearing of the coefficient RAM and the data RAM is performed. Therefore, if a regular normal effect program is processed, the process will run out of control. This is because there is a risk that noise will be generated or a large amount of noise will be generated. The information indicating whether or not this job is valid may be performed by the master CPU by changing the value of an address in the coefficient RAM, or a signal may be directly sent from the master CPU to a general-purpose input port (not shown) of the DSP. You can send it.

When the job EFF1 is normal, an effect program (for example, chorus effect) is called (S).
5). This effect program call uses the instruction memory (I
-A program is selected from a plurality of acoustic effect addition routines stored in a storage area of RAM) by a program counter. The total of the selectable sound effect programs must fit in a predetermined storage area of the instruction memory. After the acoustic effect addition routine processing, the signal data is multiplied by the coefficient C1a, and the register I
The input In1 stored in 1 is multiplied by the coefficient C1b, both values are added, and the result is stored in the temporary register O1. At this time, by appropriately controlling the values of the coefficients C1a and C1b, it is possible to crossfade the signal to which the acoustic effect is added and the signal to which the acoustic effect is not added (S7).

If the EFF1 is invalid, a weight equivalent to the number of steps of the EFF1 is applied before passing through the sound effect program (S6). Here, for example, a loop instruction built into the DSP is used to loop for a required number of steps (EFF written in the coefficient RAM).
Load the number of steps of 1 and delay by that number). In this loop, the redundant function is omitted in the DSP used here, and the input and output of the R signal and the L signal are the same port, and the WS signal rises (or falls).
It has to be performed within a predetermined time (corresponding to the serial data R0 and L0 processing time). Then, as described above, crossfade processing is performed between the musical tone signal to which the acoustic effect addition processing has not been performed, and further crossfade processing between the musical tone signal and the musical sound signal to which the new acoustic effect has been added. Then, the sound effect changing process is ended.

Next, when the value of the ACR flag is 1, the area top 2 and the area bottom 2 are selected, and the job EFF2
The area area for use is designated (S8). After that, the same processing as described above is repeated for the job EFF2.

Then, Rch input is performed, and signals from IN1 and IN2 in FIG. 8 are transferred to registers I1 and I2.
2 as In1 and In2, and the Rch output is output from OUT1 and OUT2 from the temporary registers O1 and O2 on the output side to Out1 and Out.
The signal data of t2 is output (S9).

Finally, the value of the pointer (DPTR) of the internal memory (D-RAM) and the value of the pointer (XPTR) of the external RAM (X-DRAM) are incremented (+1) to return to the state of waiting for the sampling clock ( S10). This is a program based on the next sampling, and the same data R
This is because even if the AM address is specified, the +1 address is actually automatically accessed.

In the above configuration, a dedicated memory access area is secured for each of these job programs by the designation by the offset register and area register set for each job (independent memory area for each job EFF). since there is assigned) gets rid causing problems such as accessing a memory area of another job during the first job execution, these jobs if parallelism therefore a program of the same contents However, they cannot access the other memory area. In the above embodiment, the configuration in which the memory access areas are set for the job EFF1 and the job EFF2 has been described. However, when there are more jobs than that, each independent memory access area should be set similarly. It goes without saying that is possible.

FIG. 5 and FIG. 6 show the configuration of one embodiment of the memory address control device of the DSP as a reference example .
In this configuration, like the configuration of the above-described embodiment, it is a configuration of a part that performs address control for the internal memory and external memory of the DSP, and an address pointer that stores a memory address, a value of the address pointer, and an operand value on a program Or, it has a boundary register for setting and storing an address which becomes a boundary with respect to an address generated based on coefficient data, and a program (not shown) for processing the job EFF1 and the job EFF2 in a time-sharing manner. Due to the circuit configuration as shown, each of these job programs uses different address pointers, and, as shown in FIG. 6, addresses generated based on the values of these address pointers and the operand value or coefficient data on the program. Is the job EFF with the address stored in the boundary register as a boundary. It is configured to access the memory area for the sound effect program memory region and job EFF2 for sound effects program.

In the configuration of FIG. 5, the direction setting flag (APR flag) for setting the vertical use range is used with the boundary address stored as a boundary register in the register set as a boundary, and when the APR flag = 0. , Specifies the address area for job EFF1 shown in FIG.
When the R flag = 1, the address area for the job EFF2 is designated. Further, the configurations of the comparator 14 and the selector 15 compare the basic address data, which is the added value of the address pointer and the operand value or the coefficient data, with the boundary address data set in the boundary register, and perform the comparison for the job EFF1. When the address area is specified, the judgment is made when the basic address data exceeds the boundary address, and when the address area for the job EFF2 is specified, the basic address data becomes the boundary. The configuration is such that a determination is made when the address falls below the address. Further, the configuration of the complement converter 16, the selector 17, and the adder 18 is a configuration for correcting the address data when it is determined by the determination configuration that the address data exceeds or falls below the boundary address. .

In this configuration, when the basic address data exceeds the boundary address when the address area for the job EFF1 is designated, as shown in FIG. Subtract only the boundary address,
Further, when the basic address data falls below the boundary address when the address area for the job EFF2 is designated, as shown in FIG.
Only the boundary address is added. With such a configuration, 0 to 0 are set for the job EFF1.
Address area up to the boundary address, job EFF
For 2, the address areas from the boundary address to the address upper limit value can be set respectively, and each job program cannot access the memory beyond the boundary. Further, even if the programs have the same contents, it is possible to make the other memory area inaccessible in each job. When the basic address data exceeds the boundary address during the designation of the address area for the job EFF1, the adder 18 performs the address data correction process of subtracting the boundary address from the exceeded value. In order to carry out the addition operation of, the complement converter 16 obtains the value of the two's complement of the boundary address value, and the adder 18 adds it to the basic address data.

In the above configuration, when the APR flag = 0, the selectors 15 and 17 selectively output the A input. As a result, the address area for the job EFF1 is designated.
At this time, the comparator 14 compares the basic address data (A input) with the boundary address (B input),
When it is determined that the address data exceeds the boundary address (A> B), a signal is output to the A input of the selector 15, and the selector 15 further outputs a select signal to the selector 19. On the other hand, since the selector 17 selectively outputs the A input as described above, the 2's complement value of the boundary address obtained by the complement converter 16 is output to the adder 18. The adder 18 performs addition processing of the complemented value and the basic address data (corresponding to processing of subtracting the boundary address portion from the exceeded address data), and outputs it as the B input of the selector 19. As a result, the selector 19 selectively outputs the correction value of the address data output from the adder 18 and input as the B input. If the comparator 14 determines that A <B, the selector 15 does not output the select signal. Therefore, the selector 19 directly outputs the basic address data input as the A input as the memory access address. To be done.

When the APR flag = 1, the selector 15
And 17 selectively output the B input. As a result, the address area for the job EFF2 is designated. At this time, the comparator 14 compares the basic address data (A input) with the boundary address (B input) and determines that the address data is below the boundary address (A
<B), a signal is output to the B input of the selector 15, and the selector 15 further outputs a select signal to the selector 19. On the other hand, since the selector 17 selectively outputs the B input as described above, the value of the boundary address is directly added to the adder 1
8 is output. The adder 18 performs addition processing of the value of the boundary address and the basic address data, and outputs it as the B input of the selector 19. As a result, the selector 19 selectively outputs the correction value of the address data output from the adder 18 and input as the B input. When the comparator 14 determines that A> B, the selector 15 does not output the select signal. Therefore, the selector 19 directly outputs the basic address data input as the A input as the memory access address. To be done.

In the above configuration, the address data is incremented by incrementing the address pointer, and the above process is repeated. Since these processes are done in parallel,
As shown in FIG. 6, the memory area for the job EFF1 and the memory area for the job EFF2 can be designated at the same time, and each job program accesses each independent memory area.

The above configuration was adopted as a DSP configuration for applying effects such as a chorus effect and a delay effect to a musical sound emitted from an electronic musical instrument. One D
In SP, these effects are applied to job EFF1 and job EF.
In the system configuration in which each processing is performed in time division as F2, the processing is performed according to the flow shown in FIG.

When the power is turned on, first, a boundary address is set in the register set (S11). Next, the state becomes the sampling clock waiting state (S12). Similarly for the Lch input, referring to FIG. 8, the signals from IN1 and IN2 are input to the registers I1 and I2 and In1.
And In2, and the Lch output outputs the signal data of Out1 and Out2 from the temporary registers O1 and O2 on the output side to OUT1 and OUT2 in the figure (S13).

Next, when the value of the APR flag is 0, the area area for the job EFF1 in the range of 0 to the boundary address is designated (S14). Then, it is determined whether or not EFF1 is valid, and the flow of the effect program for job EFF1 is passed through normally (effect addition processing is performed), or
Alternatively, it is checked whether or not the sound effect program is to be passed through because of pre-processing by changing the sound effect (S1).
5). The information indicating whether or not this job is valid may be performed by the master CPU by changing the value of an address in the coefficient RAM, or a signal may be directly sent from the master CPU to a general-purpose input port (not shown) of the DSP. You can send it.

During the normal time when the job EFF1 is valid, an effect program (for example, chorus effect) is called (S1).
6). This effect program call uses the instruction memory (I
-A program is selected from a plurality of acoustic effect addition routines stored in a storage area of RAM) by a program counter. The total of the selectable sound effect programs must fit in a predetermined storage area of the instruction memory. After the acoustic effect addition routine processing, the signal data is multiplied by the coefficient C1a, and the register I
The input In1 stored in 1 is multiplied by the coefficient C1b, both values are added, and the result is stored in the temporary register O1. At this time, by appropriately controlling the values of the coefficients C1a and C1b, it is possible to crossfade the signal to which the acoustic effect is added and the signal to which the acoustic effect is not added (S18).

If the EFF1 is invalid, a weight equivalent to the number of steps of the EFF1 is applied before passing through the sound effect program (S17). Here, for example, a loop instruction built in the DSP is used to perform a loop for a required number of steps (EF written in the coefficient RAM).
Load the number of steps in F1 and delay by that number). Then, as described above, crossfade processing is performed between the musical tone signal to which the acoustic effect addition processing has not been performed, and further crossfade processing between the musical tone signal and the musical sound signal to which the new acoustic effect has been added. Then, the sound effect changing process is ended.

Next, when the value of the APR flag is 1, the area area for the job EFF2 in the range from the boundary address to the upper limit of the address is designated (S19). After that, job EFF2
With respect to, the same processing as described above is repeated.

Then, Rch input is performed, and I in FIG.
The signals from N1 and IN2 are transferred to registers I1 and I2.
In, and import as In1 and In2, Rch output is
To the OUT1 and OUT2 in the figure, the temporary registers O1 and O2 on the output side are changed to Out1 and Out2.
The signal data of is output (S20).

Finally, the value of the pointer (DPTR) of the internal memory (D-RAM) and the value of the pointer (XPTR) of the external RAM (X-DRAM) are incremented (+1) to return to the state of waiting for the sampling clock ( S21). This is a program based on the next sampling, and the same data R
This is because even if the AM address is specified, the +1 address is actually automatically accessed.

In the above reference example configuration, a dedicated memory access area is secured for each of these job programs by the boundary address set at the boundary of the address area for each job (independent for each job EFF. Since the memory area is allocated), it is possible to prevent problems such as accessing the memory area of another job during execution of one job. In the above configuration as well, the configuration in which the memory access areas are set for the job EFF1 and the job EFF2 has been described. However, when there are more jobs than that, each independent memory access area can be similarly set. It goes without saying that it is possible.

The DSP used in this embodiment is
Has the characteristic of being able to calculate multiple independent programs in a time-sharing manner within one sampling time, so it can process multiple acoustic effects such as electronic musical instruments, Desk Top Music, and karaoke. It can also be used for electronic tone generation systems and time-division processing systems such as car audio, vibration analysis, and active noise filters.

[0053]

According to the configuration of claim 1 which has been described in detail above, according to the present invention invention, to indicate different memory areas before each job program for processing in a time division offset register and area registers are runs A memory area that is set and, on the premise of that, an address value generated based on the value of the address pointer and the operand value or coefficient data on the program is determined for each job based on the offset register and area register used by the job. Since each address is corrected to the internal address, each job program has an effect of accessing different memory areas. Therefore, for each job
To be able to allocate different memory areas
Ri, memory address independently for each individual job during parallel processing of a plurality of jobs are managed, even the plurality of jobs if parallel processing because of a program of the same contents, the other memory area to each other Will not be accessible.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a circuit configuration of an embodiment of a memory address control device of a DSP according to claim 1 of the present application.

FIG. 2 is a time table showing the operation timing of the address control circuit in the above configuration.

FIG. 3 is an explanatory diagram showing a memory area allocation configuration of the DSP in the above configuration.

FIG. 4 is a flowchart showing a processing flow of a program when the above configuration is adopted as a configuration of a DSP for applying an effect to a musical sound emitted from an electronic musical instrument.

FIG. 5 is a reference example of a memory address control device of a DSP .
It is a schematic diagram showing a circuit configuration that.

FIG. 6 is an explanatory diagram showing a memory area allocation configuration of the DSP in the above configuration.

FIG. 7 is a flowchart showing a processing flow of a program when the above configuration is adopted as a configuration of a DSP for applying an effect to a musical sound emitted from an electronic musical instrument.

FIG. 8 is an explanatory diagram showing a signal flow of a main routine in a conventional DSP.

FIG. 9 is an explanatory diagram showing a memory map of I-RAM and C-RAM of the DSP.

FIG. 10 is an explanatory diagram showing a conventional address control circuit configuration in a DSP and a memory area allocation configuration.

FIG. 11 is an explanatory diagram showing a visual data flow on an external memory according to the conventional DSP configuration.

FIG. 12 is a program flowchart in a conventional DSP.

[Explanation of symbols]

1, 2, 3, 5, 8, 9, 11, 15, 17, 19
Selector 4, 14
Comparator 6
Differentiator 7, 16
Complement converter 10, 18
Adders 12, 13
latch

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-2-137514 (JP, A) JP-A-7-219839 (JP, A) JP-A-3-222043 (JP, A) JP-A-60- 15762 (JP, A) JP 53-146542 (JP, A) JP 5-274276 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9/46 G06F 12 / 00-12/06 G06F 12/14

Claims (2)

(57) [Claims] 1. An offset register for storing an offset address, an address pointer for storing a memory address, and a memory address for an address generated based on a value of the address pointer and an operand value or coefficient data on a program. It has an area register that specifies an allowable range and a program that processes a plurality of jobs in a time-sharing manner.These job programs use different offset registers and area registers, respectively, and commonly use the above address pointer, Those offset registers
And d rear register is set to indicate the different memory areas before each job program to be processed by the time-division is performed, the operand values on the value of the address pointer and the program also
Corrects the address value generated based on the coefficient data to the address value in the memory area determined based on the offset register and area register used by the job for each job, so that each job program can store different memory areas. A memory address control device of a DSP characterized by accessing. 2. The DSP memory address control device according to claim 1, wherein the offset register in each job program indicates a lower limit of the memory address, and the area register in each job program indicates an upper limit of the memory address. The memory address control device of the DSP according to claim 1.