JP3477056B2 - Data transfer device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device for transferring data between a plurality of disk devices and a main storage device.

[0002]

2. Description of the Related Art In recent years, a video-on-demand system and a video server system, which deliver video data to each user in response to a plurality of user requests, have been put into practical use. In these systems, a data transfer device that transfers video data from a plurality of disk devices to a buffer memory at high speed is used.

In the data transfer device, it is necessary to sequentially read the video data determined according to the user's request from a plurality of disk devices and transfer the video data to the buffer memory. FIG. 20 is a block diagram showing the configuration of a data transfer device provided in a conventional video server. This data transfer device sequentially reads video data in response to a user request from the disk device and stores it in the main memory (buffer memory for video data) as the video data to be distributed. Therefore, the magnetic disk devices 22a, 22b, 22c. , A disk access unit 23, a processor 24, and a main memory 25.

Magnetic disk devices 22a, 22b, 22c
Is connected to a SCSI (Small Computer System Interface) bus and stores compressed video data such as a movie. Each magnetic disk device has an internal buffer (disk cache) for temporarily storing read or write data, and reads / writes data when the bus use right is acquired. Further, each magnetic disk device has a disconnect function and a reconnect function. The disconnect function is a function that temporarily releases the bus to another disk device when a head seek occurs or when the internal buffer becomes empty during data reading / writing. Each magnetic disk device generates an interrupt to the processor 24 via the disk access unit 23 at the time of disconnection. The reconnect function is a function for reacquiring the bus that was temporarily released when data was stored in the internal buffer after disconnection.

The disk access unit 23 controls the read / write of the magnetic disk devices 22a, 22b, 22c (disk access control) and the read / write data of the magnetic disk devices 22a, 22b, 22c into the main memory 25 and the respective disks. Control (DMA (Direct Memory Access) control) for direct transfer to and from the device is performed. Regarding the above-mentioned disk access control, the disk access unit 23 receives a read / write command (hereinafter referred to as a disk command) of the magnetic disk device from the processor and changes from a SCSI bus release state (bus free phase) to an arbitration state (arbitration phase). )
When the bus use right is acquired through the above, the bus can be used by shifting to the bus occupation state (selection phase, transfer phase).

Regarding the DMA control, the disk access unit 23 sequentially reads the DMA command table created on the main memory 25 by the processor 24,
The main memory 25 stores the data read from the magnetic disk device.
Is directly written to the data area of (the DMA chain command method). An example of the DMA command table is shown in FIG. As shown in the figure, the DMA command table is stored in the main memory 2
5 is an array of DMA commands consisting of the start address of the data area 5 which is the transfer destination and the number of data (data size) to be transferred to the data area. One DMA command consists of, for example, 4 bytes for each address and data size. Normally, when the main memory is virtual memory, the data size specified by the DMA command is specified within a range that does not exceed one page (for example, 4 kbytes) of virtual memory. Therefore, when reading a large amount of video data (several hundreds of kilobytes to several megabytes) at a time like a video server, a DMA command table in which a large number of DMA commands are arranged is required. Further, since one DMA command table also needs to be created so as not to exceed one page, there is a data size limit that can be specified in one DMA command table.

The processor 24 performs the following functions by executing the program stored in the main memory 25. That is, the processor 24 creates the above-mentioned DMA command table in order to sequentially read the video data in accordance with the user's request by each predetermined size (for example, the size corresponding to one second of video) from each disk device and store it in the main memory 25. Issuing the above disk command, DMA start instruction,
It processes the interrupt request from the disk access unit 23. The interrupt requests received by the processor 24 mainly include a table update interrupt request and a disconnect interrupt request.

The table update interrupt request occurs when there is a shortage of unexecuted DMA commands in the DMA command table during data transfer. That is, when the data size specified by the disk command is larger than the data size specified by the DMA command table, this occurs when the data transfer is completed according to the DMA command at the end of the DMA command table. For example, when a 512 Kbyte main storage area is designated in the DMA command table and a disk command for reading 1 Mbytes of data is executed, the DMA command table is updated when about 512 Kbytes of data are transferred. Interrupt is generated. In response to this interrupt request, the processor 24 performs interrupt processing for updating the DMA command table. The disconnect interrupt request is
This occurs when the magnetic disk device makes the above disconnection. In response to this interrupt request, the processor 24
In preparation for the subsequent reconnection, the state is saved, the remaining transfer byte number is calculated, and the recovery process for correcting the address and size of the DMA command is performed.

FIG. 22 is an explanatory diagram showing an example of the occupation timing of the SCSI bus and the interrupt processing timing of the processor 24.

In the figure, on the time axis indicating the bus timing, the solid line portion shows the section where the magnetic disk device has acquired the bus use right, and the broken line portion shows the section where the bus is released. “R” indicates the timing of reconnection or connection (first bus right acquisition), and “D” indicates the timing of disconnection. Further, on the time axis indicating the interrupt processing timing, “d” indicates a disconnect interrupt processing section and “c” indicates a table update interrupt processing section. As shown in the figure, while the processor 24 updates the DMA command table in the table update interrupt process, the disk access unit 23 continues the data transfer after updating the table without releasing the bus. Further, in the disconnect interrupt process, the processor 24 performs the above recovery process. After the disconnection interrupt process, the released bus is occupied by the disk device by reconnection from another magnetic disk device or by issuing a disk command by the processor.

FIG. 23 is an explanatory diagram showing a state change until one magnetic disk device receives a disk command and completes the data transfer of the size designated by the disk command. As shown in the figure, when the disk command is issued from the processor 24 in the bus released state (S41), the disk access unit 23 refers to the DMA command table and executes data transfer between the magnetic disk device and the memory. (S42). In the meantime, each time the unexecuted DMA command runs out in the DMA command table, the table is updated by the interrupt process. Further, the operation of disconnecting when the disk internal buffer becomes empty, reconnecting when the data is accumulated in the disk internal buffer, and restarting the data transfer is repeated (S4
3 → S44 → S42). Interrupt processing occurs at disconnection. After that, when the data transfer of the size specified by the disk command is completed, an interrupt for notifying the completion of execution of the disk command (S45) is generated (I4
3). In this way, data transfer for one disk command is performed to one magnetic disk device. In FIG. 20, three magnetic disk devices 22a, 22b, 22
Since disk commands are sequentially issued to c, when one magnetic disk device is disconnected, another magnetic disk device is reconnected.

[0012]

However, the above-mentioned conventional data transfer device has a problem that the throughput of data transfer cannot be improved because of the overhead of the processor.

The reason why the overhead is generated is as follows.
This is because table update interrupts and disconnect interrupts frequently occur, and data transfer is substantially stopped during each interrupt process.

Secondly, when the bus is released by the disconnection, the processor repeatedly attempts the bus use right acquisition processing to issue a new disk command, so that the processing for the next data transfer of the processor ( DMA
Command table creation, disk command creation, DMA
This is because it is not possible to proceed (such as creating a boot instruction). The bus use right acquisition process here is a process in which the processor checks the released state of the bus via the disk access unit and causes the disk access unit 23 to acquire the bus use right after an arbitration phase.

In view of the above points, the present invention provides a data transfer device for transferring data between a plurality of disk devices connected to a bus and a memory, the data transfer device having improved data transfer throughput. The purpose is to

A further object of the present invention is to provide a data transfer device capable of promptly issuing a disk command.

[0017]

In order to solve the above problems, the present invention provides data to be DMA-transferred between a plurality of bus-connected disk devices and memories according to a direct memory access (hereinafter abbreviated as DMA) command table. In the transfer device, the disk device temporarily releases the bus use right according to the state of its internal buffer, and reacquires the temporarily released bus use right. Data transfer destination area start address and data size to be transferred are arranged in accordance with the contents of a DMA command table in which a DMA command table is arranged, data transfer is performed between the disk device and the memory, and the bus usage right Of the disk access unit that issues a disconnect interrupt request when the temporary release of the bus usage right is detected. , If there is disconnection interrupt request from the disk access unit, and executes the processing for it, and a processor for executing a process of updating the DMA command table, the processor,
Transfer data size specified in the DMA command table
Continuous without the disk unit releasing the right to use the bus
The maximum transfer size for data transfer
It is characterized in that the DMA command table is generated . According to this configuration, when the disk access unit detects the temporary release of the bus use right, the command table is updated for restarting the data transfer of the disk device, so that the occurrence of the table update process is eliminated or reduced. You can As a result, the overhead of the data transfer device can be reduced and the throughput of data transfer can be improved.

The disk device has an internal buffer.
Data from the internal buffer to the bus and the disk
The data from the memory to the internal buffer in parallel
However, the maximum data size S that can be continuously transferred is S.
_trans satisfies (Equation 1)

[Equation 1] Here, B_inner is a disc inside the disc device.
From B to bus to the internal buffer, B_bus is the bus
Data transfer rate, S_inner_buff is inside the disk device
Capacity of the buffer, n have a configuration is an integer of 1 or more
good.

[0019]

DETAILED DESCRIPTION OF THE INVENTION

First Embodiment <Video Server Configuration> FIG. 1 is a block diagram showing the configuration of a video server having a data transfer device according to an embodiment of the present invention. This video server includes a data transfer device 1, a video information transmission unit 11, and a time slot management unit 1.
2. The exchange 13 is provided, and video data is distributed in real time to a plurality of user terminals (hereinafter referred to as terminals).

The data transfer device 1 includes magnetic disk devices (hereinafter abbreviated as HDDs) 2a, 2b, 2c, a disk access unit 3, a processor 4, and a main memory 5, and the video data stored in each HDD is stored in the main memory 5. Transfer to. The video information sending unit 11 sends the video data transferred from each HDD to the main memory 5 by the data transfer device 1 to each terminal through the exchange 13.

The time slot management section 12 indicates a time slot indicating which video data of which magnetic disk device should be read out at a constant cycle (here, 1 second) in response to video requests from a plurality of terminals. Manage tables. In this embodiment, each HDD supports up to 3 time slots (capable of supplying video data to up to 3 terminals). The time slot table is a table in which read information (terminal number and read position) for instructing the reading of video data of a predetermined size is assigned to the time slot of the HDD. Here, the predetermined size is a size corresponding to a reproduction time of 1 second, and is 1024 kbytes in this embodiment.

2A and 2B show an example of the time slot table. In FIG. 2A, for example, in the time slot 1 of the HDD 2a, read information “T07
-P10 "is assigned. T07 represents a terminal number, and P10 represents a read position. The figure shows that eight total terminal devices are using the video server. 2B shows a time slot table of the next cycle (after 1 second) of FIG. 2A. In the figure, it can be seen that the read position of each time slot is updated as compared with FIG.

FIG. 3 is an explanatory diagram showing a cycle in which the time slot table is updated. As shown in the figure, the time slot management unit 12 updates the read position at the beginning of each cycle. In the remaining time of each cycle, the video data is read by the data transfer device according to the updated read position. The exchange 13 delivers the video data read from the main memory 5 by the video information sending unit 11 to the terminals specified in the time slot table.

<Structure of Data Transfer Device> Next, the internal structure of the data transfer device 1 will be described. HDD2a-2c is S
It is connected to a CSI (Small Computer System Interface) bus and stores compressed video data such as different movies. Since these are equivalent to the magnetic disk device described in the prior art, detailed description will be omitted. However, in this embodiment, each HDD has an ID number as shown in FIG. 4, and in an arbitration state (arbitration phase) on the SCSI bus, the larger number has priority. The internal buffer of each HDD has a capacity of 256 kbytes. In addition, the read speed from the disk to the internal buffer is 5 Mbytes in each HDD.
Second, the data transfer rate of the SCSI bus is 10 Mbytes / second.

The disk access unit 3 controls reading and writing of each HDD (disk access control).
And a control for directly transferring read / write data of each HDD to and from the main memory 5 (DMA (Direct Memory Acc
ess) control). With respect to the above-mentioned disk access control, the disk access unit 3 controls the processor 4
In response to a read / write command (hereinafter referred to as a disk command) to the SCSI bus from the released state (bus free phase) of the SCSI bus to the arbitration state (arbitration phase) to acquire the bus use right, the bus occupation state (selection phase) , Transfer phase) and can use the bus.

Regarding the above-mentioned DMA control, the disk access unit 3 sequentially reads out the DMA commands in the DMA command table created on the main memory 5 by the processor 4, and the data read from the HDD is stored in the main memory 5. Write directly to the area. The DMA command table is the same as that shown in FIG. However, in this embodiment, as will be described later, the data transfer size designated by the entire DMA command table is set so as not to generate a table update interrupt request for the HDD.

By executing the program stored in the main memory 5, the processor 4 executes each program according to the read information specified in the time slot table in each cycle.
The disk access unit 3 is controlled so that the video data is read from the DD and the read video data is DMA-transferred to the main memory. Specifically, the processor 4 creates (1) a DMA command table, (2) a DMA activation instruction to the disk access unit 3, and (3) a disk access unit for each piece of read information specified in the time slot table. 3) Creation / issue of a disk command for instructing to read video data according to the read information to (3), and (4) interrupt processing in response to an interrupt processing request from the disk access unit 3.

(1) The DMA command table is shown in FIG.
As shown in, the top of the data storage area of the main memory 5
It is an array of DMA commands consisting of addresses and transfer data sizes. Both the address and the size are 4 bytes each. In this embodiment, the processor 4
The data transfer size specified by the entire DMA command table is set to be 512 kbytes or more.

FIG. 5 shows an example of the DMA command table in this embodiment. As shown in the figure, the DMA command table includes DMA commands 1 to 128. One DMA command has a data size of 4
k bytes are specified. This is because one page is 4 kbytes in the virtual memory system of the main memory 5. 12 in the same figure
The data transfer size specified by the eight DMA commands is 512 kbytes. This size is a size for preventing a table update interrupt request from being generated, and is determined by (Equation 3).

[Equation 3] Here, S_trans is the data transfer size specified by the entire DMA command table, B_inner is the data transfer speed from the disk inside the HDD to the internal buffer,
B_scsi is the data transfer rate on the SCSI bus, S_in
ner_buff is the capacity of the internal buffer of each HDD. n is an integer of 1 or more (n = 1, 2, 3, ...). In this embodiment, B_inner is 5 Mbytes / second and B_scsi is 10.
M bytes / second and S_inner_buff are 256 kbytes. In this case, the HDD is 2 when the internal buffer is full.
128 kbytes of data can be read from the disk into the internal buffer while sending 56 kbytes of data to the SCSI bus. By repeating this in sequence, the above right side is 256 + 128 + 64 + 32 + ... = 512
It will be k bytes. The right side of (Equation 3) means the theoretical maximum number that data can be continuously supplied from the HDD to the SCSI bus.

Therefore, if the data transfer size S_trans according to the DMA command table is 512 kbytes or more, a table update interrupt does not occur when data transmission is started from the internal buffer full state.

(2) The DMA activation instruction to the disk access unit 3 consists of the address of the main memory 5 indicating the storage destination of the DMA command table and the DMA transfer enable instruction.

(3) The disk command is the HDD I
D, command type (read here), disk sector number, and read size. In this embodiment, the command type is read and the read size is 1024k.
It is a byte.

(4) The interrupt processing request from the disk access unit 3 is mainly a disconnect interrupt request,
There is a table update interrupt request. The table update interrupt request is usually an interrupt that occurs when there is a lack of unexecuted DMA commands in the DMA command table during data transfer. That is, when the data size specified by the disk command is larger than the data size specified by the DMA command table, this occurs when the data transfer is completed according to the DMA command at the end of the DMA command table. For example, if a 512 Kbyte main storage area is specified in the DMA command table,
When a disk command for reading 1 Mbytes of data is being executed, an interrupt requesting an update of the DMA command table is generated at the time when data of about 512 Kbytes is transferred.

In response to this interrupt request, the processor 4
Performs interrupt processing for updating the DMA command table. Specifically, the processor 4 creates a new DMA command table for the remaining data transfer specified by the disk command, and instructs the disk access unit 3 to restart the DMA. In the data transfer apparatus of the present invention, in principle, the table update interrupt request does not occur. The disconnection interrupt request is generated when the magnetic disk device makes the above disconnection. In this embodiment, when each HDD sends data of 512 kbytes at the maximum, disconnection occurs simultaneously with disconnection.

In response to this interrupt request, the processor 4
Prepares for later reconnection, saves the state, calculates the number of remaining transfer bytes, etc., and performs the recovery process to correct the address and size of the DMA command by reflecting the result. In addition to this, the above table update It also executes processing. In the table update process here, the executed DMA command is deleted, and the entire data size specified in the DMA command table including the transferred data size or the transferred data size by the DMA command table becomes S_trans. Until the data size designated by the command is reached, a new DMA command is added to the data transfer unit 1 of this embodiment. In this way, the processor 4 also executes the table update process in the disconnect interrupt process. In combination with the above, and the data size by the DMA command table according to (Equation 3), the table update interrupt request is not generated.

<Processing Content of Processor> FIGS. 6 (1) and 6 (2) are more detailed flowcharts showing the processing content performed by the processor 4 within one cycle (one second). In FIG. 6A, the processor 4
When the time slot management unit 12 updates the time slot table (step 100), if there is unissued read information by referring to the time slot table (step 101), the corresponding DMA command table, DMA start An instruction and a disk command are created (step 102). This DMA command table specifies the transfer data size of 512 kbytes as described above, and is created within one page of the virtual storage system. Further, this disc command instructs reading of 1024 kbytes of video data.

Next, the processor 4 waits until the bus is disconnected (until the bus becomes free) (step 103), and causes the disk access unit 3 to participate in the arbitration of the bus use right in the bus free state. Attempt to acquire usage rights (step 104). When the bus usage right cannot be acquired, for example, when another HDD reconnects between the time the bus is disconnected and the time when it participates in arbitration, the attempt is repeated until the bus usage right is acquired (steps 103 to 105). ). When the bus use right is acquired, a DMA start instruction and a disk command are issued (step 106). After issuing these commands, the processor 4 repeats the same processing as above if there is the next unissued read information in the time slot table.

In this way, the processor 4 performs command issuing processing for all the read information in the time slot table during one cycle. FIG. 6B is a flowchart showing the interrupt processing of the processor 4.

When an interrupt request occurs, the processor 4 performs the above-mentioned recovery processing and DMA command table updating processing if the interrupt request is a disconnect interrupt request (steps 107 and 108). DM of the disk access unit 3 if it is not a disconnect interrupt request (that is, if it is an interrupt indicating the end of execution of a disk command)
The A status is checked and the DMA is ended (steps 107 and 109).

<Processing Content of Disk Access Unit>

FIG. 7 is a flowchart showing the processing contents of the disk access unit 3. In the figure, when the disk access unit 3 receives an arbitration start command from the processor 4 (steps 110 and 111), it tries to acquire the bus usage right (step 112). When the bus usage right is acquired, the processor 4 sends the bus usage right. SCSI according to disk command
Issue a command to the HDD (steps 112, 11
3) Then, DMA commands are sequentially read from the first entry of the DMA command table of the main memory 5 and data transfer is executed (steps 114 and 115).

The disk access unit 3 receives a reconnect request from any of the HDDs (step 11).
0, 111: no) restarts the data transfer of the HDD (steps 114, 115).

When the HDD is disconnected during the data transfer, the data transfer from the HDD is stopped,
Inside the HDD, data writing from the disk to the internal buffer continues. During this time, the disconnection interrupt process updates the DMA command table. When the internal buffer becomes full or when some data is accumulated, the HDD is reconnected, and the data transfer is restarted according to the updated DMA command table. The first aspect of the present invention configured as described above
The operation of the data transfer device according to the embodiment will be described.

FIG. 8 shows S in the prior art and this embodiment.
FIG. 6 is a diagram comparing an example of the CSI bus occupation timing and the interrupt processing timing of the processor 4. In the figure, on the time axis showing the bus timing, the solid line portion shows the section where the magnetic disk device has acquired the bus use right, and the broken line portion shows the section where the bus is released. "R"
Indicates the timing of reconnection or connection (first bus right acquisition), and “D” indicates the timing of disconnection. Further, on the time axis indicating the interrupt processing timing, “d” indicates the disconnection interrupt processing section,
“C” is the section for table update interrupt processing, and is “d / c”
Indicate disconnect interrupts of the present embodiment, respectively.

In FIG. 6B, the situation after the disk command is issued to the HDDs 2a and 2b and the disk command is issued to the HDD 2c is shown. The same applies to FIG. Since the processor 4 updates the DMA command table together with the recovery process in the disconnect interrupt process as shown in FIG. 6B, the table update interrupt request no longer occurs. FIG. 9 is an explanatory diagram showing a state change until one HDD receives a disk command and finishes data transfer of a size designated by the disk command.

As shown in the figure, when the disk command is issued from the processor 4 in the bus released state (S131), the disk access unit 3 refers to the DMA command table to transfer data between the magnetic disk device and the memory. Is executed (S132). During that time, the HDD is disconnected when the disk internal buffer becomes empty, and the HDD is reconnected when the disk internal buffer is full or a certain amount of data is accumulated, and the disk access unit 3 restarts data transfer. Repeat (S
133 → S134 → S132). After that, when the data transfer of the size specified by the disk command is completed, an interrupt for notifying the execution of the disk command (S135) is generated (I132). In this way, HDD is DM
Since the unexecuted DMA commands in the A command table are not exhausted, the table update interrupt from the disk access unit 3 does not occur. As described above, the data transfer device according to the present embodiment eliminates the table update interrupt generation factor by the following two points.

First, the processor 4 performs a recovery process and a table update process in the disconnect interrupt process. Secondly, the data transfer size specified in the DMA command table is set to be equal to or larger than the maximum size that can be continuously accessed without disconnecting the HDD. It is possible to reduce the occurrence frequency of the table update interrupt only by the first point or only the second point. Also, the above two points completely eliminate the occurrence of the table update interrupt. As a result, the data transfer apparatus 1 can reduce the processor overhead and improve the data transfer throughput.

<Second Embodiment><OverallConfiguration> A video server equipped with a data transfer device according to a second embodiment of the present invention will be described. The block diagram showing the overall configuration of the video server in this embodiment is the same as that in FIG. 1 of the first embodiment except for the processor 4 and the main memory 5. In the figure, the processor 4 and the main memory 5
Since the other components are the same as those in the first embodiment, the different points will be mainly described below.

In addition to the functions of the first embodiment, the main memory 5 further has a queue buffer (also simply called a queue) for accumulating DMA commands and disk commands.
FIG. 10 shows the configuration of the queue buffer. In the figure,
The queue buffer is a DMA for the same video data.
A plurality of command sets, which are a set of a boot instruction and a disk command, are stored, and the processor 4 stores a FIFO (First In
First Out) stored in the expression. Hereinafter, the command set will be simply referred to as a command unless otherwise specified. Processor 4
Performs command set registration processing in the queue buffer and command set issuing processing from the queue buffer to the disk access unit 3 instead of the command issuing processing shown in FIG. 6A of the first embodiment. The command set registration process and the command issuing process are performed in both the normal process (other than the interrupt process) and the interrupt process, respectively.

<Process of Registering Command in Queue of Processor 4> FIG. 11 is a flow chart showing a command registering and issuing process by the processor 4 in the normal process (other than the interrupt process). In the figure, when the time slot management unit 12 updates the time slot table (step 151), the processor 4 refers to the time slot table, and if there is unissued read information (step 152), the corresponding DMA Command table, D
Create MA start instruction and disk command.
The MA start instruction and the disk command are registered in the queue buffer of the main memory 5 (step 153). If there is no unissued read information in the time slot table and there is no command in the queue buffer (steps 152 and 15).
5) Waiting for update of the time slot table.

After registering in the queue buffer, the processor 4 executes a command issuing process from the queue buffer (step 154). FIG. 12 is a flowchart showing the command issuing process by the processor 4 in the interrupt process. In the figure, when an interrupt request occurs, the processor 4 performs the above-mentioned recovery processing and DMA command table update processing if it is a disconnect interrupt request (steps 161, 162). If it is not a disconnection interrupt request (that is, if it is an interrupt indicating the end of execution of a disk command), D of the disk access unit 3
The MA status is checked and the DMA is ended (steps 161, 163). Furthermore, the processor 4
Command issuing processing from the queue buffer is performed (step 164).

<Command Issuing Process from Queue of Processor 4> FIG. 13 is a flowchart showing the command issuing process in step 154. The same applies to step 164 described above.

First, if the command exists in the queue buffer and the bus is free, the processor 4 attempts to acquire the bus use right by causing the disk access unit 3 to participate in the arbitration of the bus use right (steps 171-173). ). When the bus use right is acquired, the command is fetched from the queue buffer, the command is issued to the disk access unit 3 (step 174), and the command is deleted from the queue buffer. At this time, the processor 4 sequentially takes out the commands from the head of the queue buffer. If the command does not exist in the queue buffer (step 171), if the command is not bus free (step 172),
If the right to use the bus cannot be obtained (step 174)
Ends the issuing process without issuing any. The operation of the data transfer apparatus according to the second embodiment of the present invention configured as above will be described.

FIG. 14 is an explanatory diagram showing the command issuing timing of the data transfer apparatus in this embodiment.
In the figure, a time slot table in a certain cycle,
The timing of command set generation by the processor 4, the timing of command registration (queue in), the timing of command issue (queue out), and the timing of reading the HDDs 2a-2c are shown. Processor 4
Generates a command sequentially from each read information of the time slot table according to the flowchart shown in FIG. Since this command is temporarily stored in the queue buffer, it is generated prior to the command issuance timing regardless of the state of the bus as shown in FIG. For comparison with the figure, FIG. 15 shows the command issuing timing of the data transfer device in the prior art. In the data transfer device of the present embodiment, it can be seen that the processor 4 is released from the bus state check and issues a command promptly as compared with FIG. This is because the queue buffer is provided and the command issuing process from the queue is performed in the interrupt process (particularly the disconnect interrupt process). In particular, since the command issuing process is performed in the disconnect interrupt process, a new command can be issued immediately when the bus becomes free, and the overhead of the processor 4 is reduced.

<Third Embodiment> The data transfer device of this embodiment is different from the data transfer device of the first embodiment only in that the processor 4 does not use interrupt processing. Since the other points are the same as those in the first embodiment, only different points will be described below. The processor 4 is configured to detect an interrupt request by software, instead of detecting an interrupt request by hardware, as compared with the first embodiment.

FIG. 16 is a flowchart showing the processing contents of the processor 4 in this embodiment. In the figure, the steps indicated by broken line frames represent steps executed as interrupt processing in the first embodiment. 6A and 6B of the first embodiment in FIG. 6 is that a program checks whether or not an interrupt request is generated in steps 201, 203, and 207. For other processes, see FIG.
Since almost the same processing is performed as in (a) and FIG. 6 (b), the description thereof will be omitted. With the above configuration, in the present embodiment, the hardware interrupt is not used, and like the first embodiment,
The effect of canceling the table update interrupt request can be obtained.

<Fourth Embodiment> The data transfer device of this embodiment is different from the data transfer device of the second embodiment only in that the processor 4 does not use interrupt processing. Since the other points are the same as those of the second embodiment, only the different points will be described below. Compared to the second embodiment, the processor 4 is configured to detect an interrupt request by software instead of detecting an interrupt request by hardware.

FIGS. 17, 18 and 19 are flow charts showing the processing contents by the processor 4 in this embodiment. In the figure, the steps indicated by broken line frames are
The second embodiment represents steps executed as interrupt processing. These figures correspond to FIG. 1 of the second embodiment.
The process is the same as that of FIG. 1, FIG. 12, and FIG. 13, and is configured to check by a program whether or not an interrupt request is generated particularly in steps 223 and 224 of FIG. 17 and step 232 of FIG. The other processes are almost the same as those in FIGS. 11, 12, and 13, and thus the description thereof is omitted. With the above configuration, in the present embodiment, it is possible to obtain the effect that the table update interrupt request is canceled and the processor overhead is reduced as in the third embodiment, without using a hardware interrupt.

In each of the above embodiments, the processor 4
Is not executed as the update process of the DMA command table
The MA command is shifted so as to be packed from the head of the DMA command table in order, a new DMA command is generated for the remaining fields, and the entire DMA command table is updated. The DMA command is executed from the entry. Instead of this,
The processor 4 rewrites only the executed DMA command in the DMA command table as the table updating process, and the disk access unit 3 restarts the data transfer from the DMA command suspended after the reconnection, and the last entry of the DMA command table The execution of the DMA command of the first entry may be continued after the execution of the DMA command.

In the second and fourth embodiments, the processor 4 fetches commands in order from the head of the queue buffer, but the following may be done. That is, if the first command cannot be issued, the processor may wait for issuance if the next command is addressed to the same disk device, and may issue it if the next command is addressed to another disk device. The above assumes that the HDD itself does not queue commands. If the HDD has a command queuing function, the problem that the first command cannot be issued is solved.

Further, instead of the HDD in each of the above embodiments, a storage device for disconnecting and reconnecting,
For example, an optical disk drive or a magneto-optical disk drive may be used.

Further, since the operation of the data transfer device in each of the above-described embodiments is controlled by the processor, the data transfer device of the present invention is stored in the main memory of the conventional data transfer device in each flowchart shown in each embodiment. This can be realized by newly writing a program describing the processing of. In this case, the program may be recorded in a storage medium readable by the processor of the data transfer device, and the processor may write the program from the storage medium to the main memory.

[0063]

The present invention is a data transfer device for performing a DMA transfer between a plurality of disk devices connected to a bus and a memory according to a DMA command table, wherein
The disk device uses the bus according to the state of its internal buffer.
Use the bus after releasing the right temporarily
Reacquire the rights, the data transfer apparatus, data of memory - de to be transferred as the head address of the data transfer destination area - Tasaizu and contents of the DMA command <br/> table that DMA command are arrayed showing the According to the following, transfer data between the disk device and memory and monitor the release of the bus right,
When a temporary release of the bus use right is detected, if there is a disk access unit that issues a disconnection interrupt request and a disconnection interrupt request from the disk access unit, processing for it is executed and the DMA is executed.
A processor that executes command table update processing,
And the processor includes a DMA command table
The disk device uses the specified transfer data size on the bus.
Maximum continuous data transfer without releasing license
The DMA command table so as to be equal to or larger than the transfer size of
Is generated. According to this configuration, de
When the disk access unit detects the temporary release of the bus use right, the command table is updated for restarting the data transfer of the disk device, so that the occurrence of the table updating process can be eliminated or reduced. As a result, the data transfer apparatus 1 can reduce the overhead and improve the throughput of data transfer. In addition,
The processor uses the transfer specified in the DMA command table.
Data size, disk unit releases bus right
Less than the maximum transfer size that can be continuously transferred without
Generate the DMA command table as above
The disk device has the right to use the bus.
When the DMA command table is
The table is updated without running out of DMA commands in the row.
It is possible to completely eliminate the occurrence of new processing.

Further, the data transfer device further includes a command generating means for generating a disk command for instructing each disk device to read or write up to a fixed number at predetermined intervals, and a disk generated by the command generating means. Queue holding means for holding commands in a queue and a first disk device in the disk access unit
When temporary release of the bus use right by is detected, and a command issuing unit for issuing eject the disc command for the second disk device from the queue, the de
When a disk command is issued by the command issuing means, the disk access unit acquires the bus use right and acquires the second disk.
In this configuration, data transfer is started with the disk device .
According to this configuration, the generated command is once stored in the queue holding means as a queue, so that the disk command is issued more than the actual issuing timing regardless of the bus state (whether in use or released). It can be generated in advance, and the overhead of the data transfer device can be reduced to improve the throughput of data transfer.

[0065] The data transfer apparatus of the present invention, the disk command generation means for generating a disk command up to a certain number instructing data reading or writing of a predetermined size in disk device, for each disk device for every predetermined cycle If, de memory - performs data transfer between the disk device and the memory in accordance with the contents of the DMA command table that DMA command are arrayed showing the Tasaizu - de to be transferred as the head address of the data transfer destination area , The bus access right is monitored, and when it is detected that the disk device reading or writing data according to the disk command temporarily releases the bus right, the disk access unit that issues the disconnect interrupt request and the disk If there is a disconnect interrupt request from the access unit, And executes the processing, the DMA
A processor that executes command table update processing,
The processor is provided with a command to the DMA command table.
The disk device uses the specified transfer data size on the bus.
The maximum that can transfer data continuously without releasing the right
The DMA command table so that the transfer size is not less than
Is generated . According to this configuration,
When the disk access unit detects the temporary release of the bus use right, the command table is updated for restarting the data transfer of the disk device, so that the occurrence of the table updating process can be eliminated or reduced. As a result, the data transfer apparatus can reduce the overhead and improve the throughput of data transfer.

The data transfer apparatus further includes a queue holding means for holding the disk command generated by the disk command generating means in a queue, and a disk access means.
When the temporary release of the right to use the bus is detected by the
And a command issuing unit for issuing the disk device from the queue remove the disc command, the disk A
The access section starts data transfer when the disk device is issued a disk command by the command issuing means,
It is configured to resume data transfer when the disk device that has temporarily released the bus use right regains the bus use right. According to this configuration, the generated command is once stored in the queue holding means as a queue, so that the disk command is issued more than the actual issuing timing regardless of the bus state (whether in use or released). It can be generated in advance, and the overhead of the data transfer device can be reduced to improve the throughput of data transfer.

[0067]

The disk device has an internal buffer and executes data transmission from the internal buffer to the bus and data writing from the disk to the internal buffer in parallel, and the first data size S_trans is the above. (Equation 1)
Configured to meet. With this configuration, the first data size can be appropriately determined according to the data transfer rate from the disk to the internal buffer in the disk device, the data transfer rate of the bus, and the capacity of the internal buffer of the disk device. Further, according to the storage medium storing the program readable by the processor according to the present invention, the same effect as the above can be obtained by causing the conventional data transfer device to execute the program stored in the storage medium. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video server having a data transfer device according to a first embodiment of the present invention.

FIG. 2 shows an example of a time slot table.

FIG. 3 is an explanatory diagram showing a cycle in which a time slot table is updated.

FIG. 4 shows ID numbers (SCSI IDs) of magnetic disk devices and disk access units.

FIG. 5 shows an example of a DMA command table in this embodiment.

FIG. 6 is a more detailed flowchart showing the contents of processing performed by the processor within one cycle (one second).

FIG. 7 is a flowchart showing the processing contents of a disk access unit.

FIG. 8 is a diagram comparing an example of a SCSI bus occupancy timing and an interrupt processing timing in the related art and the present embodiment.

FIG. 9 is an explanatory diagram showing a state change until the HDD receives a disk command and finishes data transfer of a size designated by the disk command.

FIG. 10 shows a configuration of a queue buffer according to the second embodiment of the present invention.

FIG. 11 is a flowchart showing command registration and issue processing by a processor in normal processing (other than interrupt processing).

FIG. 12 is a flowchart showing command issuing processing by a processor in interrupt processing.

FIG. 13 is a flowchart showing command issuing processing.

FIG. 14 is an explanatory diagram showing command issuing timing.

FIG. 15 shows the command issuing timing of the data transfer device in the prior art.

FIG. 16 is a flowchart showing the processing contents of a processor in the third embodiment.

FIG. 17 is a flowchart showing the processing contents by a processor in the fourth embodiment.

FIG. 18 is a flowchart showing processing contents by a processor.

FIG. 19 is a flowchart showing processing contents by the processor.

FIG. 20 is a block diagram showing a configuration of a data transfer device provided in a conventional video server.

FIG. 21 shows an example of a DMA command table.

FIG. 22 shows an example of SCSI bus occupancy timing and interrupt processing timing in the prior art.

FIG. 23 shows a state change until the magnetic disk device receives a disk command and finishes data transfer of a size designated by the disk command.

[Explanation of symbols]

1 Data transfer device 2a Magnetic disk device 2b Magnetic disk unit 2c magnetic disk unit 3 Disk access section 4 processors 5 main memory 11 Video information sending unit 12 Time slot management section 13 exchanges

Claims (9)

(57) [Claims] 1. Direct memory access (hereinafter referred to as DMA
A data transfer device for performing DMA transfer between a plurality of disk devices connected to the bus and a memory according to a command table, wherein the disk device temporarily holds the bus use right according to the state of its internal buffer. The bus transfer right that has been temporarily released is reacquired, and the data transfer device is arranged with a DMA command indicating the start address of the data transfer destination area of the memory and the data size to be transferred. The data transfer is performed between the disk device and the memory according to the contents of the DMA command table, and the release of the bus use right is monitored. When the temporary release of the bus use right is detected, a disconnection interrupt request is issued. When there is a disk access block and a disconnect interrupt request from the disk access block, it is common to execute processing for it. And the above D
A processor for executing the MA command table update processing, wherein the processor is designated in the DMA command table.
The disk device releases the bus usage right
Maximum transfer service that can transfer data continuously without releasing
The DMA command table is generated so that
A data transfer device characterized by: 2. The disk device has an internal buffer, executes data transmission from the internal buffer to the bus and data writing from the disk to the internal buffer in parallel, and is the maximum that can transfer data continuously. Data size S_tra
ns satisfies (Equation 1) and [Equation 1] Here, B_inner is the data transfer speed from the disk to the internal buffer inside the disk device, B_bus is the data transfer speed of the bus, S_inner_buff is the capacity of the internal buffer of the disk device, and n is an integer of 1 or more. The data transfer device according to claim 1 . 3. The data transfer device further queues a command generating means for generating a disk command for instructing reading or writing up to a fixed number and a disk command generated by the command generating means for each predetermined cycle. A queue holding means for holding and a command issuing means for taking out and issuing a disk command for the second disk device from the queue when the temporary release of the bus use right by the first disk device is detected in the disk access part. When the disk command is issued by the command issuing means, the disk access unit acquires the bus use right and
3. The data transfer device according to claim 1 , wherein data transfer is started with the second disk device. 4. Direct memory access (hereinafter referred to as DMA
A data transfer device for performing DMA transfer between a plurality of disk devices connected to the bus and a memory according to a command table, wherein the disk device temporarily holds the bus use right according to the state of its internal buffer. And re-acquire the bus use right that was temporarily released, the data transfer device sends a disk command up to a fixed number for instructing the disk device to read or write data of a predetermined size in each predetermined cycle. A disk command generating means for generating the disk device, and a disk device according to the contents of a DMA command table in which DMA commands indicating the start address of the data transfer destination area of the memory and the data size to be transferred are arranged. Transfers data to and from memory, monitors the release of bus usage rights, and follows disk commands. When a disk device that is reading or writing data by detecting that the bus right of use is temporarily released is detected, there is a disk access unit that issues a disconnect interrupt request, and a disconnect interrupt request from the disk access unit, The processing for it is executed and the D
A processor for executing the MA command table update processing, wherein the processor is designated in the DMA command table.
The disk device releases the bus usage right
Maximum transfer service that can transfer data continuously without releasing
The DMA command table is generated so that
A data transfer device characterized by: Wherein said disk device has an internal buffer, and the data sent from the internal buffer to the bus, and executed in parallel with writing of data to the internal buffer from the disk, the maximum the possible continuous data transfer Data size S_tra
ns satisfies (Equation 1) and [Equation 1] Here, B_inner is the data transfer speed from the disk to the internal buffer inside the disk device, B_bus is the data transfer speed of the bus, S_inner_buff is the capacity of the internal buffer of the disk device, and n is an integer of 1 or more. The data transfer device according to claim 4 . Wherein said data transfer apparatus, and queue holding means for holding further by the disk command generated by the disk command generation unit in the queue, the temporary release of the bus use right of the first disk device in a disk access unit when but detected, and a command issuing unit for issuing eject the disc command for the second disk device from the queue, when the disk access unit is issued to the disk command by the command issuing unit, a bus use right Won and first
6. The data transfer device according to claim 4 , wherein data transfer is started with the second disk device. 7. A processor, a memory, and a bus connection with these, which temporarily releases the bus use right according to an internal state,
Further, a disk device configured to reacquire the bus use right that has been temporarily released, and reading or writing of the disk device and direct memory access (hereinafter referred to as DMA
A storage medium storing a program, which is applied to a data transfer device including a disk controller that controls a DMA transfer between a disk device and a memory according to a command table, the processor comprising: , Table generating means for generating a DMA command table in which a DMA command indicating the start address of the data transfer destination area of the memory and the data size to be transferred is arranged, and reading or writing of data of a predetermined size in the disk device. Between the disk device and the memory according to the DMA command table by activating a disk command generating means for generating a disk command up to a fixed number for each disk device for each predetermined period and a disk controller. Data reading by the transfer method and disk command A temporary release detection means for detecting, as an interrupt processing request, that the writing or writing disk device has temporarily released the bus usage right, and data transfer of the disk device when the temporary release of the bus usage right is detected. For restarting, the executed DMA commands are deleted, and new DMA commands are added until the predetermined number of DMA commands are reached or the total data size specified in the DMA command table including the transferred data size reaches the predetermined size. A program that functions as each means of a table updating means for updating a command table by adding a command , and the table generating means specifies the DMA command table.
The transfer data size that is, the disk device bus access
The maximum amount of data that can be transferred continuously without releasing the
Create the DMA command table so that the size is not less than the sending size.
A storage medium that stores a program to be created. Maximum wherein said disk device, which has an internal buffer, and the data sent from the internal buffer to the bus, and executed in parallel with writing of data to the internal buffer from the disk, the continuous data that can be transferred data size S_t of
rans satisfies (Equation 2), and Here, B_inner is the data transfer speed from the disk to the internal buffer inside the disk device, B_bus is the data transfer speed of the bus, S_inner_buff is the capacity of the internal buffer of the disk device, and n is an integer of 1 or more. The storage medium according to claim 7 . 9. The storage medium further includes queue holding means for holding the disk command generated by the disk command generating means in a queue, and temporary release of the bus use right is detected by the temporary release detecting means, A program for functioning as command issuing means for taking out a disk command from the queue and issuing it to the disk device is stored, and the transfer means starts data transfer when the disk device issues the disk command by the command issuing means, 8. disk apparatus which has been released the right to use one o'clock is characterized in that it is programmed to resume the data transfer when reacquire the bus use right
The storage medium described.