JP3473170B2 - Signal processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device such as a memory and a look-up table for delaying pixels in a TV receiver to form a vertical filter.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for higher image quality, and in satellite broadcasting, high-definition broadcasting based on the MUSE system has been put into practical use, and test broadcasting is currently being conducted. Also, there are 9 terrestrial broadcasts using the EDTVII system.
It is scheduled to start in the fifth year. Due to these demands, the video processing speed is also required to be increased. For example, MUSE requires a high-speed operation of 44.55 MHz for output. In addition, 0 interpolation processing is performed in processing for increasing the number of pixels in one line during video processing.

Further, in a process for performing a non-linear operation in video processing, the operation is performed using a look-up table using a ROM or the like.

MUSE in which a control signal is included in the video signal
When a control signal is extracted from such a signal, a control register is individually provided and the control signal is read by reading this register from the CPU.

[0005]

However, it is difficult to increase the speed in the field memory for storing the video signal, and by reading a plurality of data from the memory and sequentially selecting the data, the speed is higher than the operating frequency of the memory. A method of outputting data is in place. In addition, processing such as 0 interpolation is performed by a selector that selects 0 in the signal processing portion.

However, a selector for selecting a plurality of data from the memory and a selector for performing 0 interpolation can be similarly used.

In consideration of the image processing by the processor, there is a problem that the area becomes large if the lookup table is built in.

Further, if the registers for extracting the control signals are individually provided, the hardware becomes large.

In order to solve the above problems, the present invention provides a signal processing apparatus that shares a selector for selecting data from a memory and a selector for performing 0 interpolation, and / or a lookup table and a register for extracting a control signal. The purpose is to provide.

[0010]

In order to solve the above-mentioned problems, the present invention provides a storage means, a first holding means for holding a plurality of data and outputting the data as one data to the storage means, and externally. Selection means for inputting data and outputting to the first holding means, second holding means for inputting and holding a plurality of data from the storage means, and one of the data of the second holding means Alternatively, the signal processing device is characterized by comprising a selection means for selecting data 0.

Further, according to the present invention, a storage means, a first holding means for holding a plurality of data and outputting it as one data to the storage means, and a data input from the outside, are stored in the first holding means. Control is provided with a selection means for outputting, a second holding means for inputting and holding a plurality of data from the storage means, and a selection means for selecting one of the data of the second holding means or data 0. Means, write address generating means for generating a write address, and read address generating means for generating a read address, and the write address is selected by the selecting means for selecting the address from the write address generating means and the address from the control means. Is output and is output to the storage means.

According to the present invention, the storage means, the first storage means for storing a plurality of data and outputting the data as one data to the storage means, and the data input from the outside, the first storage means. Selecting means for outputting to, and second holding means for inputting and holding a plurality of data from the storage means,
One of the data in the second holding means or data 0
A selection means for selecting, a control means, a write address generation means for generating a write address, and a read address generation means for generating a read address,
The write address is selected by the selection means for selecting the address from the write address generation means and the address from the control means, and the selected write address is output to the storage means. Further, the address from the read address generation means and the address from the control means are selected. The signal processing device is characterized in that the read address is selected by the selecting means for selecting and is output to the storage means.

[0013]

As described above, in the signal processing device according to the present invention, the selector for selecting the data from the memory and the selector for performing the 0 interpolation can be shared, and the circuit scale can be reduced. .

[0014]

1 is a block diagram of an embodiment of a signal processing apparatus according to the present invention.

In FIG. 1, 1 is a memory unit corresponding to a storage means, 2 is a write address generation unit for generating a write address to the memory unit 1, and 3 is a read address generation unit for generating a read address to the memory unit 1. 4 is an input for inputting a video signal, 5 is an output for outputting a video signal, 6 is a selector for selecting a setting signal from the CPU 12 and a video signal input from the input 4, 7 is an address and write address generation from the CPU 12. A selector for selecting an address from the unit 2, a selector 8 for selecting one of a signal from the input 4, an address from the read address generating unit 3, and an address from the CPU 12, 9 is data of the latch 11 and data 0 The selector 10 for selecting is a latch that holds the input signal and outputs it to the memory unit 1, and can hold three pixel signals. A latch 11 holds data from the memory unit 1 and can hold three pixels. 1
Reference numeral 2 is a CPU that sets a lookup table.

Next, the operations of the line memory, the look-up table and the register will be described. First, a case of operating as a line memory will be described.

In the write operation, the signal input from the input 4 is stored in the latch 10 by the selector 6. The selector 6 stores the data of 3 pixels in the latch 10 by sequentially selecting the storage portion of 3 pixels of the latch 10.
When 3 pixels are stored, the data of the latch 10 is stored in the memory unit 1. As a result, the memory section 1 may be operated at 1/3 the cycle of storing data. After storing, the write address generation unit 2 increments the write address. By such an operation, writing to the memory unit 1 is sequentially performed.

In the read operation, three data are read from the memory section 1 at a time, and the read data are stored in the latch 11. With respect to the stored data, one of three data is sequentially read by the selector 9 and output from the output 5 to the outside. As a result, the output data rate is three times the memory operation speed, and high-speed data output is possible even when the memory unit 1 operates at a slow speed. When performing 0 interpolation, by selecting 0 with this selector 9,
It is possible to perform 0 interpolation operation.

By thus sharing the selector with the 0-interpolator and the data selector, the 0-interpolation can be performed with a small increase in the amount of hardware.

Next, the case of operating as a lookup table will be described. For the setting of the look-up table, the address from the CPU 12 is selected by the selector 7 and input to the memory unit 1 as a write address. Also CPU
The data from 12 is selected by the selector 6, input to the memory unit 1 by the selector 7, and the data is written to the set address for setting. When referencing, select the data from input 4 by selector 8,
It is input to the memory unit 1 as a read address. As a result, the data written in the memory unit 1 is transferred to the latch 1
Read in 1. Next, the data read by the selector 9 is selected and the data is output from the output 5. This allows the hardware operating as a line memory to be used as a lookup table.

Next, the case of using as a register will be described. When operating as a line memory, pixel data is written in the memory unit 1. Selector 8
The address from the CPU 12 is input to the memory unit 1 and the read address is input to the memory unit 1.
By loading the data into 2, the pixel data can be
12 can be operated as a register for loading.

In the present embodiment, the line memory is shown, but any delay means having a memory unit such as a field memory or a pixel delay can be applied.

Further, the memory unit 1 is configured to read out three pixels at the same time, but it may be configured to read out any pixel such as one pixel simultaneously.

Although the data setting from the CPU 12 is set pixel by pixel via the selector 6, the data of 3 pixels can be directly set in the latch 10. Further, the reading may be performed by reading the data of 3 pixels directly from the latch 11 to the CPU 12.

[0025]

As described above, according to the present invention, the selector for operating at high speed with respect to the operation speed of the memory and the selector for 0 interpolation are shared, so that the increase in speed and the increase in 0 can be achieved with a small amount of hardware. The lookup table function and the register function can be implemented with a small increase in the hardware by sharing the lookup table and the register, and the effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a signal processing device according to the present invention.

[Explanation of symbols]

1 memory section 2 Write address generator 3 Read address generator 4 inputs 5 outputs 7-9 selector 10,11 Latch 12 CPU

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Claims (5)

(57) [Claims] 1. A storage means, a first holding means for holding a plurality of data and outputting it as one data to the storage means, and a selection for inputting data from the outside and outputting it to the first holding means. Means, second holding means for inputting and holding a plurality of data from the storage means, and one of the data of the second holding means or data 0
A signal processing device comprising: a selecting unit for selecting 2. Storage means, first holding means for holding a plurality of data and outputting to the storage means as one data, and selection for inputting data from the outside and outputting to the first holding means. Means, second holding means for inputting and holding a plurality of data from the storage means, and one of the data of the second holding means or data 0
Selecting means for selecting, a control means, a write address generating means for generating a write address, and a read address generating means for generating a read address, the address from the write address generating means and the control means The signal processing device is characterized in that the write address is selected by the selecting means for selecting the address and is output to the storage means. 3. Storage means, first holding means for holding a plurality of data and outputting to the storage means as one data, and selection for inputting data from the outside and outputting to the first holding means. Means, second holding means for inputting and holding a plurality of data from the storage means, and one of the data of the second holding means or data 0
Selecting means for selecting, a control means, a write address generating means for generating a write address, and a read address generating means for generating a read address, the address from the write address generating means and the control means The write address is selected by the selecting means for selecting the address and output to the storage means, and the read address is selected by the selecting means for selecting the address from the read address generating means and the address from the control means. A signal processing device which outputs to the storage means. 4. The selecting means sets data 0 for each cycle.
4. The signal processing device according to claim 1, wherein the data of the second holding unit is selected. 5. The signal processing apparatus according to claim 1, wherein the selecting means selects data 0 and data in the second holding means for each line.