JP3471966B2 - Method for manufacturing thin film semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film insulating gate type semiconductor device (particularly a thin film transistor or a TFT) on an insulating surface. The semiconductor device according to the present invention is used in an active matrix such as a liquid crystal display, a drive circuit such as an image sensor, an SOI integrated circuit, or a conventional semiconductor integrated circuit (microprocessor, microcontroller, microcomputer, semiconductor memory, or the like). It is a thing.

[0002]

2. Description of the Related Art In recent years, an insulating gate type semiconductor device (MI) has been formed on an insulating substrate, or even on a semiconductor substrate, on a surface (insulating surface) separated from the semiconductor substrate by a thick insulating film.
Researches for forming SFET) have been actively conducted. In particular, a semiconductor device having a thin semiconductor layer (active layer) is called a thin film transistor (TFT). In such a semiconductor device, it is difficult to obtain an element having good crystallinity such as a single crystal semiconductor, and a non-single crystal semiconductor having crystallinity but not single crystal is usually used. Therefore, the crystallinity of the semiconductor greatly affects the characteristics of the semiconductor device.

When silicon is used as a semiconductor,
As disclosed in JP-A-6-318701, when a metal element such as nickel, cobalt, iron, platinum, or palladium is used, amorphous silicon can be crystallized at a lower temperature and in a shorter time. Is. That is, the metal element functions as a catalyst metal element during crystallization. The characteristics of the semiconductor device using the crystalline silicon film obtained in this way were generally better than those without it. Also, good crystallization was possible even in a thin film having a thickness of less than 1000Å.

[0004] To obtain better crystallinity, Japanese Patent Laid-Open No. Hei 6 (1994)
As disclosed in JP-A-318701, it is also effective to irradiate a silicon film crystallized with a catalytic metal element as described above with intense light such as laser to perform optical annealing.

[0005]

However, the method using a catalytic metal element has one problem to be solved.
It is because the catalytic metal element is biased to a specific place,
This means that the variations in the characteristics of semiconductor devices will become severe. That is, most of the catalytic metal elements are present in the silicon film in the form of silicide, but in a large amount thereof, the semiconductor characteristics of silicon are significantly impaired.
In the case of FT, there is a problem that the drain current is large regardless of the gate bias. The present invention aims to solve this problem.

[0006]

The present invention aims to solve the above problems by polishing and flattening the surface of a silicon film crystallized by the above means by a chemical mechanical polishing method. Characterize.

That is, (1) a step of forming an amorphous silicon film on an insulating surface (2) a step of crystallizing the silicon film by thermal annealing using a catalytic metal element (3) Step (4) of subjecting the silicon film to optical annealing. By subjecting the silicon film to chemical mechanical polishing (CMP), the root mean square (R
MS) is 10% or less of the film thickness, or the difference between the heights of the convex portion and the concave portion is 25% or less of the film thickness, so that the portion where the catalytic metal element segregates in the silicon film is segregated. Can be selectively removed, so that the characteristics of the semiconductor device can be stabilized.

A semiconductor device can be manufactured by depositing an insulating film and a conductive film so as to cover the silicon film thus treated. After the step (4), a step of forming a thermal oxide film on the surface of the silicon film may be provided. The thermal oxidation in this case is 500 to 600 ° C.
Thermal oxidation at low temperature is also included, but as a result of this oxidation step, the catalytic metal element in the silicon film is changed to metal oxide,
It is effective because it can be fixed.

Further, in the present invention, the silicon film is formed by chemical vapor deposition (CVD) or physical vapor deposition (P).
It may be formed on an insulating base film formed by the VD) method. In addition, the underlying film is planarized by polishing by a chemical mechanical polishing method,
This is effective in the step of flattening the silicon film.

In the above step (4), the CMP method for a silicon film is described by Takahashi et al. (Appl. Phys. Lett. Vol. 64) .
(1994) pp2273), or Kao et al. (Int'l Display R
es.Conf. Oct.10-13, 1994, Monterey, Calif. pp294)
It has been reported by the above, and the method similar to that may be used.

[0011]

The method disclosed in JP-A-6-318701 for obtaining a crystalline silicon film by using both thermal annealing and optical annealing using a catalytic metal element has another problem. It is a problem of unevenness (ridge) on the surface of the silicon film caused by the optical annealing process. This is a problem even when the catalytic metal element is not used, but when the catalytic metal element is used, the crystallinity changes more greatly during the photo-annealing, so that the local volume change is significant, and The unevenness becomes large.

The unevenness is at least 100 Å, and typically, a difference of unevenness (difference in height between the convex portion and the concave portion) which is about the same as the film thickness is doubled. That is, if the film thickness is 500Å,
The unevenness difference was as high as 500 to 1000Å. Further, when the root mean square (RMS) was used as another method of displaying the unevenness, the value exceeded 20% of the film thickness.

Now, the inventors of the present invention are the result of the research. The catalytic metal element is selectively present at the grain boundaries of the silicon crystal, and
It was found that ridges were generated at the grain boundaries. This state is conceptually shown in FIG. 1A, in which the ridges 13 to 13 are formed on the crystalline silicon film 12 formed on the insulating surface 11.
There are fifteen. The concentration of the catalytic metal element is represented by the density of dots and is concentrated on the ridges 13 to 15 as shown in the figure. (Fig. 1 (A))

Therefore, since the portion where the ridge exists is a defective portion of the semiconductor device, if the ridge is removed,
At the same time, the catalytic metal element can be removed. In this case, since the concentration of the catalytic metal element is particularly high at the top of the ridge, the portion having a high concentration of the catalytic metal element can be selectively removed by removing the ridge. Although the concentration of the catalytic metal element is also high in the root portions 16 to 18 of the ridge, the concentration is not such that the semiconductor characteristics are lost, and there is almost no problem. (Fig. 1
(B))

Since the catalytic metal element in this part has a small absolute amount, the catalytic metal element in the part can be fixed as a metal oxide by a thermal oxidation treatment at an appropriate temperature. The oxide containing the catalytic metal element thus obtained can be removed by treating with hydrofluoric acid,
Therefore, the catalytic metal element can be removed.

As described above, in order to selectively remove the ridge, the silicon film may be planarized by the CMP method.
Of course, eliminating unevenness and planarizing the silicon film itself contributes to miniaturization and high reliability of the semiconductor device.
For example, as shown in FIG. 2, even when the insulating film 23 and the electrode 24 are formed so as to cover the silicon film 22 on the insulating surface 21, the existence of the ridge 25 has been a problem.

That is, the first problem is that the covering property of the insulating film 23 is deteriorated due to the existence of the ridge, and the insulating property of the portion is deteriorated. Further, as described above, since the ridge portion has a small radius of curvature and the catalytic metal element exists as a silicide and has an extremely high conductivity, when a voltage is applied between the electrode 24 and the silicon film 22. , The Fowler-Nordheim current 26 was likely to occur. (Fig. 2)

Further, since the ridge portion is conductive, charges may be trapped in the portion, which may deteriorate the semiconductor characteristics. Remove the ridge,
It has been found that flattening is effective in solving these problems. That is, an insulating film on a silicon film is deposited by a CVD method, particularly a thermal CVD method, and the thickness thereof is twice the thickness of the silicon film or less, more preferably 1
It has become possible to reduce it to less than double. As a result, the threshold voltage (V _th ) of the semiconductor device can be reduced and power consumption can be suppressed.

This makes it possible to reduce the design rule. That is, in order to reduce the design rule by half, it is necessary to reduce the thickness of the gate insulating film at the same time. However, since the gate insulating film can be thinned as described above, the design rule is reduced. To 0.2
It has become possible to set the thickness to 5 to 3 μm.

According to the research conducted by the present inventor, in order to sufficiently remove the catalytic metal element, the RMS of the surface irregularities is 10% or less of the film thickness, or the difference in height between the convex portion and the concave portion is 25% of the film thickness. % Or less. Further, in order to perform effective flattening, it is preferable that the base film is also sufficiently flat.

In addition to the present invention, it is reported that the characteristics of the semiconductor device can be improved by thinning the silicon film. For example, Hisao Hayashi et al., Jpn. J. Appl. Ph.
ys.vol. 23 (1984) In L819, the characteristics of the TFT were investigated by changing the thickness of the active layer of crystalline silicon from 100Å to 1000Å. When the active layer became thin, the field effect mobility was improved. It is reported that favorable characteristics such as reduction in threshold voltage and leak current were obtained.

This also applies to the crystalline silicon film using the catalytic metal element as the object of the present invention. Therefore, in the present invention, the characteristics of the semiconductor device can be improved not only by flattening by the CMP method but also by further polishing to thin the silicon film.

[0023]

【Example】

[Embodiment 1] This embodiment is shown in FIGS. First, the flattened and polished substrate 31 (Corning 7059, 100 mm
(× 100 mm) as a base oxide film on the silicon oxide film 32.
Was deposited to a thickness of 1000 to 5000Å, for example, 4000Å by a sputtering method. The silicon oxide film 32 is provided to prevent the diffusion of impurities from the glass substrate.

Then, the silicon oxide film was polished and flattened by the known CMP method. As the flatness,
The uneven RMS was set to 10 Å or less. Then, the amorphous silicon film 33 is 400 to 1500 by the plasma CVD method.
The film was formed at a thickness of, for example, 500 Å. After that, a layer 34 (nickel-containing layer) containing several to several tens of liters of nickel or a nickel compound was formed on the amorphous silicon film.

To form the nickel-containing layer 34, a method in which a solution containing nickel element is applied and then dried is used. A method in which nickel or a nickel compound is deposited by a sputtering method is used. It may be formed by any of the methods (vapor phase growth method) of decomposing and depositing by.

In order to apply the solution in the above method, for example, a spin coating method or a dipping method may be used. In this example, the nickel acetate film was formed by the spin coating method. The method will be described in detail below.

First, a silicon oxide film was formed to a thickness of 10 to 50 Å by oxidizing the silicon surface on the amorphous silicon film. To form a silicon oxide film, U in an oxygen atmosphere is used.
It may be performed by irradiation with V light, thermal oxidation, treatment with hydrogen peroxide, or the like. Here, an oxide film was formed to a thickness of 20 Å by irradiation with UV light in an oxygen atmosphere. This silicon oxide film spreads the nickel acetate solution over the entire surface of the amorphous silicon film in the subsequent step of applying the nickel acetate solution, that is, improves the surface characteristics of the silicon film,
This is to prevent the aqueous solution from being repelled.

Next, nickel was dissolved in the acetate solution to prepare a nickel acetate solution. At this time, the concentration of nickel was 10 ppm. Then, 2 ml of this nickel acetate solution was dropped onto the surface of the rotated substrate, and this state was maintained for 5 minutes to uniformly spread the nickel acetate solution on the substrate. After that, the rotation speed of the substrate was increased and spin drying (2000 rpm, 60 seconds) was performed.

According to the research conducted by the present inventor, if the concentration of nickel in the nickel acetate solution is 1 ppm or more, it becomes practical. This nickel acetate solution coating step
By carrying out a plurality of times, it was possible to form a nickel acetate layer having an average film thickness of 20Å on the surface of the amorphous silicon film after spin drying. Note that the above layers are not necessarily complete films. The same can be done by using other nickel compounds. Thus, the nickel acetate film (nickel-containing layer) 34 was formed. (Fig. 3 (A))

In this embodiment, the method of introducing nickel or a nickel compound onto the amorphous silicon film has been described, but under the amorphous silicon film (that is, between the base oxide film 32 and the silicon film 33). You may use the method of introduce | transducing nickel or a nickel compound into. in this case,
Nickel or a nickel compound may be introduced before the formation of the amorphous silicon film.

After forming the nickel-containing layer, in a heating furnace,
A heat treatment was performed in a nitrogen atmosphere at 550 ° C. for 4 hours to obtain a crystalline silicon film 35. By this thermal annealing, most of the amorphous silicon was crystallized, but some amorphous silicon portions were left in some places. Therefore, in order to improve crystallinity, KrF excimer laser light (wavelength 248 nm) was irradiated to crystallize these incompletely crystallized portions. Laser energy density is 200 ~
It was set to 350 mJ / cm ² . The energy density of the laser may be determined in consideration of the thickness of the silicon film, the degree of crystallization and the like. (Fig. 3 (B))

As a result of the above optical annealing, many ridges 36 to 38 were formed on the surface of the crystalline silicon film 35. In this embodiment, the height of the ridge is 200 to 1500Å
Met. (FIG. 3C) Next, the surface of the silicon film 35 was flattened by the CMP method. In this example, Int'l Display Res. Conf. Oct. 1
0-13, 1994, Monterey, Calif. Pp294) to obtain a flat surface 39 having RMS of 20 Å (that is, 4% of the film thickness) of irregularities. By removing the ridge, most of the nickel concentrated in the ridge could be removed. (Fig. 3 (D))

Although the silicon surface 39 is not a little damaged due to the above CMP method, it can be removed by thermal annealing or thermal oxidation. In this embodiment,
By performing thermal oxidation in an oxygen atmosphere at 1 atm and 550 ° C. for 30 minutes to 2 hours, a very thin silicon oxide film is formed on the surface, and by etching this with hydrofluoric acid, the above damage can be removed. (First thermal oxidation)

Next, the crystalline silicon film thus obtained was etched by a dry etching method to form island regions 43 (island silicon film). The island-shaped silicon film 43 constitutes the active layer of the TFT. Then, thermal annealing was performed for 30 minutes to 2 hours in an oxygen atmosphere at 1 atmosphere and 550 ° C. (Second thermal oxidation)

Thereafter, as the gate insulating film 107, the silicon oxide film 4 having a film thickness of 500 to 1000Å, for example, 750Å.
4 was deposited by the thermal CVD method. As the raw material gas, monosilane (SiH ₄ ) and oxygen (O ₂ ) were used. The substrate temperature during film formation was preferably 410 to 450 ° C. (Fig. 4
(A))

Further, by a low pressure CVD method, disilane (Si ₂ H ₆ ) is used as a raw material and the thickness is 3000 to 6000.
Å Polycrystalline silicon film was deposited. By adding 1 to 5% of phosphine (PH ₃ ) to disilane,
Phosphorus was added to the polycrystalline silicon film to improve the conductivity. Next, the polycrystalline silicon film is etched,
The gate electrode 45 was formed. (Fig. 4 (B))

After that, impurities (phosphorus in this embodiment) were implanted into the island-shaped silicon film 43 in a self-aligned manner with respect to the gate electrode 45 by an ion doping method. Phosphine (PH ₃ ) was used as the doping gas. The dose amount in this case is 1 × 10 ^{13 to} 5 × 10 ¹⁵ cm
^-2 , acceleration voltage is 10 ~ 90kV, for example, dose amount is 5
× 10 ¹⁴ atoms / cm ² , acceleration voltage was 80 kV. As a result, N-type impurity regions 46a (source) and 46b (drain) were formed. (Fig. 4 (C))

Further, a KrF excimer laser (wavelength 2
The doped impurity region 110 was activated by irradiation with 48 nm and a pulse width of 20 nsec. Laser energy density is 200-400 mJ / c
m ^2, and a preferably suitably 250~300mJ / cm ^2. This step may be performed by thermal annealing at 350 to 500 ° C. Further, thermal annealing may be performed after the activation by laser.

Next, plasma CV is used as an interlayer insulating film.
A silicon oxide film 47 having a thickness of 3000 Å was formed by the D method. Then, the interlayer insulating film 47 and the gate insulating film 44 were etched to form contact holes in the source / drain. Then, the titanium film 48 (thickness 1000
Å), an aluminum film 49 (thickness 5000 Å) was formed by a sputtering method, and this was etched to form a source electrode 50a and a drain electrode 50b, thereby completing a TFT. Furthermore, you may perform a hydrogenation process at 200-400 degreeC. (Fig. 4 (D))

Channel length produced by the above method /
When the characteristics of the TFT with a width of 3/3 μm were measured, TF was
Those that did not show T-motion and gate bias:
-10V, drain voltage: + 1V drain current (O
No FF current) was more than 1 nA out of 100.

However, in the case where the planarization by the CMP method of FIG. 3D was not performed, 38 out of 100 did not show the TFT operation, and out of the 62 which showed the TFT operation. , OFF current under the above conditions is 1
There were as many as 25 or more than nA. As a result of failure analysis,
The defective TFT operation and OFF current were mainly caused by gate leakage due to the thin gate insulating film of 750 Å. When the thickness of the gate insulating film was 1200Å, operation was confirmed in all TFTs.

Further, in the present example, all of the ones which did not undergo the first thermal oxidation showed the TFT operation, but the OFF currents of 1 nA or more were 3 out of 100. Similarly, in the present example, even if the second thermal oxidation was not performed, although all showed the TFT operation, the OFF current was 1 nA or more in 8 out of 100. Thus, it was confirmed that the first and second thermal oxidation steps in this example contribute to the reduction of the OFF current.

[Embodiment 2] This embodiment will be described with reference to FIG. A crystalline silicon film having a flat surface (thickness 500Å) was formed on the glass substrate 51 and the underlying silicon oxide film 52 by the same method as described in Example 1 or FIG. However, in this example, as the catalytic metal element,
Palladium was used. After that, the silicon film is etched in the same manner as in Example 1 to form the active layer 53N of the TFT.
(For N channel type TFT) and 53P (P channel type TF)
(For T). After that, a silicon oxide film 5 having a film thickness of 500 to 1000 Å, for example, 500 Å is formed as a gate insulating film.
4 was formed by the plasma CVD method.

Thereafter, an aluminum (containing 1 wt% Si or 0.1-0.3 wt% Sc) film having a thickness of 1000 Å to 3 μm, for example 5000 Å, is formed by a sputtering method and is patterned. hand,
Gate electrodes 55N and 55P were formed. (Figure 5 (A))

Next, the substrate was immersed in an ethylene glycol solution of tartaric acid having a pH of about 7 and 1 to 3%, and anodization was performed using platinum as a cathode and aluminum gate electrodes 55N and 55P as an anode. The anodic oxidation is initially 120 at a constant current.
The voltage was increased to V, and the state was maintained for 1 hour to finish. Thus, the anodic oxide coatings 56N and 56P having a thickness of 1500 to 2500Å, for example 2000Å, were formed. (Fig. 5 (B))

After that, N-type and P-type impurities (in this embodiment, phosphorus and boron, respectively) are implanted into the island-shaped silicon film 206 by ion doping in a self-aligned manner with respect to the gate electrode and the anodic oxide. did. Phosphine (PH ₃ ) and diborane (B) are used as doping gases.
₂ H ₆ ) was used. The method of doping is known CMOS
According to technology. The dose amount of this embodiment is 1 × 10 ^{13 to} 5 × 10 ¹⁵ cm ^{−2 for} both phosphorus and boron, and the acceleration voltage is 10 to 9
0 kV, for example, phosphorus has a dose amount of 5 × 10 ¹⁴ cm ^-2 , accelerating voltage is 80 kV, and boron has a dose amount of 1 × 10 ¹⁵ c.
m ⁻² and the acceleration voltage was 65 kV.

In this embodiment, the gate electrode has an offset structure separated from the source and drain by the thickness of the anodic oxide. For details of the TFT having such a structure,
It is disclosed in JP-A-5-267667. Further, as in Example 1, using a KrF excimer laser,
Activation of the doped impurities was performed. As a result, N-type impurity regions 57N (source / drain) and P-type impurity regions 57P (source / drain) are formed.
(Fig. 5 (C))

After that, a silicon oxide film 58 having a thickness of 3000 Å was formed as an interlayer insulating film by a low pressure CVD method.
Then, the interlayer insulating film 58 and the gate insulating film 54 were etched to form contact holes in the source / drain. Then, a 5000 Å-thick aluminum film was formed by a sputtering method, and this was etched to form source / drain electrodes / wirings 59a to 59c. Furthermore, you may perform a hydrogenation process at 200-400 degreeC. As described above, the CMOS circuit can be configured by the TFT. (Figure 5 (D))

The TFT thus obtained has a thinner gate insulating film as compared with the conventional TFT (in the conventional case, the gate insulating film having a thickness of 1000 Å or less could not prevent the gate leak). The characteristics such as the effect mobility, the threshold voltage, and the leakage current were significantly better than those of the conventional ones.

[0050]

According to the present invention, a TFT having excellent characteristics can be obtained. In this embodiment, the structure of the TFT has a relatively simple structure. However, for example, a low concentration impurity region as shown in Japanese Patent Publication No. 3-38755 may be provided in the source and the drain. Further, in the second embodiment, an example in which the gate electrode is anodized is shown. However, as disclosed in JP-A-6-338612, a TFT having a complicated structure can be formed by combining different types of anodic oxides. It is also possible to produce. As described above, the present invention is industrially useful and sufficient for patenting.

[Brief description of drawings]

FIG. 1 shows a method for treating a silicon film according to the present invention.

FIG. 2 shows an example of characteristic deterioration due to the presence of a ridge.

FIG. 3 shows a method for producing a silicon film according to the present invention.
(Example 1)

FIG. 4 shows a method for manufacturing a TFT element according to the present invention.
(Example 1)

FIG. 5 shows a method for manufacturing a TFT circuit according to the present invention.
(Example 2)

[Explanation of symbols]

11 board 12 Crystalline silicon film 13-15 Ridge 16-18 Area where the catalytic metal element concentration is high 21 board 22 crystalline silicon film 23 Insulating film 24 electrodes 25 ridge 26 Fowler-Nordheim Current 27 power supply 31 substrate 32 Base film 33 Amorphous silicon film 34 Nickel-containing layer (nickel acetate layer) 35 crystalline silicon film 36-38 Ridge 39 Flattened silicon surface 41 substrate 42 Base film 43 Island Silicon Region 44 Gate insulation film 45 Gate electrode (polycrystalline silicon) 46 N-type impurity region 47 Interlayer insulation (silicon oxide) 48 Titanium film 49 Aluminum film 50 Source / drain electrode / wiring 51 substrate 52 Base film 53N, 53P island silicon region 54 Gate insulation film 55N, 55P Gate electrode (polycrystalline silicon) 56N, 56P anodic oxide 57N, 57P Impurity region 58 Interlayer insulator (silicon oxide) 59 Source / drain electrodes / wiring

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Claims (6)

(57) [Claims] 1. An insulating underlayer film formed by a CVD method or a PVD method is subjected to chemical mechanical polishing to planarize the surface of the underlayer film, and an amorphous silicon film is formed on the underlayer film. The amorphous silicon film is crystallized by performing thermal annealing using a catalytic metal element to form a crystalline silicon film, the crystalline silicon film is subjected to optical annealing, and the crystalline silicon film is chemically and mechanically By polishing, the root mean square (RMS) of the irregularities on the surface of the crystalline silicon film is 10% or less of the film thickness, or the height difference between the convex portion and the concave portion is 25% or less of the film thickness. And forming an insulating film and a conductive film so as to cover the crystalline silicon film. 2. A silicon oxide film is formed on a substrate, the silicon oxide film is subjected to chemical mechanical polishing to planarize the surface of the silicon oxide film, and an amorphous silicon film is formed on the silicon oxide film. Then, the amorphous silicon film is crystallized by performing thermal annealing using a catalytic metal element to obtain a crystalline silicon film, and the crystalline silicon film is subjected to optical annealing to chemically change the crystalline silicon film. to facilities Succoth mechanical polishing
The root mean square of the irregularities on the surface of the crystalline silicon film.
Root (RMS) is less than 10% of the film thickness, or convex and concave
A method for manufacturing a thin film semiconductor device, characterized in that the difference in height is 25% or less of the film thickness, and an insulating film and a conductive film are formed so as to cover the crystalline silicon film. 3. A silicon oxide film is formed on a substrate, the silicon oxide film is subjected to chemical mechanical polishing to flatten the surface of the silicon oxide film, and an amorphous silicon film is formed on the silicon oxide film. Then, the amorphous silicon film is crystallized by performing thermal annealing using a catalytic metal element to obtain a crystalline silicon film, and the crystalline silicon film is subjected to optical annealing to chemically change the crystalline silicon film. to facilities Succoth mechanical polishing
The root mean square of the irregularities on the surface of the crystalline silicon film.
Root (RMS) is less than 10% of the film thickness, or convex and concave
So that the difference in height between them is 25% or less of the film thickness, the crystalline silicon film is subjected to a first thermal oxidation, and the silicon oxide film formed by the first thermal oxidation is etched.
After quenching, the crystalline silicon film and an island-shaped silicon film is formed by etching, subjected to a second thermal oxidation on the island silicon film, a gate insulating film is formed on the island-shaped silicon film, wherein A method for manufacturing a thin film semiconductor device, comprising forming a gate electrode on a gate insulating film. 4. The method according to any one of claims 1 to 3 ,
The catalytic metal element is nickel, cobalt, iron, platinum,
A method for manufacturing a thin film semiconductor device, which is one of palladium. 5. The method according to any one of claims 1 to 4,
The optical annealing is performed on the crystalline silicon film by KrF exci
Thin film characterized by being irradiated with Maras laser light
Manufacturing method of semiconductor device. 6. The method according to any one of claims 1 to 5,
The method for manufacturing a thin film semiconductor device, wherein the difference in height between the convex portion and the concave portion of the irregularities generated on the surface of the crystalline silicon film by the optical annealing is in the range from the same value as the film thickness up to twice.