JP3469753B2 - Return address read control method of processor and processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention supports multiple calls of a program module by an interrupt signal or a subroutine call, and moreover, stores a return address from a called program module to a calling program module. The present invention relates to a processor using a storage device having a structure and a return address read control method thereof.

[0002]

2. Description of the Related Art There is a processor that supports multiple calls of a program module by an interrupt signal or a subroutine call and stores a return address from the called program module to the calling program module in a storage device having a stack structure. The stack is a data structure that outputs the last input data first, and is also called LIFO (Last In-First Out).
The storage device having a stack structure is mainly used for the purpose of temporarily saving data.

A register or a memory is used as the storage device, and both have the characteristics described below. The register can read / write faster than the memory, but since the unit price per storage capacity is higher than the memory, it becomes more expensive than the memory when the same storage capacity is implemented. On the other hand, a memory has a lower unit price per storage capacity than a register, but its reading / writing speed is inferior to that of a register. Therefore, whether to use a register or a memory for the storage device is determined by a trade-off between the required processing speed and the price set for the processor. Generally, a small amount of registers and a memory (area dedicated to the stack provided on the data memory) are used together.

Each time a processor that uses a register for one level and a stack memory dedicated for stacking receives a multiple call of a program module, the return address to the program module in which the call occurs is overwritten in the register and the stack is also stacked. Push to memory. That is, the return address of the higher-level program module that called the program module currently being executed is written in the register.

FIG. 3 is an explanatory diagram for explaining the stored contents of the registers when the above-mentioned processor is executed. In the figure,
In the main routine, the push instruction is executed when the call of the subroutine A occurs due to the interrupt signal or the subroutine call. Then, the return address RM to the main routine is written in both the register and the stack memory. Then, the execution of the subroutine A is started.

In Subroutine A, Subroutine B
When a call is issued, a push instruction is executed and its return address RA is overwritten in the register. The return address RA is pushed to the stack memory.
Then, the execution of the subroutine B is performed. Subroutine B
When a call to subroutine C occurs,
The push instruction is executed, and the return address RB is overwritten in the register. The return address RB is pushed to the stack memory. Then, the execution of the subroutine C is performed.

When the return instruction is accepted, the subroutine C is returned to the higher-level subroutine B based on the return address RB read from the register. Once returning to the higher-level program module (subroutine B), from there, the higher-level program module (subroutine A)
When returning to, since the return address stored in the register is invalid, the return address is popped from the stack memory and used. The same applies to the return from the subroutine A to the main routine.

[0008]

The return instruction to be used differs depending on whether the return address is read from the register to return and the return address is popped from the stack memory to return. For example, TMS320C54x, a DSP (Digital Signal Processor) manufactured by Texas Instruments
, The former command is the RETF command and the latter command is RET
Accepted by command. The RETF instruction can return to the higher-level program module with a smaller number of operation clocks than the RET instruction.

In other words, in the program module (subroutine C described above) in which multiple calls due to interrupt signals or subroutine calls do not occur, the return address stored in the register is valid, so the RETF instruction for reading the return address from the register is issued. By using it, the processing speed can be increased. In the other program modules (subroutines A and B), since the return address stored in the register is invalid, the RET instruction for reading the return address stored in the stack memory is used.

That is, in order to properly use the return instruction, the programmer who creates the program module of the processor needs to know the status of multiple calls at the time of execution of the program module when creating the program module.
However, although it is clear to the programmer whether or not there is a subroutine call in the program module creation stage, it is impossible to grasp the state of the interrupt signal at the time of execution.

Therefore, in the program module in which an interrupt may occur, it is impossible to determine whether the return address stored in the register is valid at the time of execution. So, in such a program module return instruction,
I was using the RET instruction. In other words, in a program module that can generate an interrupt, even if the RETF instruction can be used for the return instruction without the interrupt occurring during its execution, the higher level Since it returns to the program module, there was room for speeding up the processing.

The present invention has been made in view of the above circumstances, and in a processor configured to overwrite a return address in a predetermined register each time a multiple call occurs, the return stored in the register is returned. An object of the present invention is to provide a return address read control method capable of reading the return address from the register and returning when it is determined that the address is valid, and if it is determined to be valid, and a processor used for the execution. To do.

[0013]

A return address read control method for a processor according to a first aspect of the present invention, a program of a higher level is executed by executing a push instruction when multiple calls for calling a program module occur during execution of the program module. When the return address to the module is written to the stack memory and the register, and the return from the called program module occurs,
In the return address read control method of the processor which reads the return address from the stack memory or the register by executing the pop instruction and returns to the higher-level program module, the status of the register is changed each time the push instruction is executed. A predetermined value is set in the status register that indicates that the status register is reset each time a pop instruction is executed, and when returning to the higher-level program module, it is determined whether or not the predetermined value is set in the status register. However, when it is determined that it is set, the return address is read from the register and the process is returned to the higher-level program module.

The processor according to the second invention writes the return address to the higher-level program module in the stack memory and the register by executing the push instruction when a multiple call for calling the program module occurs during the execution of the program module. In addition, when a return from the called program module occurs, a pop instruction is executed to read the return address from the stack memory or register, and a push instruction is issued to the processor for returning to the higher level program module. The status register is set to set a predetermined value each time it is executed and reset each time the pop instruction is executed, and means for determining whether the predetermined value is set in the status register. To Ri when a predetermined value is determined to have been set, reads the return address from the register, characterized in that no order to return to the higher-level program modules.

In the processor used for implementing the return address read control method of the processor, a status register indicating whether or not the return address written in the register by multiple call is read is provided, and the return address is pushed. Alternatively, each time a pop is performed, the status register is set / reset. Then, it is determined whether or not the status of the status register is set, and if it is set, it is determined that the return address stored in the register is valid, and the return address stored in the register is read out to restore. By doing so, the processing speed is increased.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a principal block diagram showing the configuration of a processor of the present invention. In the figure, 1 is an address bus for transmitting an address signal. The address bus 1 is connected to the stack register 2 so as to provide the address signal transmitted on the address bus 1 to the stack register 2. A read / write control terminal of the stack register 2 is supplied with a read / write signal corresponding to a pop command / push command, and when the write signal is supplied, the address signal transmitted on the address bus 1 is multiplexed. It is stored as a return address for one level. Further, the stack register 2 is adapted to provide the applied address signal to one input terminal of the stack memory 3 and the multiplexer 4.

The stack memory 3 is provided with a stack pointer 5 and stores the address signal given through the stack register 2 at the address indicated by the stack pointer 5. The stack pointer 5 gives the address stored therein to one of the operation data input terminals of the operation unit 6. In addition, 1 is input to the other operation data input terminal of the operation unit 6.
And a read / write signal is applied to the control input terminal for selecting addition / subtraction.

When the arithmetic unit 6 receives the push command of the address signal, the arithmetic unit 6 adds 1 to the address value stored in the stack pointer 5. When the pop instruction of the address signal is accepted, 1 is subtracted from the address value stored in the stack pointer 5. The status register 7 receives the read / write signal, resets when a read signal is given, that is, when a pop command is received, and when a write signal is given, that is, when a push command is received, a predetermined value (for example, I'm trying to set 1). The value set in the status register 7 is given to the control terminal of the multiplexer 4.

To the other input terminal of the multiplexer 4,
The address value read from the stack memory 3 is given, and when a predetermined value is given to the control terminal, the address value given from the stack register 2 is given to the address bus 1. When a value other than the predetermined value is given to the control terminal, the address value given from the stack memory 3 is given to the address bus 1.

FIG. 2 is a flow chart showing the processing procedure of the processor of the present invention. When the pop instruction is accepted, it is determined whether or not the value of the status register 1 is the predetermined value 1 (S1), and when it is determined that it is not 1, the address value is read from the stack memory 3 (S2). When it is determined to be 1, the address value is read from the stack register 2
(S3). Then reset status register 1 (S
4) Write the read address value to the program counter (PC) (S5).

[0021]

According to the return address read control method of the processor of the first aspect of the invention and the processor of the second aspect of the invention as described above, a status register is provided, and each time the return address is pushed or popped, the status register is set / set. In order to determine whether the return address stored in the register is valid by resetting, if the return address stored in the register is valid in the program module that may generate an interrupt, return the return address. By reading from the register, the processing speed can be increased. Moreover, since only one return instruction needs to be specified when creating a program, the programmer can be freed from the proper use of the return instruction depending on the situation.

[Brief description of drawings]

FIG. 1 is a principal block diagram showing a configuration of a processor of the present invention.

FIG. 2 is a flowchart showing a processing procedure of a processor of the present invention.

FIG. 3 is an explanatory diagram illustrating stored contents of a register when the processor is executed.

[Explanation of symbols]

1 address bus 2 stack registers 3 stack memory 4 multiplexer 6 calculator 5 Stack pointer 7 Status register

Claims (2)

(57) [Claims] 1. When a multiple call for calling a program module occurs during execution of the program module, a push instruction is executed to write a return address to a higher level program module into a stack memory and a register, and the called program. When a return from the module occurs, a pop instruction is executed to read the return address from the stack memory or register, and in the return address read control method of the processor for returning to the higher-level program module, a push instruction is issued. Each time it is executed, a predetermined value is set in the status register indicating the status of the register, and each time the pop instruction is executed, the status register is reset, and a return to the higher level program module At this time, it is determined whether or not a predetermined value is set in the status register, and when it is determined that the predetermined value is set, the return address is read from the register and the upper level program module is restored. And return address read control method of the processor. 2. When a multiple call for calling a program module occurs during execution of the program module, a push instruction is executed to write a return address to a higher level program module in a stack memory and a register, and the called program. When a return from the module occurs, the return address is read from the stack memory or register by executing the pop instruction, and the processor which is designed to return to the higher-level program module returns a predetermined value each time the push instruction is executed. And a means for determining whether or not a predetermined value is set in the status register, and the predetermined value is set by the means. The When it is determined that reads return address from the register, the processor being characterized in that no order to return to the higher-level program modules.