JP3464271B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a nonvolatile semiconductor memory device such as an EEPROM.

[0002]

2. Description of the Related Art In the usage of mounting and using a plurality of memory ICs, even if each memory IC can operate only one function of erasing, writing and reading, a plurality of functions can operate simultaneously in the entire system. is there. The reason for operating at the same time is that the erase and write operations are 5 digits compared to the read operation.
This is because it is two digits slower. By operating them at the same time, it is possible to treat them as if they were operating faster. However, as the memory IC has a larger capacity, the mounted memory IC
The number has decreased and it has become difficult to use the above.

The structure of a conventional nonvolatile semiconductor memory device will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of a conventional nonvolatile semiconductor memory device.

In FIG. 3, 1 is an IC (nonvolatile semiconductor memory device), 2 is a control signal input from the outside, 3 is the same data, 4 is the same address, and 5 is the same power supply. Reference numeral 6 is an instruction analysis and status data generation unit that controls the entire IC. Reference numeral 7 is an erase control unit, and 8 is a write control unit. Reference numeral 7a is a status signal for notifying the instruction analysis and status data generation unit 6 that the erase control unit 7 is operating, and 8a is the write control unit 8
Is a status signal that informs the instruction analysis and status data generation unit 6 that is operating.

Further, in FIG. 3, 9 (9a to 9h) is a bus for carrying address signals, data signals, and control signals from the instruction analysis and status data generator 6, and 9i is a bus 9.
Is connected to the erase control unit 7, and 9j is a bus connecting the bus 9 and the write control unit 8. Furthermore, 10a to 10h
Is a memory block, and the inside is composed of a row decoder, a column decoder, a sense amplifier and a memory cell array.

Next, the operation of the conventional nonvolatile semiconductor memory device will be described. First, the read operation will be described.

When a read signal composed of the control signal 2 and the address 4 is externally given to the instruction analysis and status data generator 6, the memory blocks 10a to 10h are moved through the bus 9 (9a to 9h). Then, the data from the memory blocks 10a to 10h is transferred to the bus 9 (9a to 9).
It is received by the instruction analysis and status data generation unit 6 through h). The instruction analysis and status data generation unit 6 sends the data 3 to the outside and the reading is completed. At the time of reading, since none of the memory blocks 10a to 10h are operating, it is not necessary to confirm whether they are operating.

Next, the write operation will be described.

When the write signal and the write data including the control signal 2, the data 3 and the address 4 are externally applied to the instruction analysis and status data generation unit 6, the instruction analysis and status data generation unit 6 causes the write control unit through the bus 9j. 8 operation signal, status signal 8
The instruction analysis and status data generation unit 6 stops its operation until a is turned on once and turned off again.

The write control unit 8 turns on the status signal 8a to notify the instruction analyzing and status data generating unit 6 that it is in operation, and the bus 9 (9a to 9h, 9j).
Through the memory block 10a-10h,
Put the memory block in the write state. In this state, the memory cells in the memory block can be continuously supplied with voltage. The write control unit 8 turns off this state and performs a verify operation after a certain period of time. If yes (OK), the writing is completed, and the status signal 8a is turned off to complete. If it is not possible (NG), the writing is performed again and the verification is performed. This operation is performed a prescribed number of times, and when the operation is not possible (NG), the instruction analysis and status data generation unit 6 returns the write error status to the outside.

Next, the erase operation will be described.

The contents are basically the same as the write operation. That is, control signal 2, data 3 and address 4
When an erase signal and erase data consisting of are externally applied to the instruction analysis and status data generation unit 6, the instruction analysis and status data generation unit 6 sends an operation signal to the erase control unit 7 through the bus 9i, and the status signal 7a is once transmitted. The instruction analysis and status data generation unit 6 stops its operation until it is turned on and turned off again.

The erase control section 7 turns on the status signal 7a to inform the instruction analyzing and status data generating section 6 that the operation is in progress, and through the bus 9 (9a to 9h, 9i), the memory blocks 10a to 10h. To the memory block to erase the memory block. In this state, the memory cells in the memory block can be continuously supplied with voltage. The erase controller 7 turns off this state and performs a verify operation after a certain period of time. If OK (OK), the erasing is completed and the status signal 7a is turned off to complete. If it is impossible (NG), the erasure is performed again and the verification is performed. This operation is performed a prescribed number of times, and when the operation is not possible (NG), the instruction analysis and status data generation unit 6 returns the erase error status to the outside.

Since the erase, write, and read operations are performed in this manner, only one of these three functions can operate. However, since there is no extra circuit, the chip area is reduced. That is, this is suitable for a small capacity memory IC.

[0015]

In the conventional non-volatile semiconductor memory device as described above, only one of the erase, write and read operations can be performed, and it takes a long time to perform a test for discriminating the non-defective product / defective product. There was a problem that it required.

The present invention has been made in order to solve the above-mentioned problems, and an object thereof is to obtain a non-volatile semiconductor memory device which can shorten the test time and speed up the whole system. .

[0017]

SUMMARY OF THE INVENTION The non-volatile semiconductor memory device according to claim 1 of the invention, there is provided a nonvolatile semiconductor memory device capable of electrically batch erasing electrical writing divided into a plurality of memory blocks, the entire IC Solution to control the
Analysis and status data generator and memory blocks
Write controller that controls the writing of the
Erase control unit for controlling the erase of the memory, and the instruction analysis and
The status data generator, the write controller, the eraser
Control unit, and a bus connecting each memory block,
Address and data are inserted before each memory block.
And a latch circuit for temporarily storing a control signal,
The command analysis and status data generation unit uses a control signal,
And a read signal consisting of
Then, if the corresponding first memory block is inactive, the previous
The signal is sent via the latch circuit and the bus to
External data from the memory cell in the first memory block
Read out, consisting of control signal, data, and address
Write signal and write data are given externally
Then, if the corresponding second memory block is inactive, write
Sending the operation start signal of cutting, control signal, data, and
Erase signal consisting of address and erase data are external
If given, the corresponding third memory block is inactive
If so, an erasing operation start signal is sent and the write control unit
After receiving the write operation start signal,
When available, via the latch circuit and the bus
To send a signal to the memory cell in the second memory block.
Data is written to the erase
After receiving the operation start signal, when the bus is available,
The signal is sent via the latch circuit and the bus to
Erase the data of the memory cell in the third memory block
During the reading of the first memory block, and
While writing to the second memory block, the third memo
The reblock can be erased at the same time .

A nonvolatile semiconductor memory device according to a second aspect of the present invention is an electrical package that is divided into a plurality of memory blocks.
For erasable electrically writable non-volatile semiconductor memory device
In order to control the entire IC, instruction analysis and status
Data generation unit, instruction analysis and status data generation
The bus that connects the memory block and each memory block, and each memory
Write controller that controls writing to memory blocks
And the write controller and each memory block are connected
Control write bus and erase of each memory block
Erase control unit, the erase control unit, and each memory block
Bus to connect the memory block and the front stage of each memory block
Inserted into the bus, the write bus, and the
Select one of the signals from the erase bus to select the memory block
Selector circuit for sending to the
The status data generator is composed of control signals and addresses.
When an external read signal is applied, the corresponding first
If the memory block is not operating, the selector circuit and
A signal is sent via the bus to the first memory block.
Data is read out from the memory cell under control and controlled.
Write signal consisting of signal, data, and address, and
And the write data is given from the outside, the corresponding second
If the memory block is not operating, the write controller
Send a write operation start signal to the control signal, data,
And erase signal consisting of address and erase data are external
Given, the corresponding third memory block is inactive.
If the operation is in progress, send an erase operation start signal to the erase controller.
The write control unit sends the write operation start signal.
Signal after receiving the signal, the selector circuit and the write bus
Via a signal in the second memory block
Writing data to a memory cell, the erase control unit
After receiving the erase start operation signal, the selector circuit and
A signal is sent via the erasing bus to the third memo.
The data of the memory cell in the reblock is erased and the first
Reading the memory block of the second memory and the second memory
During the writing of the block, the third memory block
It can be erased at the same time .

[0019]

[0020]

In the non-volatile semiconductor memory device according to the first aspect of the present invention, in the non-volatile semiconductor memory device which is divided into a plurality of memory blocks and is capable of electrical batch erasing, among the erasing, writing and reading, Since two or more functions are simultaneously executed in different memory blocks, the manufacturing side can reduce the test time. Also, on the user side, even if the number of mounted chips is small,
It is possible to easily create a system that can simultaneously operate erase and read, and since it can operate simultaneously, the speed (throughput) of the entire system improves.

[0021]

In the non-volatile semiconductor memory device according to the second aspect of the present invention, in reading, random reading is possible in all memory blocks except during writing and erasing, and the principle of reading is fault. Since it does not occur, the peripheral circuits are simple.

[0023]

【Example】

Example 1. The configuration of an embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. Only the points different from the conventional example will be described below. In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 1, 7b is a request signal sent to the instruction analysis and status data generation unit 6 before the erase control unit 7 uses the bus 9 (9a to 9h, 9i), and 7c is an instruction analysis and status data generation unit 6. Request signal 7
It is an acknowledge signal that receives b and informs the erase control unit 7 that the bus 9 (9a to 9h, 9i) is usable. Also, 8b
Is a request signal sent to the instruction analysis and status data generation unit 6 before the write control unit 8 uses the bus 9 (9a to 9h, 9j), and 8c is the bus signal which the instruction analysis and status data generation unit 6 receives the request signal 8b. (9a-9
h, 9j) is an acknowledge signal that informs the write control unit 8 that it is available.

Further, in FIG. 1, 11a to 11h are latch circuits, which temporarily store address, data and control signals from the buses 9a to 9h, and memory blocks 10a to 10h.
The data that has been sent to 10h and latched once is not changed unless it is changed by control from the instruction analysis and status data generation unit 6. 12a to 12h are latch circuits 11a to 11
It is a bus that connects h with the memory blocks 10a to 10h.

Next, the operation of the first embodiment will be described. First, the read operation will be described.

When a read signal consisting of the control signal 2 and the address 4 is externally given to the instruction analysis and status data generation unit 6, does the instruction analysis and status data generation unit 6 correspond to a memory block during an erase operation or a write operation? Check. If it is in operation, an error status is returned, and if it is not in operation, signals are sequentially sent to the bus 9, the latch circuit 11, the bus 12, and the memory block 10 to read data from the memory cells in the memory block.

Then, the memory block 10, the bus 12,
Data is sequentially sent to the latch circuit 11, the bus 9, the instruction analysis and status data generation unit 6, and the read data is sent to the outside to complete the reading. It should be noted that the latch circuits 11a to 11h are used to confirm whether the memory block is in operation.
When a signal is sent to the instruction analysis and status data generation unit 6, a busy signal indicating that it is in operation is returned to the instruction analysis and status data generation unit 6.

Next, the write operation will be described.

When a write signal including the control signal 2, data 3 and address 4 and write data are externally applied to the instruction analysis and status data generation unit 6, the instruction analysis and status data generation unit 6 erases the memory block in which it operates. After confirming that it is not in the middle (in operation), the instruction analysis and status data generator 6 sends an operation start signal to the write controller 8 through the bus 9j.

The write controller 8 requests the request signal 8b.
To the instruction analysis and status data generation unit 6 by the bus 9
When the application for use is issued and the use permission is returned as the acknowledge signal 8c, the bus 9, the latch circuit 11, and the bus 1
2. Signals are sequentially transmitted to the memory block 10 to start the write operation.

For writing, it is necessary to continuously apply a voltage to the memory cell for a certain period of time, so that the memory circuit 10 is held by the operation of the latch circuit 11 and the bus 9
Is suspended, the request signal 8b is turned off, and the instruction analysis and status data generation unit 6 is notified of the passing of the bus 9.

The write controller 8 waits for a time by an internal timer, then turns on the request signal 8b again and waits for the acknowledge signal 8c to return. When the use permission of the bus 9 is returned by the acknowledge signal 8c, the signal is sequentially transmitted to the bus 9, the latch circuit 11, the bus 12, and the memory block 10 to stop the write in order to cause the memory cell to perform the write verify operation. Then, the write verify operation starts. When the verification is possible (OK), the write completion is transmitted to the instruction analysis and status data generation unit 6 by the status signal 8a, and the write control unit 8 stops the operation.
Writing is completed. If verification is not possible (NG),
The memory cell is set to the write state again, and the write verify is performed. This operation is performed a prescribed number of times, and when the operation is not possible (NG), the instruction analysis and status data generation unit 6 returns the write error status to the outside.

Next, the erase operation will be described.

Basically, the content is the same as that of the write operation, and only the voltage applied to the memory cell and its time are different (currently mass-produced products are three digits longer). That is, when the erase signal including the control signal 2, the data 3, and the address 4 and the erase data are externally applied to the instruction analysis and status data generation unit 6, the instruction analysis and status data generation unit 6 is writing to the operating memory block. (in action)
After confirming that it is not, the instruction analysis and status data generator 6 sends an operation start signal to the erase controller 7 through the bus 9i.

The erase control unit 7 issues a request for use of the bus 9 to the instruction analysis and status data generation unit 6 by the request signal 7b, and when the use permission is returned as the acknowledge signal 7c, the bus 9, the latch circuit 11, the bus 12, the signal is transmitted to the memory block 10 in order, and the erase operation is started.

Since it is necessary to continuously apply the voltage to the memory cell for a certain period of time for erasing, the memory circuit 10 is held by the action of the latch circuit 11, the use of the bus 9 is temporarily stopped, and the request signal 7b is turned off. Then, the instruction analysis and status data generation unit 6 is notified of the passing of the bus 9.

The erasing controller 7 waits for a time by an internal timer, and then turns on the request signal 7b again,
Wait for the acknowledge signal 7c to return. When the use permission of the bus 9 is returned by the acknowledge signal 7c, the signal is sequentially transmitted to the bus 9, the latch circuit 11, the bus 12, and the memory block 10 in order to cause the memory cell to perform the erase verify operation, and the erase is stopped. Then, the erase verify operation starts. If the verification is possible (OK), the completion of erase is transmitted to the instruction analysis and status data generation unit 6 by the status signal 7a, the erase control unit 7 stops the operation, and the erase is completed. If the verification is not possible (NG), the memory cell is erased again and erase verification is performed. This operation is performed a specified number of times and is not possible (NG)
In the case of, the instruction analysis and status data generator 6 returns the erase error status to the outside.

Since the erase, write, and read operations are performed in this manner, for example, the memory block 10a can be erased, the memory block 10b can be written, and the memory block 10c can be read. Of course, when continuously reading, the request signal 7b,
Since the interrupt of the acknowledge signal 7c is sometimes intervened, the access time is partially extended. Generally, this is because there is a wait for memory access, a long busy period, and a slow response to acknowledge, so there is no problem in system operation.

The first embodiment has the following effects. First, on the manufacturing side, in a test process for determining whether a memory IC is a good product or a defective product, block writing and block erasing that require a long time for writing and erasing are performed at the same time, and other written and erased blocks are executed. The test time can be shortened by testing. Secondly, on the user side, when a large-capacity memory IC is used, even if the number of mounted chips is small, it is possible to easily create a system capable of simultaneous write, erase, and read operations. Also, if simultaneous operation is possible, the speed (throughput) of the entire system will improve.

Example 2. The configuration of another embodiment of the present invention will be described below with reference to FIG. FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention. Only the points different from the conventional example will be described below. In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 2, reference numeral 14 denotes address data sent from the erase control unit 7 to the memory blocks 10a to 10h.
An erasing bus for transmitting a control signal, 15 is a write control unit 8
Is a write bus for transmitting address, data and control signals from the memory blocks 10a to 10h. Also,
13a to 13h are erase bus 14 and write bus 15
And a selector circuit that selects one of the signals from the bus 9 and sends it to the memory blocks 10a to 10h.

Next, the operation of the second embodiment will be described. Basically, the operation is the same as that of the first embodiment described above, but since there are three systems of buses, the erase bus 14, the write bus 15 and the bus 9, the erase control unit 7 and the write control unit 8 operate in the memory block 10a. The characteristic feature is that when the start control of the operation of applying a voltage for a long time to 10h and the verify operation are performed, there is no interference with the read operation. If there are three buses as shown in FIG. 2, there will be no interference in writing and erasing operations.

First, the read operation will be described.

A read signal consisting of the control signal 2 and the address 4 is externally used for the instruction analysis and status data generation unit 6
Then, the instruction analysis and status data generation unit 6 confirms whether it corresponds to the memory block during the erase operation or the write operation. If it is in operation, an error status is returned, and if it is not in operation, signals are sequentially sent to the bus 9, the selector circuit 13, the bus 12, and the memory block 10 to read data from the memory cell. And memory block 1
0, the bus 12, the selector circuit 13, the bus 9, the instruction analysis and status data generator 6 are sequentially sent, and the data is sent to the outside to complete the reading.

Whether the memory block is in operation is confirmed by sending a signal to the selector circuit 13 by returning to the instruction analysis and status data generator 6 a busy signal indicating that it is in operation by another bus. You can do it.

Next, the write operation will be described.

When a write signal including the control signal 2, data 3 and address 4 and write data are externally applied to the instruction analysis and status data generation unit 6, the instruction analysis and status data generation unit 6 erases the memory block in which it operates. After confirming that it is not in the middle (in operation) (after confirming that the busy signal is not returned from the selector circuit 13 and the ready signal is returned), the instruction analysis and status data generation unit 6 starts operation to the write control unit 8 through the bus 9j. Send a signal.

The write controller 8 turns on the status signal 8a. The write control unit 8 uses the write bus 15 to sequentially transmit signals to the selector circuit 13, the bus 12, and the memory block 10 to start the write operation. After applying a voltage to the memory cell for a certain period of time, verification is performed, and if the result is OK (OK), the writing is completed, and the write control unit 8 turns off the status signal 8a and notifies the instruction analysis and status data generation unit 6 of the completion.

If verification is not possible (NG), the write operation starts again. This is performed up to the specified number of times, and
In the case of G), the instruction analysis and status data generation unit 6 transmits the write error status to the outside. Further, although it is said that the voltage is applied to the memory cell for the certain period of time, the timer used in the write controller 8 is used.

A feature of the second embodiment is that the write control section 8 performs all the control from the start to the end of writing, occupies the selector circuit 13 and the memory block 10, and does not interfere with the outside at all, so that the speed is high. Can be given.

Next, the erase operation will be described.

The contents are basically the same as the write operation. That is, when the erase signal including the control signal 2, the data 3, and the address 4 and the erase data are externally applied to the instruction analysis and status data generation unit 6, the instruction analysis and status data generation unit 6 is writing to the operating memory block. After confirming that it is not in operation (after confirming that the busy signal is not returned from the selector circuit 13 and the ready signal is returned), the instruction analysis and status data generation unit 6 sends an operation start signal to the erase control unit 7 through the bus 9i. To send.

The erasing controller 7 turns on the status signal 7a. The erase control unit 7 transmits a signal to the selector circuit 13, the bus 12 and the memory block 10 in order using the erase bus 14 to start the erase operation. After applying a voltage to the memory cell for a certain period of time, verification is performed, and if it is possible (OK), writing is completed, and the erase control unit 7 turns off the status signal 7a and notifies the instruction analysis and status data generation unit 6 of the completion.

If the verification is not possible (NG), the erase operation starts again. This is performed up to a prescribed number of times, and if it is not possible (NG), the instruction analysis and status data generation unit 6 transmits the status of the erase error to the outside.

In order to perform the erase, write, and read operations in this way, for example, the write controller 8, the write buses 15 and 15a, the selector circuit 13a, and the bus 12 are used.
a, during erasing in the memory block 10a, the erase control unit 7, erase buses 14 and 14b, selector circuit 13b, bus 12
b, the command analysis and status data generation unit 6, the buses 9 and 9c, the selector circuit 13c, the bus 12c, and the memory block 10c in the state of being written in the memory block 10b.
The read operation is possible with.

In the reading of the second embodiment, during writing,
This is possible in all the memory blocks other than during erasing at random, and as a feature different from the first embodiment, there is an effect that a peripheral circuit becomes simple because a fault does not occur in principle in reading.

[0058]

As described above, the nonvolatile semiconductor memory device according to claim 1 of the present invention is an electrically erasable non-volatile semiconductor memory device divided into a plurality of memory blocks. And an erasing control unit that executes three functions of writing and reading at the same time in different memory blocks, a writing control unit, and instruction analysis
Since it is provided with the status data generation unit and the status data generation unit , it is possible to shorten the test time for discriminating the non-defective product / defective product. In addition, it is possible to easily make a system capable of simultaneous write, erase, and read operations, and it is possible to improve the speed (throughput) of the entire system.

[0059]

As described above, the nonvolatile semiconductor memory device according to claim 2 of the present invention has three buses connecting the erase control unit, the write control unit, the instruction analysis and status data generation unit and the memory block. Inserted,
Because example Bei selector circuit for selecting the three buses,
In addition to the effect of the first aspect, there is an effect that a peripheral circuit can be simplified because a fault does not occur in reading in principle.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

6 instruction analysis and status data generation unit, 7 erase control unit, 8 write control unit, 9 bus, 10 memory block, 11 latch circuit, 12 bus, 13 selector circuit, 14 erase bus, 15 write bus.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 12/00-12/06 G06F 13/16-13/18 G11C 16 / 02,29 / 00

Claims (2)

(57) [Claims] 1. In an electrically batch erasable electrically writable nonvolatile semiconductor memory device divided into a plurality of memory blocks, a command analysis and status data generation for controlling the entire IC are performed.
Write control for controlling the forming unit, the writing into each memory block
Section, an erase control section for controlling erase of each memory block, the instruction analysis and status data generation section, and the write
Memory controller, the erase controller, and each memory block
Address and data are inserted before the connected bus and each memory block.
And a latch circuit for temporarily storing the control signal, the instruction analyzing and status data generating unit, a control signal
A read signal consisting of a signal and an address is given externally.
Then, the corresponding first memory block is inactive.
Send a signal via the latch circuit and the bus.
Data from the memory cells in the first memory block
Read out to the outside , and write signal consisting of control signal, data, and address.
If the number and write data are given from the outside,
If the second memory block of the
Send a start signal, erase signal consisting of control signal, data and address, and
And erase data is given from the outside, the corresponding third message is deleted.
If the memory block is inactive, send an erase operation start signal.
The write control unit sends a write operation start signal to the write operation start signal.
After receiving, when the bus is available, the latch circuit and
And a signal is transmitted via the bus to the second memory
After writing the data to the locked memory cell, the erase control unit receives the erase operation start signal,
When the bus is available, the latch circuit and the bus
In the third memory block by sending a signal via
Erasing the data in the memory cell of the second memory block, reading the first memory block, and
While the third memory block is being written,
A nonvolatile semiconductor memory device characterized in that the lock can be erased at the same time . 2. An electrical circuit divided into a plurality of memory blocks.
Bulk erasable non-volatile semiconductor memory device capable of electrically writing
In command analysis and status data generation for controlling the entire IC
The generation unit, the instruction analysis and status data generation unit, and each
Write control that controls writing to each memory block and the bus that connects the memory blocks
Section, the write control section, and each memory block are connected.
A write bus, an erase controller that controls erase of each memory block, an erase controller that connects the erase controller, and each memory block
Bus and the memory, which is inserted before each memory block.
One from the bus for writing in and the signal from the erasing bus
Select the Bei and a selector circuit to be sent to the memory block
The instruction analysis and status data generation unit
A read signal consisting of a signal and an address is given externally.
Then, the corresponding first memory block is inactive.
Signal via the selector circuit and the bus.
Data from the memory cells in the first memory block.
Data to the outside and a write signal consisting of control signals, data, and addresses.
If the number and write data are given from the outside,
If the second memory block of the
A write operation start signal is sent to the control unit , and an erase signal including a control signal, data, and an address, and
And erase data is given from the outside, the corresponding third message is deleted.
If the memory block is not operating, the erase control unit
An operation start signal is sent, and the write control unit sends the write operation start signal.
After receiving, it goes through the selector circuit and the write bus.
Therefore, a signal is transmitted to the memo in the second memory block.
Writing data to the recell, the erase control unit, after receiving the erase operation start signal,
A signal is sent via the selector circuit and the erasing bus.
Send it of Memorise Le in the third memory block Day
Data is erased, the first memory block is being read, and the second memory block is being read.
While the third memory block is being written,
The feature is that the lock can be erased at the same time .
That nonvolatile semiconductor memory device.