JP2000163314A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide high-speed write concerning a semiconductor disk device using a flash memory with which the speed of write is low in comparison with that of read. SOLUTION: This device has a standard bus 1, plural flash memories 4, a write buffer memory 5 for temporarily holding data and a processor 2. The processor 2 controls the write of data or performs the exchange or analysis of a command or status. An address control part 31 is for generating a physical address, a Vpp generating circuit 6 is the write power source of the flash memory, a memory address bus 71 and a data bus 72 are arranged. The processor 2 writes the continuously written data of one word into any arbitrary flash memory and continuously writes them into the accessible flash memory during the duration until the next data of one word can be written in that flash memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using a flash memory, and more particularly to writing data continuously to a semiconductor disk device using a flash memory.

[0002]

2. Description of the Related Art FIG. 8 shows a data write timing waveform of a flash memory which performs writing and erasing by a command control method according to a conventional technique. In the figure, Vcc is the power supply voltage of the flash memory, and +5 V is constantly applied. Vpp is a write power supply, and applies a potential higher than the power supply voltage Vcc when writing data to the flash memory. The address specifies the data write area of the flash memory in byte units. OE
Is an output enable signal, which is set to Low when data is read from the flash memory, and set to High otherwise. CE is a chip enable signal, which is set to Low when a command or data is read from or written to the flash memory. In addition, CE of the flash memory also serves as a write enable signal.
When pp is high potential and OE is High, data is written at the rise of OE. I / O7 and I / O0-I /
O6 is a data line. Next, 1
The operation when writing byte data is shown. First, C
The command on the data line is written to the flash memory at the timing of the rising edge of E. This command informs the flash memory of the start of writing one word of data,
This is a light setup command. After writing this command, the data on the data line is written into the flash memory at the timing of the rising edge of CE. The low period of the CE at the time of writing this command and data is a minimum of 50 nanoseconds. However, actually, writing to the memory chip has just started inside the flash memory, and the next data cannot be written until the internal writing is completed. Here, a time of several tens of microseconds is required until the writing in the flash memory is completed, which takes a considerable time as compared with the time of writing the command and the data of one word. Status polling is a means for checking that writing within the flash memory chip has been completed after a period of several tens of microseconds. This is CE and OE Low
The status is read from / O7 to determine the end of writing in the memory chip.

[0003]

The above technique requires a considerable amount of time to write a plurality of words of data continuously. The writing of the command and the data of one word is about several tens nanoseconds to several hundred nanoseconds. However, it takes several microseconds to several tens of microseconds from the writing of one word data to the end of the writing in the flash memory chip, during which time the flash memory cannot be accessed. Therefore, the total time for writing one word of data is considerably slower than the reading time. When data of a plurality of words is continuously written, the writing time increases in proportion to the number of words to be written. For example, when a semiconductor disk device is constructed using a flash memory, several kilowords to several tens of kilowords or more data is continuously written.
Then, the write time increases in proportion to the data to be written, so that the transfer of the write becomes slower as a whole system.

An object of the present invention is to provide a semiconductor memory device in which data writing time is reduced.

[0005]

According to the present invention, there is provided a semiconductor memory device having a plurality of flash memories mounted therein and storing data in the flash memories, wherein a write instruction is transmitted to the flash memories. Having a control unit for sending a write instruction to a flash memory different from the flash memory in which writing is being performed until the flash memory to which the write instruction has been sent can accept the next write instruction It is what it was.

More specifically, the present invention comprises, for example, a plurality of flash EEPROMs which are readable and writable in word units and electrically erasable in chip units or word units, with a plurality of bits as one word. In an apparatus for continuously writing data to a flash memory, one word of data is written to any of the flash memories mounted on the writing device, and the written flash memory transfers the next one word of data to the flash memory. One word data is written to a flash memory mounted on the device and different from the flash memory in which writing is being performed during a fixed time period during which writing is possible.

[0007]

In a semiconductor memory device equipped with a plurality of flash memories and storing data in the flash memory, the control unit sends a write instruction to the flash memory, and the flash memory to which the write instruction is sent is transmitted to the next flash memory. Until the write instruction can be accepted, the write instruction is sent to a flash memory different from the flash memory in which the write is being performed.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In this embodiment, in the case of writing continuous data, control is performed so that writing to another flash memory is performed instead of writing to the same flash memory continuously. There is a waiting time of several microseconds to several tens of microseconds between writing one word of data to the flash memory and writing the next data. Therefore, when there is data to be written continuously, one word of data is continuously written to another flash memory during this waiting time. Then, when the waiting time of the first flash memory has passed, status polling is performed from the first flash memory, and data of the next one word is written. In this way, writing to another flash memory is performed during the waiting time of the flash memory.

When a flash memory is used for writing a plurality of continuous data, according to the present embodiment, the low-speed writing of the flash memory can be speeded up in the entire apparatus. That is, when a flash memory is used in a semiconductor disk device, a plurality of continuous data are written. However, in the case of continuous data writing, the writing to the flash memory is slower than the reading, so that the total transfer speed is reduced. However, according to the present embodiment, even if the writing speed of the flash memory is low, the writing speed of the entire device can be increased.

An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a semiconductor disk device using a flash memory. In FIG. 1, reference numeral 1 denotes a standard bus such as a personal computer through which commands and data are transmitted and received from the system. The bus is not particularly limited as long as it has a protocol agreement with a system requiring an auxiliary storage device, such as a SCSI interface or a local bus of the system. 4 is a plurality of flash memories. Reference numeral 5 denotes a write buffer memory for temporarily holding data transferred from the standard bus 1. Since writing is slower in the flash memory than in reading, the flash memory temporarily holds the write data transferred from the standard bus 1 and releases the bus right to the system side earlier. The write buffer memory 5 is composed of a static RAM in the figure. However, the storage element is not limited to the static RAM, and may be any storage element capable of writing at a higher speed than the flash memory 4 irrespective of volatile or non-volatile. Further, a part of the data storage area on the system side may be used instead of the inside of the semiconductor disk device. The write buffer memory 5 has a capacity of a plurality of sectors in units of 512 bytes, which is a standard disk sector capacity. 2 is a processor. The processor 2 controls the writing of data from the write buffer memory 5 to the flash memory 4 and transmits and receives commands and statuses from the standard bus and analyzes the data. Reference numeral 11 denotes a conversion table for converting a logical sector number, which is a sector number managed by the system, to a physical sector number, which is a sector number of an area to be written to the flash memory. This is a static RAM (SRAM) that stores a table (creating a table). An address control unit 31 generates a physical address that is an actual address of the flash memory 4 or the write buffer memory 5, and is controlled by the processor 2. 6 is Vpp which is a write power supply of the flash memory.
, And the generation of power is controlled by the processor 2. Reference numeral 71 denotes a memory address bus of the flash memory 4 and the write buffer memory 5, which is output from the address control unit 31. 72 is a data bus.

FIG. 2 is a flowchart showing a write operation controlled by the processor 2 in the semiconductor disk device having the configuration shown in FIG. It is determined whether the request is a write request from the standard bus 1 (21).
Activates the generation of the write power supply Vpp for the Vpp generation circuit 6 (22). Then, the processor 2 converts the logical sector number, which is a sector number managed by the system, passed from the standard bus 1 into a physical sector number, which is a sector number of an area to be written to the flash memory (2).
3). At this time, the physical sector number is determined so that the flash memory in which data of a plurality of sectors transferred from the standard bus 1 are written in sector units is a separate chip. For example, the first transferred data of one sector is transferred to chip 0 of the flash memory, and the next transferred 1
The data of the sector is allocated to the chip 1 of the flash memory in units of sectors. The determined physical sector number is stored in the write management table shown in FIG. This write management table exists in the address control unit 31. In FIG. 3, 3 transferred from the standard bus 1
Data for one sector is held in blocks 1 to 3 of the write buffer memory 5, and data for one sector of each block is stored in the chip 0 of the flash memory 4.
Sector 3, chip 1 sector 2, chip 2 sector 7
Indicates that writing is to be performed.

When the setting of the write management table is completed, the data of three sectors transferred from the standard bus 1 are received in the three areas of the write buffer memory 5 from the block 1 to the block 3 as specified by the write management table. . Thus, the access right of the standard bus 1 is released, and writing to the flash memory 4 can be processed only in the semiconductor disk device (24).

Then, the data received in the write buffer memory 5 is written in the flash memory 4. First, when the processor 2 selects the table number 0 of the write management table, the physical addresses of the write buffer memory 5 and the flash memory 4 are output to the memory address bus 71. Therefore, the write buffer memory 5
1-word data is read from block 1 of (2)
6) Write a write command to chip 0 of flash memory 4 (27), and write one word of data read from write buffer memory 5 to chip 0 of flash memory 4 (28). With this, chip 0 of the flash memory 4 starts writing data internally,
Chip 0 cannot read or write data until the internal writing is completed. It is determined whether there is data to be written to the next chip (29), and if so, writing to another memory chip is performed during this time. As described at the time of conversion to a physical sector, when writing continuous sectors, each sector is assigned to a different chip. The processor 2 designates the table number 1 of the write management table (25),
1 read from block 2 of write buffer memory 5
The word data is written to the chip 1 of the flash memory 4 (26, 27, 28). Subsequently, one-word data read from the block 3 of the write buffer memory 5 is written to the chip 2 of the flash memory 4 by designating the table number 2 (26, 27, 28).

When one word of data has been written to each of chip 0, chip 1 and chip 2 of the flash memory 4 (29), the status polling of chip 0 of the flash memory 4 to which the data has been written first is performed (33). It is confirmed whether the writing in the chip No. 4 has been completed. At this time, similarly to the writing, the processor 2 reads the status of the chip 0 of the flash memory 4 by designating the table number 0 of the writing management table. Here, if the writing has not been completed inside the chip 0 of the flash memory 4, the status polling is repeated. If the writing has been completed, the counter value of Table 0 of the writing management table is incremented (34). Similarly, it is determined whether or not the next table exists in the write management table (35). If so, the table number 1 is designated, and the status of the chip 1 that has written data next to the chip 0 of the flash memory 4 is specified. Perform polling. Then, if the writing within the chip 1 of the flash memory 4 has been completed, the status polling of the chip 2 of the flash memory 4 to which the data has been written next is performed (33). If all the chips of the flash memory 4 to which the writing has been performed have completed the internal writing, the process returns to the beginning of the writing sequence.

Here, it is determined whether the counter has reached 512 bytes. If the counter has reached 512 bytes, writing of all data from the buffer memory 5 to the flash memory 4 has been completed. If the counter is still 512 bytes or less, the above-mentioned writing method is repeated until the writing of 512 bytes is completed. When the writing of all data from the write buffer memory 5 to the flash memory 4 is completed, the processor 2 causes the Vpp generating circuit 6 to stop generating the write power supply Vpp (3).
7).

As is apparent from the above embodiment, data of three sectors can be written to the flash memory in almost one sector write time. In this embodiment, an example of writing data in three sectors has been described. However, it is apparent that the same applies to writing data in more than three sectors.

In the above embodiment, the flash memory to be written in sector units is allocated to another chip. However, there is also a method of dividing 512 bytes in a sector into a plurality of blocks. Write is assigned to different flash memories in units of the divided blocks. For example, 512 bytes is 32
It is divided into 16 blocks in byte units. And 1
Write 16 blocks from each block to different chips of the flash memory. This is in units of 32 bytes, but may be in arbitrary bytes such as 16 bytes or 64 bytes.

In the above embodiment, the flash memory has a certain waiting time from writing of a write command and one word of data to writing of the next one word of data. However, after writing a page-write command to a flash memory that allows page writing,
A flash memory in which data of a plurality of words can be continuously written, and a flash memory having a certain waiting time from the writing of the data of a plurality of words to the end of the writing to the memory chip inside the flash memory, is similar to the above embodiment. Then, data is written to a flash memory chip different from the flash memory chip to which the data has been written during a period from writing of data in page units to status polling.

The same can be said not only for writing data to the flash memory 4 but also for erasing. The flash memory 4 is erased in a chip unit or a block unit with a plurality of words as one unit. The erasing method is to write an erasing command at the same time as specifying an address indicating a block to be erased in the flash memory 4.
The erasing process in the flash memory 4 is started. Then, a predetermined waiting time is reached until the erasing in the flash memory 4 is completed. During that time, access other than status polling cannot be performed to the flash memory 4 that is performing the erasing process. Then, after a certain period of time, if the end of the internal erasure is confirmed by status polling, the operation proceeds to the next flash memory erasure. During this fixed time, by writing an erase command to a flash memory different from the flash memory that is performing the erase, and simultaneously erasing a plurality of flash memories,
Higher erasing speed is realized in the entire semiconductor disk device.

FIG. 4 is a flowchart showing the erasing operation controlled by the processor 2 in the semiconductor disk device having the configuration shown in FIG. Since it is necessary to apply the write power supply Vpp even when erasing the flash memory 4, the processor 2
Activates the generation of the write power supply Vpp for the Vpp generation circuit 6 (41). Then, the processor 2 sets the physical sector number of the flash memory 4 to be erased in the write management table of FIG. 3 (42). At this time, the area to be erased is set to be another memory chip. In this embodiment, a case where the erasing unit of the flash memory 4 is one sector will be described. After setting the sector to be erased in the write management table, the erase command is written to each chip of the flash memory 4 indicated by the table (44) while updating the designation of the write management table (43). It is determined whether there is a next erase area (45). When all the erase commands have been written, the table specification is updated (46), and status polling is performed from the memory chip to which the erase command was first written (4).
7) Check whether the erasing process in the flash memory 4 has been completed. Then, it is determined whether or not the next table is designated (48). When the erasing process for all the flash memories is completed, the processor 2 causes the Vpp generating circuit 6 to stop generating the write power supply Vpp (49).

The above embodiment has described a flash memory which performs erasing in units of one sector. However, the erasing unit differs depending on the flash memory. Therefore, the method of setting the write management table differs depending on the erase unit of the flash memory. When erasing the flash memory in units of chips, it is sufficient to set only the chip number column of the flash memory in the write management table. In the case of a flash memory that performs erasing in units of a plurality of words, it is a set of two columns of a chip number and a sector number of the flash memory in the write management table. However, even a flash memory that erases in multiple word units,
Erasing is not always performed in units of one sector. When the flash memory erases the capacity of a plurality of sectors as one block,
A plurality of sectors are erased by setting the sector number column of the flash memory in the write management table.

In the above-described embodiment, when a write power supply Vpp is required, such as at the time of writing or erasing, the write power supply Vpp is applied to all the flash memories 4. However, there is also a method in which the write power supply Vpp is applied only to the flash memory for writing. FIG. 5 is a block diagram of a semiconductor disk device according to the embodiment. 61 in the figure is Vp
Power supply V from p generation circuit 6 to flash memory 4
A switch unit for turning on / off the application of pp. The switch unit is controlled by the processor 2 and is capable of selecting the output of a plurality of write power supplies Vpp. Other configurations are the same as those in FIG. When a write request is received from the standard bus 1, the processor 2 activates the Vpp generation circuit 6 to generate a write power supply Vpp. Thereafter, the logical sector number is converted into a physical sector number, and the physical sector number is stored in the write management table of FIG. At this time, the write power supply Vpp to a plurality or one flash memory 4 for writing is changed to Vpp
The voltage is applied according to the designation of the pp switch unit 61. It is apparent that the application of the write power supply Vpp by the designation of the Vpp switch unit 61 is performed not only at the time of writing but also when the flash memory 4 requires the write power supply Vpp such as erasing.

The above embodiment has described the flash memory that requires a write power supply Vpp having a voltage value different from the power supply voltage at the time of writing or erasing. However, a single power supply flash memory, in short, a write power supply Vpp
FIG. 6 is a block diagram of a semiconductor disk device equipped with a flash memory which does not require a flash memory. Although the configuration is the same as that of FIG. 1, it is not necessary to mount the Vpp generation circuit 6. Also, it is clear that the write power supply on / off processing is not required in the write flowchart of FIG. 2 and the erase flowchart of FIG.

In the above embodiment, the chip of the flash memory to be written is selected by the chip enable signal CE. However, there is a method of controlling the selection of the flash memory to be written by the write enable signal WE instead of the chip enable signal CE. FIG. 7 shows a block diagram of the semiconductor disk measures at that time. In the figure, reference numeral 32 denotes a WE selection unit that selectively supplies a write enable signal WE to the flash memory 4 to which writing is performed to the flash memory 4. Other configurations are the same as those in FIG. The WE selection unit 32 enables the write enable signal only for the flash memory in which writing has occurred. The write control performed by the processor 2 is the same as the operation shown in the flowchart of FIG.

Some flash memories 4 do not have the write enable signal WE. When writing data to the flash memory, writing is controlled by controlling the chip enable signal CE and the write power supply Vpp. Even in such a flash memory, high-speed writing and erasing can be achieved by using the present invention.

As is apparent from the above description, according to the present invention, even if a flash memory whose writing is slower than reading is used for an auxiliary storage device or the like having a large amount of writing data, the entire device can be used. There is an effect that writing can be performed at high speed. In particular, the effect is great when a large amount of continuous data is written. In addition, high-speed erasing can be performed for a plurality of areas simultaneously.

[0027]

As described above, the present invention can provide a semiconductor memory device in which the data writing time is reduced because of the above-mentioned configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor disk device according to an embodiment that performs an operation of the present invention.

FIG. 2 is a flowchart showing a write operation of the present invention.

FIG. 3 is a write management table used in the operation of the present invention.

FIG. 4 is a flowchart showing an erase operation according to the present invention.

FIG. 5 is a block diagram of a semiconductor disk device according to one embodiment for performing the operation of the present invention.

FIG. 6 is a block diagram of a semiconductor disk device according to an embodiment for performing the operation of the present invention.

FIG. 7 is a block diagram of a semiconductor disk device according to an embodiment for performing the operation of the present invention.

FIG. 8 is an explanatory diagram of a write timing waveform of one word of the flash memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Standard bus 2 ... Processor 31 ... Address control part 32 ... WE selection part 4 ... Flash memory 5 ... Write buffer memory 6 ... Vpp generation circuit 61 ... Vpp Switch 71: Address bus 72: Data bus

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takashi Tsunehiro 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Japan Microelectronics Equipment Development Laboratory, Hitachi, Ltd.

Claims (16)

[Claims] A bus interface connected to a system bus for receiving write data from the system bus; a plurality of nonvolatile semiconductor memory chips for storing data; a plurality of nonvolatile semiconductor memory chips connected to the plurality of nonvolatile semiconductor memory chips; A buffer memory for holding write data to be written to the plurality of nonvolatile memory chips transferred from the system side via the bus interface, and a buffer memory; the bus interface; the plurality of nonvolatile semiconductor memory chips; A control unit connected to a buffer memory, wherein the control unit reads the write data from the buffer memory in response to a write instruction received from the system by the bus interface; and
A write operation of write data read from the buffer memory to the plurality of nonvolatile semiconductor memory chips is performed. Write data to be written to each of the nonvolatile semiconductor memory chips is transmitted to the system side by the bus interface. And memory-side sector data corresponding to system-side sector data of the standard disk received from the non-volatile semiconductor memory chip. First, a first write address from the control unit and a first write data from the buffer memory are sent, respectively. Second, a second write address from the control unit, Second from buffer memory
And the first write address and the second write address sent from the control unit are physical according to a logical sector address received from the system bus by the bus interface. The control unit is configured to store a physical sector address of the first write address and the second write address in the first write address and the first write address.
Wherein the write data and the second write data are determined before being sent from the buffer memory to designated locations of the plurality of nonvolatile semiconductor memory chips. 2. A bus interface connected to a system bus for receiving write data from the system bus; a plurality of nonvolatile semiconductor memory chips for storing data; and a plurality of nonvolatile semiconductor memory chips connected to the plurality of nonvolatile semiconductor memory chips; By temporarily holding the write data to be written to the plurality of nonvolatile memory chips transferred from the system side via the bus interface, control and use of the system bus can be quickly performed to the system side. A buffer memory for performing transfer, a control unit connected to the bus interface, the plurality of non-volatile semiconductor memory chips, and the buffer memory; In response to the received write instruction, the buffer Read operation of write data from memory, and
A write operation of write data read from the buffer memory to the plurality of nonvolatile semiconductor memory chips is performed. Write data to be written to each of the nonvolatile semiconductor memory chips is transmitted to the system side by the bus interface. From the memory-side sector data corresponding to the system-side sector data received from the plurality of non-volatile semiconductor memory chips, the write operation to the plurality of non-volatile semiconductor memory chips, A first write address from the control unit and a first write data from the buffer memory are sent, and a second write address from the control unit, a second write data from the buffer memory, And the first writing sent from the control unit. The address and the second write address are physical sector addresses according to a logical sector address received from the system bus by the bus interface, and the control unit includes the first write address and the second write address The physical sector address of the first
Wherein the write data and the second write data are determined before being sent from the buffer memory to designated locations of the plurality of nonvolatile semiconductor memory chips. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory disk. 4. The semiconductor memory device according to claim 1, wherein the capacity of said buffer memory is equivalent to a plurality of sector capacities of a standard disk. 5. The semiconductor memory device according to claim 1, wherein each of said plurality of nonvolatile semiconductor memory chips is constituted by one flash memory semiconductor memory chip. 6. The semiconductor memory device according to claim 5, wherein each of said plurality of nonvolatile semiconductor memory chips has a capacity for storing write data of one or a plurality of sectors stored in said buffer memory. A semiconductor device, wherein write data of each sector stored in the buffer memory is written for each memory chip in accordance with a corresponding write instruction. 7. The semiconductor memory device according to claim 1, wherein a sector capacity of said standard disk is 512 bytes. 8. The semiconductor memory device according to claim 1, wherein the write data to be written to each of the nonvolatile semiconductor memory chips is a sector capacity of a standard disk.
A semiconductor memory device wherein a byte is defined as one unit. 9. A bus interface connected to a system bus for receiving write data from the system bus; a plurality of nonvolatile semiconductor memory units for storing data; and a plurality of nonvolatile semiconductor memory units connected to the plurality of nonvolatile semiconductor memory units. Holding the write data to be written to the plurality of nonvolatile memory units transferred from the system side via the bus interface, a buffer memory, the bus interface, the plurality of nonvolatile semiconductor memory units, and A control unit connected to the buffer memory, wherein the control unit reads write data from the buffer memory in response to a write instruction received from the system via the bus interface; and
A write operation of write data read from the buffer memory to the plurality of nonvolatile semiconductor memory units is performed. Write data to be written to each of the nonvolatile semiconductor memory units is transmitted to the system side by the bus interface. From the memory-side sector data corresponding to the system-side sector data received from the plurality of non-volatile semiconductor memory units,
A first write address from the control unit and a first write data from the buffer memory are respectively sent to designated portions of the plurality of nonvolatile semiconductor memory units, and The first write address and the second write address are controlled by sending a second write address and second write data from the buffer memory, respectively, and the first write address and the second write address sent from the control unit are the bus interface. And a physical sector address corresponding to a logical sector address received from the system bus. The control unit stores the physical sector addresses of the first write address and the second write address in the first
Wherein the write data and the second write data are determined before being sent from the buffer memory to designated locations in the plurality of nonvolatile semiconductor memory units. 10. A bus interface connected to a system bus for receiving write data from the system bus, a plurality of nonvolatile semiconductor memory sections for storing data, and connection to all of the plurality of nonvolatile semiconductor memory sections. The write data to be written to the plurality of nonvolatile memory units transferred from the system side via the bus interface is temporarily held, and control and use of the system bus are transferred to the system side. A buffer memory for performing an early transfer; and a control unit connected to the bus interface, the plurality of nonvolatile semiconductor memory units, and the buffer memory. From the buffer memory according to the write instruction received from Read operation of write data, and
A write operation of write data read from the buffer memory to the plurality of nonvolatile semiconductor memory units is performed. Write data to be written to each of the nonvolatile semiconductor memory units is transmitted to the system side by the bus interface. From the memory-side sector data corresponding to the system-side sector data received from the plurality of non-volatile semiconductor memory units,
A first write address from the control unit and a first write data from the buffer memory are respectively sent to designated portions of the plurality of nonvolatile semiconductor memory units, and The first write address and the second write address are controlled by sending a second write address and second write data from the buffer memory, respectively, and the first write address and the second write address sent from the control unit are the bus interface. And a physical sector address corresponding to a logical sector address received from the system bus. The control unit stores the physical sector addresses of the first write address and the second write address in the first
Wherein the write data and the second write data are determined before being sent from the buffer memory to designated locations in the plurality of nonvolatile semiconductor memory units. 11. The semiconductor memory device according to claim 9, wherein said semiconductor memory device is a semiconductor memory disk. 12. The semiconductor memory device according to claim 9, wherein the capacity of said buffer memory is equivalent to a plurality of sector capacities of a standard disk. 13. The semiconductor memory device according to claim 9, wherein each of said plurality of nonvolatile semiconductor memory units is constituted by one flash memory semiconductor memory chip. 14. The semiconductor memory device according to claim 13, wherein each of said plurality of nonvolatile semiconductor memory units has a capacity for storing write data of one or a plurality of sectors stored in said buffer memory. And the write data of each sector stored in the buffer memory is:
A semiconductor memory device wherein data is written for each memory unit in response to a corresponding write instruction. 15. The semiconductor memory device according to claim 9, wherein a sector capacity of said standard disk is 512 bytes. 16. The semiconductor memory device according to claim 9, wherein write data to be written to each of the nonvolatile semiconductor memory units is set to 512 bytes, which is a sector capacity of a standard disk, as one unit. A semiconductor memory device characterized by the following.