JPH1173784A - Semiconductor memory device and data reading method in its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up a reading operation by enabling the reading operation for the address during operation even during the writing or erasing operation and executing the reading for the address of writing or erasing without needing to wait the finish of the writing or erasing operation. SOLUTION: Data and addresses of a writing address and an address within an erasing block are previously stored in a reading resistor 11 using a resistor control circuit 10 at the point in time starting the writing or erasing operation. Thus, if the reading operation for the operation address is generated during the writing or erasing operation, it is controlled with the resistor control circuit 10 so that above data stored at the point in time are substituted for the data output during writing or erasing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a rapid data reading method, and more particularly, to a semiconductor memory device having a flash memory unit in which data is erased in block units and a rapid data reading method.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional semiconductor memory device having a flash memory unit. The respective operations of reading, writing, and erasing data will be described. (1) Data read operation In the case of data read, a control signal for reading is first applied to the read / write / erase control circuit 23, and at the same time, an address signal of an address to be read is applied to the address buffer 28. Can be The address signal is stored in an address latch 29 and is input to a decoder 30 for selecting an address of the memory cell unit 31. The read / write / erase control circuit 23 determines this operation as a read operation by the control signal, activates the decoder 30, and selects the memory cell of the address to be read in the memory cell section 31. The selected memory cell outputs data to the data register 27, and the data is output to the outside of the semiconductor memory device via the input / output buffer 26 as a data output signal. The read operation speed is generally 1
00 ns. (2) Data Write Operation The data write unit is generally a byte unit.

In writing data, first, a control signal for inputting a command to a read / write / erase control circuit 23, an address signal of an address to be written to an address buffer 28, and an input / output buffer 26, a write setup command is added. On the other hand, the read / write / erase control circuit 23 determines that the operation is a command input operation based on the control signal,
The command register 24 is activated. At this time, the write setup command input to the input / output buffer 26 is stored in the data register 27. The command register receives the write setup command stored in the data register 27, and writes the write setup command to the read / write / erase control circuit 23. Inform that it is an action.

Next, a read / write / erase control circuit 23
On the other hand, a control signal for command input is applied, and write data is applied to the input / output buffer 26. Next, the write data is stored in the data register 27. Further, an address signal of an address to be written to the address buffer 28 is input again, stored in an address latch 29, and input to a decoder 30 for selecting an address of the memory cell unit 31. On the other hand,
The write / erase control circuit 23 determines the start of the write operation by the control signal and the previous command, and writes the write data stored in the data register 27 to the memory cell of the memory cell unit 31 selected by the decoder 30. And start the write operation. At this time, the command register 24 sets a flag in the status register 25 to indicate that it is currently busy. When the write operation is completed, the read / write / erase control circuit 23 returns the flag set in the status register 25 via the command register 24 to the original state. The writing operation speed is generally 10
μs. (3) Erasing Operation In the case of erasing data, it is common to treat a plurality of addresses in a specific unit as one block and erase this as one erasing block.

In the case of erasing data, a control signal for command input to the read / write / erase control circuit 23, an address signal of a block address of an erase block to be erased to an address buffer 28, and an input / output An erase setup command is added to the buffer 26. On the other hand, the read / write / erase control circuit 23 determines that the operation is a command input operation based on the control signal, and activates the command register 24.

At this time, the erase setup command input to the input / output buffer 26 is stored in the data register 27, and the command register 24 receives the erase setup command stored in the data register 27, and reads, writes, and erases. The erase operation is transmitted to the control circuit 23.

Next, a read / write / erase control circuit 23
, A control signal for command input is applied, and an erase start command is applied to the input / output buffer 26. This erase start command is stored in the data register 27. The address buffer 28
, The address signal of the erase block address is input again, stored in the address latch 29, and input to the decoder 30 for selecting the address of the memory cell unit 31. On the other hand, the command register 24 is
Received the erase start command and read it out.
An instruction to start the erase operation is issued to the write / erase control circuit 23. Read / write / erase control circuit 23 receiving this
Starts an erase operation on the erase block of the memory cell section selected by the decoder 30. At this time, the command register 24 sets a flag in the status register 25 to indicate that it is currently busy. When the erase operation is completed, the read / write / erase control circuit 23 returns the flag set in the status register 25 via the command register 24 to the original state. The erasing operation speed is generally about several ns.

As described in (1) to (3), in a conventional semiconductor memory device having a flash memory unit in which data is erased in block units, operations such as writing and erasing are controlled by command input. There are read, write and erase operations for the flash memory unit, but the read speed is 100 ns and the write speed is 10 μm.
The s and erasing speeds are about several ns, and the writing or erasing operation takes an enormous amount of time as compared with the reading operation. In general, each operation of reading, writing, and erasing is independent of one write address and one erase block address, and two or more operations cannot be performed in parallel.

[0009]

As described above, in a conventional semiconductor memory device having a flash memory unit in which data is erased in units of blocks, once writing or erasing operation is performed on the flash memory unit, writing or erasing is started. Until the erasing operation is completed, the reading operation of the address data for writing or erasing becomes impossible. In addition, the reading speed is 100 ns, the writing speed is 10 μs, and the erasing speed is about several ns. It takes an enormous amount of time for the writing or erasing operation as compared with the reading operation, and the data at the address of the writing or erasing is found. However, there is a disadvantage that it takes time from the writing or erasing operation to the completion of the reading operation of the address data of writing or erasing.

SUMMARY OF THE INVENTION It is an object of the present invention to make it possible to perform a read operation on a write or erase address during a write or erase operation, and to perform a write or erase operation on the address without waiting for the end of the write or erase operation. An object of the present invention is to speed up a read operation by enabling a read operation.

[0011]

According to the present invention, there is provided a semiconductor memory device having a flash memory unit in which data is erased in units of a block, a data storage unit, an address storage unit, and a data write operation. A write / erase state flag section for storing a flag indicating whether the state is in the erase state or in the erase operation state; a register section including a read register formed of a read / write state; And a read / write / erase control circuit for performing control and a register control circuit for outputting data from a read register when a read is performed to the operation target address during a write or erase operation. And a unit.

It is preferable that the register control circuit of the semiconductor memory device of the present invention has a structure for controlling the read / write / erase control circuit, and the capacity of the data stored in the read register of the present device is the erase block. It is preferable that the number of read registers of the present device is plural.

Further, in the data reading method of the semiconductor memory device according to the present invention, at the start of the writing or erasing operation, the register control circuit stores and stores the data of the address of the writing or erasing in the read register to perform the writing or erasing operation. When a read operation to the relevant address of writing or erasing is performed during this time, the register control circuit outputs the data stored in the read register as read data, so that before the completion of the writing or erasing operation, It is characterized in that writing or erasing of the address data is possible.

A method of reading a semiconductor memory device having a plurality of read registers includes a method for reading a new erase operation when the address of the new write operation is not the address of the current write operation and is not the address in the same erase block. If the erase block address does not include the address during the current write operation, if the address of the new write operation is not included in the block address during the current erase operation, or if a new erase operation occurs during the current erase operation of data. In this case, the operation can be performed in parallel without setting the prohibited operation.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a semiconductor memory device according to the present invention, and FIG. 2 is a configuration diagram of a read register of FIG.

The read / write / erase control circuit 1, command register 2, status register 3, input / output buffer 4, data register 5, address buffer 6, address latch 7, decoder 8, and memory cell unit 9 are conventional flash memory units. This is the same as a semiconductor memory device having In addition to these, the present invention includes a register control circuit 10 and a read register 11. As shown in FIG. 2, the read register 11 stores a data storage section 32 for storing data, an address storage section 33 for storing the address of the data, and indicates whether the data is being written or erased. Write / erase flag section 34 for storing flags
It is composed of

When a read operation is performed on a write or erase operation target address during a write or erase operation, the register control circuit 10 uses the register control circuit 10 at the time of starting the write or erase operation. A register control circuit stores the data and the address of the address in the erase block in the read register 11, and replaces the data output of the address being written or erased with the data stored in the read register 11 when the read operation occurs. By controlling at 10, it is possible to perform a read operation on an address during a write or erase operation without waiting for the end of the write or erase operation.

The present embodiment will be described in more detail.

First, the configuration will be described. In FIG. 1, when a read operation is performed during a write or erase operation, the read register 11 stores data of an address being written or an address in an erase block being erased in advance. This is a register for storing addresses and replacing data output of addresses being written or erased. Further, the register control circuit 10 monitors the data input / output signal, the address signal, and the status register, and
1 is a circuit that controls the data of 1 and gives an instruction of each operation to the read / write / erase control circuit 1.

As shown in FIG. 2, the read register 11 includes a data storage section 32 for storing data, an address storage section 33 for storing the address of the data, and whether or not the data is being written or erased. And a write / erase flag section for storing a flag indicating the flag. The depth n of the address of the register 11 is the same as the depth of an erase block of a semiconductor memory device having a flash memory unit in which data is erased in erase block units.

Next, the actual operation will be described in detail.

(1) When the data read operation is performed independently, the same operation as the data read operation shown in the conventional example is performed. However, at this time, the register control circuit 10 refers to the status register 3 and the write / erase state flag 34 of the read register 11 to confirm that no write or erase operation is being performed, and to transmit data from the memory cell unit 9 to the data register 5. , The read register 1
1 is not referred to.

(2) In the case of independently performing the data write operation, first, a control signal for command input is applied to the read / write / erase control circuit 1 and the address to be written to the address buffer 6. , And a write setup command for the input / output buffer 4 is applied.

Next, the read / write / erase control circuit 1
Determines that the command input operation is performed by the control signal, and activates the command register 2. The address signal of the address to be written input to the address buffer 6 is transmitted to the decoder 8. The write setup command input to the input / output buffer 4 is stored in the data register 5.

Next, the register control circuit 10 stores the data stored in the data register 5 and the address latch 7 in order to prepare for a read, write or erase operation during writing.
Are referred to, and these are stored in the read register 11. At this time, the write data is written to the same address in the read register 11 as the address in the erase block containing the write data.

Next, the command register 2 receives the write setup command stored in the data register 5 and notifies the read / write / erase control circuit 1 of the write operation.

Next, a control signal for command input is applied to the read / write / erase control circuit 1, and write data is applied to the input / output buffer 4. This write data is stored in the data register 5. Further, an address signal of an address to be written to the address buffer 6 is input again, stored in the address buffer 6, and input to a decoder 8 for selecting an address of a memory cell portion.

Next, the read / write / erase control circuit 1
Is determined to be an instruction to start the write operation by the control signal and the previous command, and the register control circuit 1 is applied to the memory cell of the memory cell section 9 selected by the decoder 8.
The write data stored in the data register 5 is transmitted via 0, and the write operation is started. At this time, the command register 2 sets a flag in the status register 3 to indicate that it is currently busy, and the register control circuit 10 sets the write / erase state flag 34 of the read register 11 in the portion where the write target address is stored. Set the writing flag. From this time until the end of the writing, the circuits such as the read / write / erase control circuit 1 and the decoder 8 are released from the writing operation.

Finally, at the stage when the write operation is completed, the read / write / erase control circuit 1 returns the flag, which is set in the status register 3 to indicate the current busy state, via the command register 2 to the original state. Further, the register control circuit 10 restores the writing flag set at the portion where the write target address is stored in the write / erase state flag 34 of the read register 11 to the original state.

(3) When performing the data erasing operation alone, first, a control signal for inputting a command to the read / write / erase control circuit 1 and a control signal for the erase block to be erased in the address buffer 6 An address signal of a block address and a setup command for erasing are added to the input / output buffer 4.

Next, the read / write / erase control circuit 1
Determines that the command input operation is performed by the control signal, and activates the command register 2. The erase setup command input to the input / output buffer 4 is stored in the data register 5.

Next, in order to prepare for reading and writing operations during writing, the register control circuit 10 refers to the addresses of the erase blocks stored in the address latch 7, and corresponds to all the addresses in the erase blocks and their respective addresses. The erased data, that is, the data of all pits “1” is stored in the read register 11.

Next, the command register 2 receives the erase setup command stored in the data register 5 and notifies the read / write / erase control circuit 1 that the operation is an erase operation.

Next, a control signal for command input is applied to the read / write / erase control circuit 1, and an erase start command is applied to the input / output buffer 4. This erase start command is stored in the data register 5. Further, the address signal of the erase block address is input to the address buffer 6 again,
The data stored in the address buffer 6 is input to a decoder 8 for selecting an address of the memory cell portion.

Next, the command register 2 receives the erase start command stored in the data register 5, and the read / write / erase control circuit 1 issues an instruction to start the erase operation. In response to this, the read / write / erase control circuit 1 starts an erase operation on the erase block of the memory cell section selected by the decoder 8. At this time, the command register 2 sets a flag in the status register 3 to indicate that the current state is busy, and the register control circuit 10 sets an erasing flag in all addresses of the write / erase state flag 34 of the read register 11. From this time until the end of the erasure, the circuits such as the read / write / erase control circuit 1 and the decoder 8 are released from the erasing operation.

Finally, at the stage when the erasing operation is completed, the read / write / erase control circuit 1 restores the flag indicating the current busy state set in the status register 3 via the command register 2 to the original state. Further, the register control circuit 10 restores the erase-in-progress flag set at all addresses of the write / erase state flag 34 of the read register 11 to the original state.

(4) Read Operation During Data Write Operation When there is a read operation during the data write operation, which is a feature of the present invention, first, the register control circuit 10 sets the ready / busy flag of the status register 3 With reference to the address storage section 33 and the write / erase state flag section 34 of the read register 11, it is checked whether the address of the read operation is the address during the write operation.

Next, when the address of the read operation is not the address during the write operation, this read operation is read from the memory cell portion in the same manner as a normal read operation. During this time, the write operation is continued.

Next, when the address of the read operation is the address in the write operation, the register control circuit 10 reads the data of the write address stored in the read register 11 in the operation of the third stage (2). Are output to the input / output terminal via the data register 5 and the input / output buffer 4. During this time, the write operation is continued.

(5) Write Operation During Data Write Operation If there is a write operation during the data write operation, first, the register control circuit 10 sets the ready / busy flag of the status register 3 and the read register 11
If the address of the write operation is an address during the write operation and the address of the write operation is not the address during the write operation, the address of the write operation is referred to as the write address. Check whether the address is in the same erase block as the address in operation.

Next, if the address of the write operation is not the address during the write operation and is not the address in the same erase block, the erase operation is ignored because the two write operations cannot be performed simultaneously. You. Therefore, this operation is set in advance as a prohibited operation.

Next, when the address of the write operation is not the address during the write operation and is the address in the same erase block, the register control circuit 10 performs the same operation as the normal write operation in the third stage of the above (2). The operation is performed. At this time, since the write operation cannot be performed concurrently, the register control circuit 10 monitors the status register 3 and
After confirming that the previous write operation has been completed,
The write / erase control circuit 1 is instructed to write an address stored in read, write and erase later, and the next write operation is started.

Next, when the address of the write operation is the address during the write operation, the register control circuit 10 instructs the read / write / erase control circuit 1 to stop the writing,
The operation of the third stage of (2) is performed. At this time, new data is overwritten on the previous data in the read register 11. Next, the register control circuit 10 reads the data other than the write address from the data of the erase block including the write address from the memory cell portion and copies the read data to the corresponding address of the register 11. Next, the read / write / erase control circuit 1 is instructed to perform an erase operation on the erase block in which data has been copied. Next, the status register 3 is monitored, and when the erase operation is completed, the read register 11
Then, the read / write / erase control circuit 1 is instructed to rewrite the data saved at the address for each erase block for each address.

(6) Erasure Operation During Data Write Operation First, when an erase operation is performed during data write operation,
The register control circuit 10 refers to the address register 33 and the write / erase state flag unit 34 of the status register 3 and the read register 11 to check whether the erase block address of the erase operation includes the address during the write operation.

Next, when the erase block address of the erase operation does not include the address during the write operation, the erase operation is ignored because the write operation and the erase operation cannot be performed simultaneously. Therefore, this operation is set in advance as a prohibited operation.

Next, when the erase block address of the erase operation includes the address during the write operation, the register control circuit 10 instructs the read / write / erase control circuit 1 to stop the writing, and A three-stage operation is performed. Next, the read / write / erase control circuit 1 is instructed to perform an erase operation on the erase block.

(7) Read Operation During Data Erase Operation First, when there is a read operation during the data erase operation,
The register control circuit 10 refers to the status register 3 and the address storage unit 33 and the write / erase state flag unit 34 of the read register 11 to check whether the address of the read operation is included in the erase block address during the erase operation.

Next, when the address of the read operation is not included in the block address during the erase operation, this read operation is read from the memory cell portion, similarly to the normal read operation. During this time, the write operation is continued.

Next, when the address of the read operation is included in the block address during the erase operation, the third address of (3)
The register control circuit 10 reads the data of the read address stored in the read register 11 by the operation of the stage, ie, the data of all pits “1”, and outputs the data to the input / output terminal via the data register 5 and the input / output buffer 4. You. During this time, the erasing operation is continued.

(8) Write Operation During Data Erase Operation First, when there is a write operation during data erase operation,
The register control circuit 10 refers to the status register 3 and the address data of the read register 11 and the write / erase state flag section 34 to check whether the address of the write operation is included in the block address during the erase operation.

Next, if the address of the writing operation is not included in the block address during the erasing operation, the erasing operation and the writing operation cannot be performed simultaneously, so that the writing operation is ignored. Therefore, this operation is
Put as prohibited operation.

Next, when the address of the write operation is included in the block address during the erase operation, the register control circuit 10 performs the third stage operation (3) as in the normal write operation. At this time, since the erasing operation and the writing operation cannot be performed simultaneously, the register control circuit 10 monitors the status register 3 and confirms that the previous erasing operation has been completed. 1,
Thereafter, a write command for an address stored for reading, writing and erasing is issued, and the next writing operation is started.

(9) Erasing operation during data erasing operation If an erasing operation is performed during the data erasing operation, the two erasing operations cannot be performed simultaneously, so that the erasing operation entered later is ignored. You. Therefore, this operation is set in advance as a prohibited operation.

In this embodiment, as shown in (4) and (7), when a read operation is performed on an address being written or erased during a write or erase operation,
The data and the address of the address being written or the address in the erase block being erased are stored in the read register 11 in order to replace the data output of the address being written or erased without waiting for the end of the write or erase operation. A read operation can be performed on an address during a write or erase operation.

In this embodiment, (1) and (2)
As shown in (3) and (3), the single operation of reading, writing and erasing is performed in the same manner as in a semiconductor memory device having a conventional flash memory unit. Also,
As shown in (5), (6), (8) and (9),
Write operation during write operation, erase operation during write operation,
The writing operation during the erasing operation and the erasing operation during the erasing operation are also configured and processed so that they can be efficiently processed.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram of a second embodiment of the present invention.

In FIG. 3, the configuration having a register control circuit 21 and a read register is the same as that of the first embodiment.
2, a plurality of read registers are provided. The configuration of each register is the same as that of the read register of the first embodiment. Operationally, the first embodiment is described in (5)
Are the same except for the second stage of (6), the second stage of (6), the second stage of (8) and (9).

In the present embodiment, since a plurality of read registers are provided to form the read register group 22, the read registers used in the previous operation are avoided, and the data of the next operation is stored in the unused read registers. The register control circuit 21 controls such that the next operation is started when the previous operation is completed, so that a plurality of commands can be continuously executed by the number of read registers,
The second operation of (5), which was a prohibited operation in the first embodiment.
There is an advantage that the operation of the second stage of (6), the second stage of (8) and (9) is not prohibited.

[0061]

At the start of the write or erase operation, the register control circuit stores and stores the data of the address of the write or erase in the register section, and the read operation of the write or erase to the address during the write or erase operation. Is performed, the register control circuit outputs the data stored in the register section as read data, so that the data read operation of the write or erase address can be performed without waiting for the completion of the write or erase operation. It becomes possible.

Thus, when a read operation to the write operation target address occurs during the write operation, the conventional 1
The present invention has an effect that what takes about 0 μs + 100 ns can be completed in about several hundred ns in the present invention. Further, in the case where a read operation to an address in the block concerned in the erase operation occurs during the erase operation, the present invention takes about several s + 100 ns, but in the present invention, there is an effect that it can be done in several hundred ns.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a configuration diagram of a read register of FIG. 1;

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 1, 12, 23 Read / write / erase control circuit 2, 13, 24 Command register 3, 14, 25 Status register 4, 15, 26 Input / output buffer 5, 16, 27 Data register 6, 17, 28 Address buffer 7 , 18, 29 Address latch 8, 19, 30 Decoder 9, 20, 31 Memory cell unit 10, 21 Register control circuit 11 Read register 22 Read register group 32 Data storage unit 33 Address storage unit 34 Write / erase state flag unit

Claims (7)

[Claims] In a semiconductor memory device having a flash memory unit in which data is erased in block units, a data storage unit, an address storage unit, and whether or not a data writing operation is being performed and whether an erasing operation is being performed are performed. A write / erase state flag section for storing a flag indicating whether the register section includes a read register; and a read / write / erase control circuit for controlling the register section for reading, writing, and controlling at normal times. A register control circuit configured to output data from the read register when data is read from the operation target address during a write or erase operation. Semiconductor storage device. 2. The register control circuit according to claim 1, wherein said register control circuit also controls said read / write / erase control circuit.
13. The semiconductor memory device according to claim 1. 3. The capacity of data stored in a read register can be equal to the capacity of an erase block.
13. The semiconductor memory device according to claim 1. 4. The semiconductor memory device according to claim 2, wherein a plurality of read registers are provided. 5. The semiconductor memory device according to claim 3, wherein a plurality of read registers are provided. 6. A data read method for a semiconductor memory device, wherein at the start of a write or erase operation, a register control circuit stores and stores data of the write or erase address in a read register, and writes during a write or erase operation. Alternatively, when a read operation is performed on the relevant address for erasure, the register control circuit outputs the data stored in the read register as read data, so that the write or erase operation is performed before the completion of the write or erase operation. A data reading method, wherein the address data can be read. 7. A read method for a semiconductor memory device having a plurality of read registers, wherein a new erase operation is performed when an address of a new write operation is not an address in a current write operation and is not an address in the same erase block. If the erase block address does not include the address during the current write operation, if the address of the new write operation is not included in the block address during the current erase operation, or if a new erase operation occurs during the current erase operation of data. A data reading method characterized in that even if there is a case, the operation can be performed in parallel without setting a prohibited operation.