JP2003256266A - Memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accelerate data write processing in a memory device wherein the time required for writing data is longer than the time required for reading data. <P>SOLUTION: In the memory device having a data read function for reading and outputting data stored in an address designated by a host 140 and a data write function for writing designated write data into an address designated by the host 140, when carrying out the data write function, write data inputted from the host 140 are written in a second memory, data stored in the address designated by the host 140 are read from a first memory 110 to the second memory 120, two pieces of data are compared and it is decided whether two pieces of data are coincident or not. When two pieces of data are coincident, processing for writing the write data into the first memory 110 is omitted. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device using a memory in which the time required for a data write process is longer than the time required for a data read process, and in particular,
The present invention relates to a memory device having a non-volatile memory (eg, flash memory).

[0002]

2. Description of the Related Art As a means for writing data to a non-volatile memory device, a non-volatile memory having a flash memory and a dual port RAM having the same capacity as the flash memory is disclosed in Japanese Patent Laid-Open No. 9-161489. In the device, the host writes the data to the dual port RAM, and in order to match the data of the dual port RAM with the data of the flash memory, the host stores the data stored in the dual port RAM and the data stored in the flash memory. When the data inconsistency is detected by sequentially comparing from the first address to the last address, the erase block including the address in which the inconsistency is detected is erased, and the data in the range of the erase block is dual port RA.
There is a technique of reading the data from M and writing the data in the flash memory to make the data in the erase block the same as the data in the dual port RAM.

[0003]

In the above-mentioned conventional technique, since the flash memory and the dual port RAM sequentially compare all the data, the data write processing time becomes long. Further, since the data write processing time becomes long, the risk of losing the data in the dual port RAM before it is written in the flash memory increases due to the power cutoff due to an unexpected accident or the like.

An object of the present invention is to provide a memory device which speeds up data write processing.

[0005]

In order to achieve the object of the present invention, a data read function for reading and outputting data stored at an address designated by a host, and a data read function designated at the address designated by the host. In a memory device having a data write function of writing the written write data, a first memory having a longer time required to write the data than a time required to read the data, and a data read time longer than the first memory And the data writing time is short
Memory and a memory device control unit for controlling the first memory and the second memory, and the memory device control unit transmits and receives data between the host and the first memory. In the above, a function of using the second memory as a buffer is provided, and the memory control unit, when executing the data write function, writes the write data input from the host and the first memory to the host. Data comparison means is provided for comparing the data already stored at the specified address and determining whether the two data match. If the two data match, the ride data is The function of not writing to the first memory is provided. Alternatively, when the first memory writes data, in a memory device which needs to execute a process of initializing the data of the address to a specific value in advance, the memory device control unit is When executing the data write function, there is provided means for determining whether or not the data of the address designated by the host of the first memory has a specific value. When the data has the value, the initialization processing is performed. The function that is not executed is provided.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below.

FIG. 1 shows a memory device 10 to which the present invention is applied.
The internal structure of 0 is shown. The memory device 100 is connected to a host device 140 such as a CPU or ASIC,
It has a function of performing a read operation and a write operation in accordance with the data read and data write instructions issued by the host device 140. The memory device 100 includes a first memory 110, a second memory 120, and a memory device controller 130.

The first memory 110 has a function of reading data and writing data, and the time required to write data is longer than the time required to read the same amount of data. Is. For example, when the access unit for writing and reading is 2 kilobytes, a memory is used that takes about 1 millisecond to write data of 2 kilobytes and takes about 100 microseconds to read data of 2 kilobytes. can do. First
Further, the memory 110 may be a memory that needs to be erased in advance when writing data. In this case, the time required to erase the area is longer than the time required to read the data in the area. For example, when the access unit for erasing is 2 kilobytes, a memory can be used in which the time required for erasing processing of a 2 kilobyte area is 1 millisecond and the time required for reading data of 2 kilobytes is 100 microseconds. . Further, it may be non-volatile. For the first memory 110, for example, a flash memory can be used.

The values of the write access unit, the read access unit, the erase access unit, the write processing time, the read processing time, and the erase processing time of the first memory 110 described above are examples only, and the type of memory device and the driving method are used. Different values may be taken depending on conditions such as voltage.
Further, the write access unit, the read access unit, and the erase access unit may not match. For example, the write access unit and the read access unit are 512
The erase access unit may be 16 kilobytes in bytes.

The second memory 120 is a memory having the characteristic that the reading and writing processes can be performed at a higher speed than the first memory 110. For example, when the access unit for reading and writing is 1 byte, each memory can be accessed once in 50 nanoseconds. In this case 2
The memory is capable of reading and writing kilobytes of data in about 100 microseconds each. For example, a RAM or a data register can be used.
The second memory 120 is the host 140 and the first memory 11
It can be used as a buffer in the data transmission / reception process between 0. In addition, the second memory 1 mentioned above
The values of the write access unit, the read access unit, the write processing time, and the read processing time of 20 are merely examples, and may take different values depending on conditions such as the type of memory device and drive voltage. For example, the write access unit and the read access unit may each be 2 bytes.

The memory device controller 130 includes a host 140.
In accordance with the operation instruction from the above, it has a function of integrally controlling each unit of the memory device 100. For example, when a data write instruction is accepted, the first memory 110 that writes data
Address and the data to be written are received, and the data is written to the address in the first memory 110 via the second memory 120. Alternatively, when the data read instruction is accepted, the first memory 1 that reads the data
10 addresses are received, data is read from the address of the first memory 110, and the data is output to the host 140 via the second memory 120. Further, the memory device controller 130 may have an operation reporting unit for reporting the operating state to the host 140. Further, the memory device controller 130 has a data comparison unit 131.

The data comparing means 131 has a function of comparing the comparison source data and the comparison destination data of a specific size and detecting the match / mismatch of the two data. For example, the function may be configured to compare data stored in two registers, or may be configured to compare data stored in two areas having different addresses in the second memory 120. The configuration may be such that the register and the data stored in the area in the second memory 120 are compared.

Next, an outline of an operation example of the memory device 100 during a data write process will be described.

FIG. 2 is a flow chart showing an example of the outline of the processing flow for writing data to the memory device 100.

When the memory device 100 receives a write command input from the host 140 (201), the data write process is started. Next, the write address and the write data are accepted (201, 203). Host 14 here
The data received from 0 is not directly written to the first memory 110, but is once written to the second memory 120. Next, the data of the designated address is read from the first memory 110 (204). Here, the data received from the host 140 and the data read from the first memory 110 are compared (205). When the two data match, the write processing is ended here (206). If the data do not match, it is determined whether the area of the first memory 110 has been erased (207). The determination of erased is performed by comparing the data read from the first memory 110 with a data value indicating that the first memory 110 has been erased. If the area has already been erased, the write data received from the host 140 is written to the address specified by the host 140 in the first memory 110 (209). If the area has not been erased, the address specified by the host 140 of the first memory 110 is erased (208), and then the write data received from the host 140 is written to the address (20).
9). When the writing is finished, the write process is finished.

By making the data write process a flow in which the data is read and compared once before the data is written as described above, the same data that the host tried to write will be written by the host. If the data is already stored in the area of the first memory 110, the process of writing the data in the area of the first memory 110 can be omitted. Here, since the first memory 110 has a longer write processing time than the read processing time as described above,
By omitting the writing process, the time required for the data writing process can be shortened, and the data writing process can be speeded up. Further, as described above, when the data match, the writing process to the first memory 110 is not performed, so that the first memory 110 is written as compared to the case where the data is written each time without comparing the data. The number of writing processes can be reduced. According to the present invention, since the number of times of writing can be reduced as described above,
When the first memory 110 is a memory with a limited number of times of writing, such as a flash memory, the life of the memory can be extended. Further, since the number of times of writing can be reduced as described above, the probability of occurrence of a writing error due to an unexpected accident such as power shutoff during the process of writing data in the first memory 110 is reduced, and reliability is improved. it can. Further, by making the data write processing a flow in which the data is read and compared once before writing the data as described above, the area of the first memory 110 where the host tried to write the data has already been erased. If completed, the erasing process of the area of the first memory 110 can be omitted. Here, since the first memory 110 has the erase processing time longer than the read processing time as described above, the time required for the data write processing can be shortened by omitting the erase processing, and the data write processing can be speeded up.

Here, the first memory 110 is composed of a plurality of banks, and the background erasing can perform the erasing process to another bank in parallel with the writing process or the reading process of the data to a certain bank. It may be a memory having a function. Memory device 100 using first memory 110 having the background erasing function
In this case, the host can erase the address to write the data in advance by the background erasing function prior to the data write processing, so that the effect of accelerating the data write processing can be further improved.

Although FIG. 2 shows an example of reading the data of the first memory 110 after receiving the write data, the order is changed and the first memory 110 is changed.
The write data may be accepted after reading the data of. Alternatively, the two processes may be executed in parallel. When the two processes are executed in parallel, the data write processing time can be shortened as compared with the case where the two processes are continuously executed. After accepting the write data, the end of the write data may be notified and a write start command for instructing the start of the write processing may be issued. During the execution of each process, a signal indicating that the process is being executed, such as a busy signal, may be reported to the host 140.

After execution of each process, it may be reported to the host 140 whether each process has been completed normally. At this time, if the termination is not normal, what abnormality may have occurred may be reported to the host 140. When the processing result is reported to the host as described above, the host can easily grasp the state of the memory device 100,
The controllability of the memory device 100 is improved.

Further, here, as the first memory 110, it is premised that a memory such as a flash memory which needs to be erased in advance when writing data is used. As described above, if a memory that does not require the erasing process is used as the first memory 110, steps 207 and 208 of the flow can be omitted.

If the two data match, the process of writing the write data input from the host into the first memory 110 as described above is omitted and the data write process is terminated (206). Here, the write data may be discarded, or the write data may be retained in the second memory 120 until the next memory access from the host, and when the next memory access is a data read, it is used as cache read-ahead data. You may decide to use it.

Next, an outline of an operation example of the data read process of the memory device 100 will be described.

FIG. 3 is a flow chart showing an example of the outline of the processing flow for reading data from the memory device 100.

When the memory device 100 receives the read command, the data read process is started (301). Subsequently, when the read address is accepted (302), the data stored in the address of the first memory 110 is read (303) and written in the second memory 120. Then, the data in the second memory 120 is output to the host 140 (304). During execution of each processing, the host 14 receives a signal indicating that the processing is being executed, such as a busy signal.
You may report to 0. After the execution of each process, it may be reported to the host 140 whether each process has ended normally.
At this time, if the termination is not normal, what abnormality may have occurred may be reported to the host 140.

Next, a more detailed application example of the data write process will be described.

FIG. 4 is a flow chart showing an example of the processing flow of the data write processing. Here, the data write instruction from the host 140 is given in two stages. In the first step, a process of transferring write data from the host 140 to the memory device 100 is instructed, and in the second step, a process of writing the transferred data in the first memory 110 is instructed.

The memory device 100 receives an instruction from the host 140 to transfer write data (40
1). Then, the address to write the data is accepted (402). Here, with respect to the host 140, the memory device 1
A data reception busy signal for waiting the input of data to 00 is issued (403). Next, the first memory 11
The data stored in the address designated by the host 140 is read from 0 (404) and written in the second memory 120. When this processing ends, the data input reception busy signal is released to the host 140 (405), and then the write execution command is received from the host 140 (40).
Up to 7), accept write data input (40
6). The received data is written in the second memory 120. When a write execution command is received from the host 140 (407), a command reception busy signal for waiting for command input is issued (408), and then the data erasing / writing process (409) is started.

At this time, the write data is received from the host 140, and at the same time, the data read from the first data and the write data are compared in parallel (412). When the erase / write processing is completed, the command reception busy signal is released to the host 140 (410), and then the host 1
The operation state is reported to 40 (411), and the data write process ends.

Next, the comparison process and the erase write process shown in FIG. 4 will be described in detail.

FIG. 5 is a flow chart showing an example of a detailed processing flow of the comparison processing 412 in the data write processing shown in FIG. The data comparison process 412 is a process of comparing the data read from the first memory 110 with the write data and determining whether the two match. At this time, it is assumed that the comparison process can be divided and performed for each data of a specific size. Data of this size is used as a data comparison unit. All data may be compared at once.

First, a data comparison pointer is set at the head of the read data (501). The data comparison pointer is a pointer that indicates the progress of the comparison process when the two pieces of data are divided and the comparison process is performed. Next, it waits for write data to be input from the host 140 (502). Host 140 stores data for the data comparison unit
When received from, the data and the first memory 110
Of the data read from, the data at the location pointed to by the data comparison pointer is compared (503). When all the data in the data comparison unit match (504), it is determined whether the process of comparing all the write data is completed (5
13). If the comparison of all write data is not completed, the data comparison pointer is advanced (501) and the write data input from the host 140 is waited again (502).
Repeat the process. If even some of the data in the data comparison unit do not match (504), it is determined whether the mismatch flag is set (505). If the mismatch flag is not set, the mismatch flag is set (507). Next, it is determined whether the data has been erased (506). Among the data read from the first memory 110, this is
It is determined whether or not the data at the location pointed to by the data comparison pointer has a value indicating that the data has been erased. If it is determined that the data has been erased (508), the process proceeds to a process (513) of determining whether or not all the data have been compared.

Here, the mismatch flag means the first memory 1
This is a flag indicating that the data read from 10 does not match the write data input from the host. If it has not been erased, it is determined whether the unerased flag is set (509). The unerased flag is the first
Is a flag indicating that the area of the memory 110 has not been erased. If the unerased flag is set, a process for determining whether or not all data has been compared (5
Proceed to 13). If the unerased flag is not set, the unerased flag is set (510). Next, it is determined whether the parallel erasing process is permitted (51
1).

When the parallel erasure is not permitted, the process proceeds to a process (513) for judging whether or not all the data have been compared. When the parallel erasure is permitted, the parallel erasure is started (512), and then the process proceeds to a process for determining whether or not all the data have been compared (513). Here, the parallel erasure means that in parallel with the reception of data input from the host 140,
This is a process of executing an erasing process of the area of the first memory 110. When the processing is executed, the data write processing time can be shortened as compared with the case where the erase processing is started after all the data input reception is completed. Whether to allow parallel erasure can be set, for example, when the memory device 100 is manufactured, when it is shipped, when the power is turned on, when a data write command is received, and the like.

FIG. 6 is a flow chart showing an example of a detailed processing flow of the erase write processing 409 in the data write processing shown in FIG.

First, the process waits until the comparison process 412 is completed (601). When the comparison process 412 is completed, it is determined whether or not the mismatch flag is set (60
2). If the mismatch flag is not set, the erase / write process is terminated (602). If the mismatch flag is set, it is determined whether the unerased flag is set (603).

If the unerased flag is not set, the write data written in the second memory 120 is written to the designated address in the first memory 110 and the erase / write process is terminated (607). If the unerased flag is set, it is determined whether parallel erasure is in progress (604).

If parallel erasure is being executed, the process waits until the erasing process is completed (606). If parallel erasing is not being executed, the erasing process is started (605). When the erasing process is completed (606), the write data written in the second memory 120 is written to the designated address in the first memory 110 and the erasing / writing process is completed (60).
7).

The above flags are reset at the start or end of the data write process.

In the above example, the data reception busy is issued to the host while the data is being read, and the host waits for data input to the memory device 100 until the data reception busy is released. .

Next, an application example of the present invention will be described in which the host does not need to wait for data input as described above and the host controls the memory device 100 more easily.

FIG. 7 is a flow chart showing an example of the processing flow of the data write processing.

The memory device 100 receives an instruction to transfer write data from the host 140 (70).
1). Then, the address to write the data is accepted (702). Next, input of write data is received (703) until a write execution command is received from the host 140 (704). After receiving a write execution command from the host 140 (704), after issuing a command reception busy signal for waiting the input of the command (7)
05), data comparison processing is performed (706). Here, in parallel with receiving write data from the host 140,
Data is read from the first memory 110 (710). Next, erase / write processing is performed (707). When the erasing and writing process is completed, the command reception busy signal is released to the host 140 (708), the operation state is reported to the host 140 (709), and the data write process is completed.

Next, the comparison process 706 and the erase write process 707 shown in FIG. 7 will be described in detail.

FIG. 8 is a flow chart showing an example of a detailed processing flow of the comparison processing 706 in the data write processing shown in FIG.

The data comparison process 706 is a process of comparing the data read from the first memory 110 and the write data to determine whether or not they match. At this time, the comparison process 706 can be performed by dividing each data of a specific size. Data of this size is used as a data comparison unit. All data may be compared at once.

First, it waits for data to be read from the first memory 110 (801). When the data is read from the first memory 110, the data comparison pointer is set at the head of the read data (802). The data comparison pointer is a pointer that indicates the progress of the comparison process when the two pieces of data are divided and the comparison process is performed. When the data for the data comparison unit is received from the host 140, the data at the location indicated by the data comparison pointer in the write data and the data at the location indicated by the data comparison pointer among the data read from the first memory 110 are displayed. Compare (803). If all the data in the data comparison unit match (804), it is determined whether the comparison processing of all write data has been completed (813). If the comparison is not completed, the data comparison pointer is advanced (80
2) Then, the data comparison process (803) is repeated again.

If some of the data in the data comparison unit also do not match (804), it is determined whether the mismatch flag is set (805). If the mismatch flag is not set, set the mismatch flag (8
07). Here, the mismatch flag means the first memory 110.
It is a flag indicating that the data read from the host does not match the write data input from the host.

Next, the erase completion determination is performed (806). Among the data read from the first memory 110, this is
It is determined whether or not the data at the location pointed to by the data comparison pointer has a value indicating that the data has been erased. If it is determined that the data has been erased (808), the process proceeds to the process of determining whether or not the comparison of all data is completed (8).
13).

If it has not been erased (808), it is determined whether the unerased flag is set (80).
9). The unerased flag is a flag indicating that the area of the first memory 110 has not been erased. If the unerased flag is set (809), the process proceeds to the process of determining whether or not all the data have been compared (81).
3).

If the unerased flag is not set (809), the unerased flag is set (810). Next, it is determined whether the parallel erasing process is permitted (811). If parallel erasure is not permitted, the process proceeds to a process of determining whether or not all the data have been compared. When the parallel erasure is permitted, after starting the parallel erasure (812), the process proceeds to a process (813) of determining whether or not all the data have been compared. Here, the parallel erasing is a process of executing the erasing process of the area of the first memory 110 in parallel with the reception of the data input from the host 140.
When the processing is executed, the data write processing time can be shortened as compared with the case where the erase processing is started after all the data input reception is completed. Whether or not parallel erasure is permitted is determined, for example, when the memory device 100 is manufactured, when it is shipped, when the power is turned on,
It can be set when receiving a data write command.

FIG. 9 is a flow chart showing an example of a detailed processing flow of the erase / write processing 707 in the data write processing shown in FIG.

First, the process waits until the comparison process is completed (901). When the comparison process is completed, it is determined whether the mismatch flag is set (902). If the mismatch flag is not set, the erase / write process is terminated. If the mismatch flag is set, it is determined whether the unerased flag is set (90
3). If the unerased flag is not set, the write data written in the second memory 120 is written to the designated address in the first memory 110, and the erase / write process ends (907). If the unerased flag is set, it is determined whether parallel erasure is being executed (904). If parallel erasing is in progress, the process waits until the erasing process is completed (906). If parallel erasing is not being executed, the erasing process is started (905).

When the erasing process is completed, the second memory 120
The write data written to the first memory 110 is written to the designated address in the first memory 110, and the erase / write process is completed.

The above flags are reset at the start or end of the data write process.

Next, the memory device 10 to which the present invention is applied
An example of the No. 0 embodiment will be described.

FIG. 10 is a block diagram showing an embodiment of the present invention.

The memory device 1000 comprises a first memory chip 1010 and a memory device control chip 1050. The first memory chip 1010 corresponds to the first memory 110 in the memory device 100 shown in FIG. 1, and is a memory chip that itself functions as a normal memory device. The memory device control chip 1050 includes a memory device control unit 130 and a second memory device control unit 130 in the memory device 100 shown in FIG.
It corresponds to a chip including the memory 120. The memory device 1000 is a multi-chip package in which the first memory chip 1010 and the memory device control chip 1050 are connected by, for example, wire bonding and sealed in one package.

By using the multi-chip package as described above, by using the existing first memory chip 1010 which does not have the data write speed-up function of the present invention in combination with the memory control chip 1050, The present invention can be used as the memory device 1000 having the data write speed-up function of the invention. Further, in the case of the multi-chip package as described above, the development man-hours can be reduced as compared with the case where all the functions of the memory device 100 are configured on one chip. In addition, for example, the first memory chip 10
If a memory device 1000 having a larger memory capacity of 10 is to be manufactured, it is not necessary to redesign the entire memory device 1000, and only the first memory chip 1010 may be replaced with a memory chip having a desired capacity. ,
Development man-hours can be reduced.

Here, the chip means an integrated circuit formed on one silicon piece. What is a package?
The above chip is sealed with a material such as ceramic or plastic, and is formed by TSOP (Thin Sma).
ll Outline Package) and BGA (B
all Grid Array).

FIG. 11 is a block diagram showing an example of another embodiment of the present invention.

The memory device 1100 comprises a first memory chip 1110, a second memory chip 1120, and a memory device control chip 1150. The first memory chip 1110 corresponds to the first memory 110 in the memory device 100 shown in FIG. 1, and is a memory chip that itself functions as a normal memory device. The second memory chip 1120 corresponds to the second memory 120 in the memory device 100 shown in FIG. 1, and is a memory chip that itself functions as a normal memory device. The memory device control chip 1150 corresponds to the memory device control unit 130 in the memory device 100 shown in FIG. In the memory device 1100, the memory device control chip 1150, the first memory chip 1110 and the second memory chip 1120 are connected by, for example, wire bonding to form a multi-chip package enclosed in one package. By using the multi-chip package as described above, the existing first memory chip 1110 that does not have the data write speedup function of the present invention is used in combination with the second memory chip 1120 and the memory control chip 1150. Therefore, the memory device 110 having the data write speed-up function of the present invention is provided.
It can be used as 0. In the case of the multi-chip package as described above, the memory device 100
It is possible to reduce the development man-hours as compared with the case where all the functions are configured on one chip. Further, for example, the memory device 110 in which the memory capacity of the first memory chip 1110 is larger
When it is attempted to manufacture 0, it is not necessary to redesign the entire memory device 1100, and the first memory chip 1110
You can reduce development man-hours because you only need to replace Similarly, for example, when attempting to manufacture a memory device 1100 having a larger memory capacity of the second memory chip 1120, it is not necessary to redesign the entire memory device 1100 and only the second memory chip 1120 needs to be replaced. The development man-hours can be reduced.

[0062]

According to the present invention, the data write processing can be speeded up.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of an internal configuration of a memory device to which the present invention is applied.

FIG. 2 is a diagram showing an example of a flowchart of a data write process in a memory device to which the present invention is applied.

FIG. 3 is a diagram showing an example of a flowchart of a data read process in a memory device to which the present invention is applied.

FIG. 4 is a diagram showing an example of a flowchart of a data write process in a memory device to which the present invention is applied.

FIG. 5 is a diagram showing an example of a flowchart of data comparison processing in a memory device to which the present invention is applied.

FIG. 6 is a diagram showing an example of a flowchart of an erase / write process in a memory device to which the present invention is applied.

FIG. 7 is a diagram showing an example of a flowchart of a data write process in a memory device to which the present invention is applied.

FIG. 8 is a diagram showing an example of a flowchart of data comparison processing in a memory device to which the present invention is applied.

FIG. 9 is a diagram showing an example of a flowchart of erase / write processing in a memory device to which the present invention is applied.

FIG. 10 is a diagram showing an example of an embodiment of a memory device to which the present invention is applied.

FIG. 11 is a diagram showing an example of an embodiment of a memory device to which the present invention is applied.

[Explanation of symbols]

100, 1000, 1100 ... Memory device, 110 ... First memory, 120, 1020 ... Second memory, 13
0, 1030, 1130 ... Memory device control unit, 131 ...
Data comparison means, 140 ... Host, 1010, 1110
... first memory chip, 1120 ... second memory chip, 1050,1150 ... memory device control chip

Continued front page    (72) Inventor Shinya Iguchi             1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture             Ceremony company Hitachi Systems Development Laboratory (72) Inventor Motoyasu Tsunoda             1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture             Ceremony company Hitachi Systems Development Laboratory F term (reference) 5B025 AA01 AD04 AD05 AD08 AE05                 5B060 CB04

Claims (14)

[Claims] 1. A data read process for reading and outputting data stored at an address designated by a host, and a data write process for writing designated write data at an address designated by the host. In the memory device, when executing the data write process, if the data stored in advance at the address designated by the host and the write data designated by the host match,
A memory device in which the time required for data write processing is shorter than when the two data do not match. 2. A first memory, which takes a longer time to write data than a time to read a data, and a second memory, which has a shorter data read time and a shorter data write time than the first memory. The memory controller includes a memory controller that controls the first memory and the second memory, and the memory controller is the second memory when transmitting / receiving data between the host and the first memory. Is used as a buffer, and the write data specified by the host is used when the data write processing is executed,
Writing to the memory, reading data stored in advance at the address designated by the host from the first memory to the second memory, comparing two data of the second memory, and comparing the two data. If the data match,
The memory device according to claim 1, wherein a process of writing the write data in the first memory is omitted. 3. The memory device according to claim 2, wherein the memory control unit writes the write data in the first memory when the two data do not match. 4. The memory device according to claim 2, wherein the first memory, the second memory, and the memory control device are all formed on one chip. 5. The first memory is configured on one chip,
The memory device according to claim 2, wherein the second memory and the memory control device are formed on one chip, and the two chips are enclosed in one package. 6. The memory device according to claim 2, wherein the first memory, the second memory, and the memory control device are all configured on different chips, and the three chips are enclosed in one package. 7. The memory device according to claim 2, wherein the first memory is a flash memory. 8. A data read process for reading and outputting data stored at an address designated by a host and a data write process for writing designated write data at an address designated by the host can be executed. In the memory device, when the data write processing is executed, when the data stored at the address specified by the host has a specific value, the data is different from the case where the data has a value other than the specific value. A memory device that requires less time for write processing. 9. The time required to write data is longer than the time required to read data, and when writing data, the process of initializing the data of the address to the specific value in advance is performed before writing the data. And a first memory to be executed, a second memory having a shorter data read time and a shorter data write time than the first memory, and a memory control unit for controlling the first memory and the second memory. The memory control unit uses the second memory as a buffer when transmitting and receiving data between the host and the first memory, and when the data write process is executed, The first of the addresses specified by the host
A memory device that determines whether or not the data in the memory has the specific value and omits the process of initializing the first memory when the data has the specific value. 10. The memory device according to claim 9, wherein the specific value is a value in which all bits are 1. 11. The memory device according to claim 9, wherein the first memory, the second memory, and the memory control device are all formed on one chip. 12. The first memory is configured on one chip, the second memory and the memory control device are configured on one chip, and the two chips are enclosed in one package. The memory device according to. 13. The memory device according to claim 9, wherein the first memory, the second memory, and the memory control device are all configured on different chips, and the three chips are enclosed in one package. 14. The memory device according to claim 9, wherein the first memory is a flash memory, and the process of initializing the first memory is an erasing process of the flash memory.