JP3464048B2 - Multi-channel processing microprogram control circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-channel processing microprogram control circuit for a processor which performs multichannel processing by the same microprogram while switching channels in the middle of a program.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration example of a conventional multi-channel processing microprogram control circuit (a part of a processor).

This multi-channel processing microprogram control circuit saves a value (program address) of a program counter 7 which will be described later, in a LIFO (Last In First).
Out) stack 2, a channel register 5 indicating the channel being processed, an adder 4 that increments the value stored in the channel register 5 by 1, and an address that selects a program address to be processed in the next machine cycle by a sequence. Selector 6, adder 8 for adding 1 to the program address being processed, program counter 7 for holding the value after the addition, microprogram storing ROM 9, and instruction register for storing the program being processed 10 and a decoder 11 that creates a control signal from the value of the instruction register 10 to the arithmetic unit and the like.

In a normal sequence, the address selection means 6 uses the partially stored value of the instruction register 10 or the decoder 11.
The output value of the program counter 7, which is obtained by adding 1 to the program address being processed, is selected based on the partial decoded value from, and the ROM 9 causes the address selecting means 6 to select the output value.
Outputs the program stored in the selected program address, the instruction register 10 reads the program output from the ROM 9 at the start of the next machine cycle, increments the program address processed by the adder 1 by one, and increments the program counter. Hold at 7.

In the jump sequence, the address selecting means 6 selects the output value of the instruction register 10 indicating the program address of the jump destination based on the partially stored value of the instruction register 10 or the partially decoded value from the decoder 11. And set it as the program address of the next machine cycle.

In the sequence of calling a subroutine,
In addition to the jump operation, the value of the program counter 7 is pushed onto the stack 2. In the sequence of returning (RET), the address selecting means 6 selects the top value of the stack 2 and sets it as the program address of the next machine cycle. At this time, the stack 2 performs the pop operation.

A processor including such a microprogram control circuit has a plurality of input / output channels, and an input / output channel or a flag is selected by a channel register 5 indicating a channel being processed. In the following, it is assumed that the number of channels is N and the channels are divided by numbers from 0 to (N-1). Normally, the adder 4 outputs a value obtained by adding 1 to the input, but outputs 0 when (N-1) is input.

Here, let us consider processing the 1-channel processing (which is an example) shown in FIG. 3 with N channels. In the case of multi-channel processing, the micro-program storing ROM 9 stores a multi-channel processing micro program. Here, the pre-requisite micro program for one channel is shown in FIG.

First, the processing itself for one channel shown in FIG. 3 will be described. When a series of processes is started (F1), the contents of the flag are confirmed (F2). If the flag is 1, the subroutine SA1 is called, the subroutine process SA1 is executed, then the process returns to the main routine, the subroutine SA2 is called, and the subroutine process S is executed.
After executing A2, the process returns to the main routine to end the series of processes (F3 to F9). If the flag is 0, the subroutine SB1 is called and the subroutine processing S
After executing B1, the process returns to the main routine, further calls the subroutine SB2, executes the subroutine process SB2, and then returns to the main routine to end the series of processes (F3 to F9).

It is assumed that the processing for one channel is processed by N channels under the following assumptions. It is assumed that each channel has the above-mentioned flag, and the flag does not change while the processor is performing processing. Note that the flags are given from the outside and are held in a portion not shown in FIG. 2, and correspond to the input / output channels. Further, the subroutines SA1 and SB1 have higher processing priority than the subroutines SA2 and SB2, and the subroutines SA1 and S1 are used for all channels.
Subroutine SA2 or SB2 is executed after B1 is completed.

By performing the multi-channel processing while switching the channels in the middle of the program, it is possible to perform the real-time processing for a plurality of input / output channels. Also, when the data transfer rate of the device connected to the I / O channel is slow, the waiting time of the processor can be shortened by performing multi-channel processing while switching channels in the middle of the program.
The overall processing time can be shortened. Furthermore, it is possible to perform different processing for each channel by conditional branching.

FIG. 4 is a flowchart showing a multi-channel processing microprogram stored in the microprogram storing ROM 9 shown in FIG. 2, which is formed based on the processing microprogram for one channel shown in FIG.
The microprogram of FIG. 4 is naturally formed in consideration of the configuration shown in FIG.

CH (hereinafter referred to as channel parameter) is an output value of the channel register 5 which indicates the channel being processed. Also, the flag [CH] indicates a flag of the channel defined by the channel parameter CH.

Assuming that the flag [0] is 1 and the flag [1] is 0, the flowchart of FIG. 4 will be described with reference to FIG.

The program is started by setting the channel parameter CH to 0 (F1). The processing of channel 0 is started. The condition is branched by the flag [0] (F2). For example,
The output of the channel register 5 reads the value of the holding register (not shown) for the channel flag, and the condition is branched. Since the flag [0] is 1, the subroutine SA1 is called and the value of the program counter 7 is pushed onto the stack 2 (F3). The processing of the subroutine SA1 is performed (F4). When the processing of the subroutine SA1 is completed, the value of the top of the stack 2 becomes the program address of the next machine cycle by the RET (return) instruction, and the stack 2 performs the pop operation (F5). As a result, the channel parameter CH is incremented by 1
(F10). Since the channel parameter CH is 1, the process proceeds to the above-mentioned process F2 (F11).

Channel 1 processing is started. Flag [1]
The condition is branched by (F2). Flag [1] is 0, so
The subroutine SB1 is called and the value of the program counter 7 is pushed onto the stack 2 (F3). The processing of the subroutine SB1 is performed (F4). When the processing of the subroutine SB1 is completed, the top value of the stack 2 becomes the program address of the next machine cycle by the RET instruction, and the stack 2 performs the pop operation (F5). The channel parameter CH is incremented by 1 to 2 (F10). Since the channel parameter CH is 2, the process proceeds to the above-mentioned process F2 (F11).

Similarly, loop processing F2-F3-F4
-F5-F10-F11 are repeated to perform the processing of the subroutine SA1 or SB1 for all the channels.

Channel (N-1) subroutine SA1
Or, when the processing of SB1 is completed, the channel parameter C
H is set to 0 again (F10). Channel parameter CH
Is 0, the process proceeds to the next process F12 (F11).

The processing of channel 0 is restarted. Here, the condition is branched again by referring to the flag [0] (F12). Since the flag [0] is 1, the subroutine SA2 is called and the value of the program counter 7 is pushed onto the stack 2 (F6). Perform processing of subroutine SA2 (F
7). When the processing of the subroutine SA2 is completed, the value of the top of the stack 2 becomes the program address of the next machine cycle by the RET instruction, and the processing proceeds to the next processing F13.
The stack 2 performs a pop operation (F8). The channel parameter CH is incremented by 1 to 1 (F13).
Since the channel parameter CH is 1, the above process F12
Proceed to (F14).

The processing of channel 1 is restarted. Here, the condition is branched again by referring to the flag [1] again (F12). Since the flag [1] is 0, the subroutine SB2 is called and the value of the program counter 7 is pushed onto the stack 2 (F6). Perform processing of subroutine SB2 (F
7). When the processing of the subroutine SB2 ends, the value of the top of the stack 2 becomes the program address of the next machine cycle by the RET instruction, the process proceeds to the process F13, and the stack 2 performs the pop operation (F8). The channel parameter CH is incremented by 1 to 2 (F13). Since the channel parameter CH is 2, the process proceeds to F12 (F
14).

Similarly, loop processing F12-F6-F
7-F8-F13-F14 are repeated to perform the processing of subroutine SA2 or SB2 for all channels.

Channel (N-1) subroutine SA2
Or, when the processing of SB2 ends, the channel parameter C
H is set to 0 again (F13). Channel parameter CH
Is 0, the process proceeds to the next process F9 (F14). Then, the series of programs ends (F9).

The multi-channel processing microprogram of FIG. 4 has increased processing over the one-channel microprogram of FIG. 3, that is, the processing increased by introducing the channel switching is processing F10, F11, F12,
F13 and F14. Therefore, each processing F10, F1
Assuming that each of 1, F12, F13, and F14 is one step, the number of processing steps increased by channel switching is (the number of channels × 5) steps in the entire processing. R for program storage by channel switching
The increase in the capacity of the OM9 is due to the increasing processes F10 and F.
There are at least 5 words, because there are 5 of 11, F12, F13 and F14.

In this program example, there is one conditional branch in the processing for one channel, but the more conditional branches there are, the more complicated the program structure is, and the branch is performed depending on the condition such as the operation result not being held. Since the number of channel switching increases, the number of processing steps required for channel switching and the program storage ROM 9
It is obvious that the capacity of 1 is greatly increased, and changing a program for processing one channel to a program for processing multiple channels becomes a complicated task.

[0025]

In the circuit having the above configuration, the number of processing steps increases due to channel switching and the processing capacity of the processor decreases, and the capacity of the program ROM increases and the amount of hardware increases. There is a problem that the cost reduction effect due to multi-channel processing is reduced, and that changing a program that processes one channel into a program that processes multiple channels is a complicated task and easily causes an error. was there.

The present invention minimizes an increase in the number of processing steps due to channel switching, and enables RO for program storage.
It is an object of the present invention to provide a multi-channel processing micro program control circuit having a simple structure that can minimize the increase in the capacity of M and easily create a program for processing multiple channels.

[0027]

A multi-channel processing microprogram control circuit of the present invention has a channel register whose stored value is changed each time the processing of one channel is completed, and the channel is changed according to the value of the channel register. In a processor that performs multi-channel processing by the same microprogram while switching between, the stack for each channel is provided as a stack for saving the program address by the program counter, and the stack of the channel is selected according to the value of the channel register to Stack selection means for pushing or popping addresses is provided, and multi-channel processing is executed by repeating the operation of giving a program address from the top of the stack of channels to be switched each time the channels are switched. A.

[0028]

According to the present invention, a stack for each channel is prepared as a stack for saving the program address, and the stack selecting means selects the stack for each channel according to the value of the channel register that appropriately changes the channel instruction value, and pushes or pops. By operating it, it is possible to perform multi-channel processing with a hardware configuration that is as simple as possible, and with the same micro program that has a minimum number of steps that is as close as possible to the micro program for one channel.

[0029]

【Example】

(A) First Embodiment Hereinafter, a first embodiment of a multi-channel processing microprogram control circuit according to the present invention will be described in detail with reference to the drawings.
Here, FIG. 1 shows the configuration of the microprogram control circuit of the first embodiment, and the same or corresponding portions as those in FIG. 2 described above are designated by the same reference numerals.

As is clear from the comparison between FIGS. 1 and 2,
The microprogram control circuit of the first embodiment is different from the conventional microprogram control circuit in that (1) each channel is a stack of a LIFO structure for saving the value of the program counter 7 at the start of subroutine processing. (2) Push stack selection means for pushing the value of the program counter 7 to the stack 2- [CH] corresponding to the value (channel parameter) CH stored in the channel register 5 Point 1 is provided,
(3) Stack 2- [CH] according to channel parameter CH
Of the output stack selecting means 3 for selecting the top value of the above and outputting it to the address selecting means 6, and (4) R
The difference is that the stack 2- [CH] selected at the time of the ET instruction is pop-operated. The stack 2- [CH] for each channel may be of any level as long as it has one level or more.

Next, the operation of the multi-channel processing microprogram control circuit of the first embodiment will be described in correspondence with the operation of the other parts of the processor (not shown).

Also here, the description will be made assuming that the microprogram considering only the processing for one channel is the one shown in FIG. 3 described above.

Considering the hardware configuration of the multi-channel processing microprogram control circuit of the first embodiment, FIG.
The microprogram for performing the processing for one channel shown in (1) by N channels, that is, the microprogram stored in the microprogram storing ROM 9 is as shown in FIG. 5, for example. FIG. 6 is a flow chart showing the flow of processing when the microprogram shown in FIG. 5 is executed.

Hereinafter, assuming that the flag [0] is 1 and the flag [1] is 0, the flow of the process shown in the flowchart of FIG. 6 will be sequentially described with reference to FIG.

First, stacks 2- [0] to 2 of all channels
-At the top of [N-1], the start address of the program (the address of the process F2 in FIG. 5) is input, the channel parameter CH is set to 0, and the process is started (F1).

As a result, channel 0 processing is started. A conditional branch based on the flag [0] is performed (F2).
Since the flag [0] is 1, the value of the program counter 7 (the address of the main routine at the time of return; flag [0] is called in the stack 2- [0] while calling the subroutine SA1.
= 1 for processing F6 address) is pushed (F
3). The processing of the subroutine SA1 is performed (F4). When the processing of the subroutine SA1 is completed, the channel parameter CH is incremented by 1 to 1 (F1
0), execute the RET instruction, which causes stack 2
-The top value of [1] becomes the program address of the next machine cycle, the process proceeds to F2, and the stack 2- [1] performs a pop operation (F5).

As a result, the processing of channel 1 is started. A conditional branch is performed based on the flag [1] (F2).
Since the flag [1] is 0, the value of the program counter 7 (the address of the main routine at the time of return; flag [1] is called on the stack 2- [1] when the subroutine SB1 is called.
= 0 processing address of F6) is pushed (F
3). The processing of the subroutine SB1 is performed (F4). When the processing of the subroutine SB1 is completed, the channel parameter CH is incremented by 1 to 2 (F1
0), RET instruction is executed, which causes stack 2-
The top value of [2] becomes the program address of the next machine cycle, the process proceeds to F2, and the stack 2- [2] performs a pop operation (F5).

Thereafter, the loop processing F2-F3 is similarly performed.
-F4-F10-F5 are repeated to perform the processing of the subroutine SA1 or SB1 for all the channels.

Channel (N-1) subroutine SA1
Or, when the processing of SB1 is completed, the channel parameter C
After setting H to 0 again (F10), execute the RET instruction,
As a result, the value at the top of stack 2- [0] becomes the program address for the next machine cycle, and stack 2- [0]
Pops (F5).

The processing of channel 0 is restarted. Stack 2
-Since the stored value of [0] is the address of the process F6 related to the flag 1, the value of the program counter 7 (the address of the main routine at the time of return; The address of the process F9) is pushed (F6). The processing of the subroutine SA2 is performed (F7). When the processing of the subroutine SA2 ends, the channel parameter CH is incremented by 1 to 1 (F13), and then the RET instruction is executed, whereby the top value of the stack 2- [1] (the processing relating to the flag 0) The address of F6) becomes the program address of the next machine cycle, and the stack 2- [1] performs a pop operation (F8).

The processing of channel 1 is restarted. At the same time as calling the subroutine SB2, the value of the program counter 7 (address of main routine at return; address of process F9) is pushed onto the stack 2- [1] (F6).
The processing of subroutine SB2 is performed (F7). When the processing of the subroutine SB2 is completed, the value CH stored in the channel register 5 is incremented by 1 to 2 (F1
3), the RET instruction is executed, and the stack 2-
The top value of [2] becomes the program address of the next machine cycle, and stack 2- [2] pops (F
8).

Thereafter, in the same manner, loop processing F6-F7 is performed.
-F13-F8 are repeated to perform the processing of subroutine SA2 or SB2 for all channels.

Channel (N-1) subroutine SA2
Or, when the processing of SB2 ends, the channel parameter C
H is set to 0 again (F13). By the subsequent RET instruction, the top value of stack 2- [0] becomes the program address of the next machine cycle, and stack 2- [0] performs a pop operation (F8). The stored value of the stack 2- [0] at this time is the address of the process F9, and the series of programs ends (F9).

In the multi-channel processing microprogram shown in FIG. 5, the processing that increases more than the processing for one channel (see FIG. 3) due to channel switching is processing F10 and F13. One of these processes F10 and F13 occurs once every time the channel is switched, so the process F1
If 0 and F13 are each one step,
By performing the multi-channel processing shown in FIG.
The number of processing steps that is greater than that of performing the processing of (1), that is, the number of processing steps that increases with channel switching is (the number of channels × 2) steps.

In the multi-channel processing shown in FIG. 5, the required capacity of the ROM 9 for storing the micro program is increased by only one word of the instruction for incrementing the channel parameter CH for each processing for switching the channel, and the entire program. 4 words (each word is
F10 related to flag 0, F10 related to flag 1, F13 related to flag 0, and F13 related to flag 1).

In this multi-channel processing, the change from the program for one channel is that an instruction to increment the channel parameter CH is inserted before the RET instruction of the subroutine for switching channels.

As described above, the first embodiment is characterized in that the stack 2- [CH] is provided for each channel, and the microprogram shown in FIG. 6 is an example, and the present invention is not limited to this. Other multi-channel processing micro programs may be stored in the micro program storing ROM 9, and the micro program describes the processing for switching channels by a subroutine and inserts an instruction to increment the channel parameter CH before the RET instruction. All you have to do is do it.

The microprogram stored in the microprogram storing ROM 9 will be described below with some additional explanation.

In the microprogram shown in FIG. 5, there is one conditional branch. However, even if the program configuration becomes complicated due to more conditional branches, or the branch is performed due to a condition such as an operation result not being held, channel switching is performed. There is no increase in the number of processing steps and the capacity of the program storing ROM due to, and a program for processing one channel can be easily replaced with a program for processing multiple channels.

In the example shown in FIG. 5, the channel is switched by the subroutine called from the main routine, but the channel may be switched by the subroutine further called from the subroutine.

In the example shown in FIG. 5, the channel parameter C
Although the initial value of H is set to 0 and incremented by 1, the initial value of the channel parameter CH and the channel parameter CH can be switched freely.

In the example shown in FIG. 5, the stack 2- [CH] is pop-operated by the RET instruction, but when the stack is one level or data other than the top of the stack is empty, the pop-operation is not performed. Is also good. In such a case, under certain conditions, the channel parameter CH
Each time the channel is switched, the same subroutine processing is repeated every time the channel is switched, or the program is configured to push the start address of the subroutine to the top of the stack so that the processing of the same subroutine is repeated. It is possible to
The number of processing steps can be reduced.

Therefore, according to the first embodiment, since the stack 2- [CH] is provided for each channel, the process for switching the channel is described by a subroutine, and the stored value CH of the channel register is stored before the RET instruction. It becomes possible to perform multi-channel processing simply by inserting an instruction for incrementing, and it is possible to suppress a decrease in processing capacity due to channel switching and an increase in the capacity of the ROM 9 for storing microprograms, and it is possible to expect an improvement in quality of microprograms.

(B) Second Embodiment Next, a second embodiment of the multi-channel processing microprogram control circuit according to the present invention will be described in detail with reference to the drawings.
Here, FIG. 7 shows the configuration of the microprogram control circuit of the second embodiment, and the same or corresponding portions as those in FIG. 1 described above are designated by the same reference numerals.

The microprogram control circuit of the second embodiment is provided with a NEXT instruction for performing the operation of incrementing the channel parameter CH by 1 and the operation of the RET instruction in one machine cycle. That is,
The adder 4 in the second embodiment has a value (CH + 1) obtained by incrementing the channel register 5 by 1 at the time of the NEXT instruction.
To indicate the channel to be processed next, and the output stack selection means 3 of the second embodiment uses the adder 4
Is input and the top of the stack 2- [CH + 1] is selected and output to the address selecting means 6. Each stack 2- [CH + 1] of the second embodiment is pop-operated at the time of the NEXT instruction.

The adder 4 outputs 0 as the channel parameter CH when (N-1) is input as the channel parameter CH at the time of the NEXT instruction. Further, since the adder 4 outputs the input channel parameter CH as it is at the time of the RET instruction, the RET instruction can also be used.

Next, the operation of the multi-channel processing microprogram control circuit of the second embodiment will be described in correspondence with the operation of a processor (not shown).

Here again, it is assumed that the microprogram considering only the processing for one channel is the one shown in FIG. 3 described above. Considering the hardware configuration of the multi-channel processing micro program control circuit of the second embodiment, a micro program in which the processing for one channel shown in FIG. 3 is processed by N channels, and therefore stored in the ROM 9 for storing the micro program. As the generated microprogram, for example, the one shown in FIG. 8 is suitable. FIG. 9 is a flow chart showing the flow of processing when the microprogram shown in FIG. 8 is executed.

Hereinafter, assuming that the flag [0] is 1 and the flag [1] is 0, the process shown in the flowchart of FIG. 9 is executed by executing the microprogram of FIG. 8 with reference to FIG. 7. Explain the flow.

First, stacks 2- [0] to 2 of all channels
-At the top of [N-1], the start address of the program (address of the process F2 in FIG. 8) is input, the channel parameter CH is set to 0, and the process is started (F1).

As a result, channel 0 processing is started. A conditional branch is performed according to the flag [0] (F2). Since the flag [0] is 1, the subroutine SA1 is called and the value of the program counter 7 (NE
The address of the main routine at the time of return by the XT instruction; the address of the process F6 related to flag = 1) is pushed (F3). Perform processing of subroutine SA1 (F
4). When the processing of the subroutine SA1 is completed, NEX
By the T instruction, the channel parameter CH is incremented by 1 and becomes 1, the top value of the stack 2- [1] becomes the program address of the next machine cycle, and the stack 2- [1] performs the pop operation (F15).

The processing of channel 1 is started. Flag [1]
A conditional branch is performed (F2). Since flag [1] is 0, call subroutine SB1 and stack 2
-The value of the program counter 7 (the address of the main routine at the time of return by the NEXT instruction; the address of the process F6 related to flag = 0) is pushed to [1] (F3). The processing of the subroutine SB1 is performed (F4). When the processing of the subroutine SB1 is completed, the channel parameter CH is incremented by 1 to 2 by the NEXT instruction, the top value of the stack 2- [2] becomes the program address of the next machine cycle, and the stack 2- [2] becomes The pop operation is performed (F15).

Thereafter, the loop processing F2-F3 is similarly performed.
-F4-F15 are repeated to perform the processing of subroutine SA1 or SB1 for all channels.

Channel (N-1) subroutine SA1
Or, when the processing of SB1 is completed,
Channel parameter CH becomes 0 again and stack 2-
The top value of [0] becomes the program address of the next machine cycle, and the stack 2- [0] pops (F1
5).

As a result, the processing of channel 0 is restarted. Call subroutine SA2 and stack 2
-The value of the program counter 7 (the address of the main routine at the time of return by the NEXT instruction; the address of the process F9) is pushed to [0] (F6). Subroutine SA2
Is performed (F7). When the processing of the subroutine SA2 is completed, the channel parameter CH is incremented by 1 to 1 by the NEXT instruction, and the stack 2-
The top value of [1] becomes the program address of the next machine cycle, and stack 2- [1] pops (F1
6).

As a result, the processing of channel 1 is restarted.
Call subroutine SB2 and stack 2- [1]
The value of the program counter 7 (the address of the main routine at the time of returning by the NEXT instruction; the address of the process F9) is pushed to (F6). The processing of subroutine SB2 is performed (F7). When the processing of the subroutine SB2 is completed, the channel parameter CH is issued by the NEXT instruction.
Is incremented by 1 to become 2, the value at the top of stack 2- [2] becomes the program address of the next machine cycle, and stack 2- [2] performs a pop operation (F16).

In the same manner, loop processing F6-F7-
F16 is repeated to perform the processing of subroutine SA2 or SB2 for all channels.

Channel (N-1) subroutine SA2
Or, when the processing of SB2 is completed,
Channel parameter CH becomes 0 again and stack 2-
The top of [0] becomes the program address of the next machine cycle, and stack 2- [0] pops (F1
6). This ends the series of programs (F
9).

In the multi-channel processing shown in FIG. 8, there is no increase in processing steps due to channel switching as compared with the one-channel processing (see FIG. 3). Further, in the multi-channel processing shown in FIG. 8, the capacity of the program storage ROM 9 does not increase (see FIG. 3).

In this multi-channel processing, the only change from the program for one channel is to rewrite the RET instruction of the subroutine for switching channels to the NEXT instruction.

As described above, according to the second embodiment,
Stack 2- [CH] is provided for each channel, and the operation to increment the channel parameter CH and stack 2- [CH
Since the NEXT instruction which performs the operation of setting the top of [+1] as the program address of the next machine cycle and the pop operation of stack 2- [CH + 1] in one machine cycle is introduced, one channel is processed. To change from a program to a program for processing multiple channels, it is sufficient to describe the processing for switching channels in a subroutine and replace the RET instruction with a NEXT instruction. Compared with the first embodiment, the processing capability by channel switching is further increased. Can be suppressed and the capacity of the ROM for storing the program can be suppressed, and the quality of the program can be improved.

It is necessary to add a hardware function in order to realize the NEXT instruction.

(C) Third Embodiment Next, a third embodiment of the multi-channel processing microprogram control circuit according to the present invention will be described in detail with reference to the drawings.
Here, FIG. 10 shows the configuration of the microprogram control circuit of the third embodiment, and the same or corresponding portions as those in FIG. 1 described above are designated by the same reference numerals.

The difference between the microprogram control circuit of the third embodiment and the microprogram control circuit of the first embodiment will be mainly described.

The microprogram control circuit of the third embodiment has a stack area (hereinafter referred to as a common stack) 2 common to each channel and a stack for each channel as a stack having a LIFO structure for saving the value of the program counter 7. Stack area (hereinafter called stack top) 12- [CH]
Have and. Stack top of each channel 12- [CH]
Stores the top level address, and the other level addresses are stored in the common stack 2. In order to enable switching of the stack area according to such a level, the stack area switching means 13 for switching only the stack top 12- [CH] according to the channel to be processed is provided.

Therefore, when the microprogram control circuit according to the third embodiment is applied, it is possible to easily deal with a microprogram in which a subroutine is further called during a series of processes related to the same channel. Also, if the program is configured so that the channel is switched only by the subroutine called from the main routine, it is possible to store the program address that needs to be held only in the stack top 12- [CH] and switch the channel.

When the microprogram considering only the processing for one channel is the one shown in FIG. 3 described above, the multichannel processing considering the multichannel processing microprogram control circuit of the third embodiment. The micro program for use is, for example, as shown in FIG. 5, as in the first embodiment, and the flow of processing when executing the micro program is also as shown in FIG.

As described above, according to the third embodiment, as the stack for saving the value of the program counter 7, the common stack 2 common to each channel and the stack top 12- [CH] for each channel are provided. Since this is provided, the amount of hardware can be further reduced compared to the first embodiment. That is, considering that the microprogram considering only the processing for one channel has a nested structure of subroutines, the stack 2- [CH] for each channel in the first embodiment must be set to two levels or more,
If the number of levels is 3 or more, the configuration of the third embodiment is simpler.

(D) Other Embodiments The third embodiment described above is a modification of the first embodiment, but the characteristics of the third embodiment are applied to the second embodiment. May be. That is, the stack 2- [CH] portion for each channel in the second embodiment may be replaced with the common stack 2, the stack top 12- [CH] for each channel, and the stack area switching means 13. good.

In the first and second embodiments, addresses of all levels are stored in the stack 2- [CH] for each channel, and in the third embodiment, top level addresses are stored. Stack for each channel 12- [C
However, it is also possible to provide an arbitrary area of the stack for each channel and switch the area according to the channel so that the remaining stack area is shared by all the channels. However, if the program address that needs to be stored is stored in the stack area shared by all channels and the channel is switched, this value may be lost. Therefore,
The program address that needs to be retained must be stored in a stack area provided for each channel and the program must be configured so as to switch the channel so that the necessary program address is not lost.

[0081]

As described above, according to the multi-channel processing microprogram control circuit of the present invention, a stack for each channel is prepared as a stack for saving the program address, and the value of the channel register for appropriately changing the channel indication value is set. According to the above, the stack selecting means selects the stack for each channel to perform the push operation or the pop operation. Therefore, the same micro program with a simple hardware configuration and a few steps as close as possible to the micro program for one channel is used. Multi-channel processing can be performed by a program.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a block diagram of a conventional example.

FIG. 3 is a processing flowchart for one channel.

FIG. 4 is a flowchart of a conventional multi-channel processing program.

FIG. 5 is a flowchart of a multi-channel processing program according to the first embodiment.

FIG. 6 is a flowchart showing a flow of processing at the time of execution of FIG.

FIG. 7 is a block diagram of a second embodiment.

FIG. 8 is a flow chart of a program for multi-channel processing of the second embodiment.

9 is a flowchart showing the flow of processing at the time of execution in FIG.

FIG. 10 is a block diagram of a third embodiment.

[Explanation of symbols]

1 ... Push stack selecting means, 2 ... Common stack area, 2- [CH] ... Channel-by-channel stack, 3 ... Output stack selecting means, 4 ... Channel parameter CH increment adder, 5 ... Channel register, 6 ... Address selection Means, 7 ... Program counter, 8 ... Adder for adding 1 of program address, 9 ... R for storing microprogram
OM, 10 ... Instruction register, 11 ... Decoder, 12- [C
H] ... Stack area for each channel, 13 ... Stack area switching means.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-56-79325 (JP, A) JP-A-54-133853 (JP, A) JP-A-60-122450 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 13/12 310 G06F 9/22-9/26

Claims (3)

(57) [Claims] 1. A processor having a channel register whose stored value is changed each time the processing of one channel is completed, and performing multi-channel processing by the same microprogram while switching channels according to the value of this channel register, A stack for each channel is provided as a stack for saving the program address by the program counter, and a stack selecting means for selecting the above stack of the channel according to the value of the above channel register and pushing or popping the program address is provided. A multi-channel processing microprogram control circuit characterized in that multi-channel processing is executed by repeating an operation of giving a program address from the top of a stack of channels to be switched each time switching is performed. 2. A storage value of the channel register is updated by an adder for incrementing by 1, and the stack selecting means selects the stack to be pushed according to an output value from the channel register. At the same time, the stack to be pop-operated according to the output value of the adder given to the channel register is selected, and the operation of switching the channel and the pop-operation of giving the program address from the top of the stack of the channel to be switched are performed in one machine cycle. A multi-channel processing microprogram control circuit as claimed in claim 1, characterized in that: 3. An individual stack area for each channel and a common stack area common to all channels are provided in place of the stack for each channel, and the individual stack area is switched by the stack selection means in accordance with the channel to be processed and is common. 3. The multi-channel processing microprogram control circuit according to claim 1, wherein the stack selection means is used so that the stack area is shared by all channels.