JP3455997B2 - Data processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for handling digital data, for example, a data processing device suitable for use in a data reproducing system such as a digital audio tape recorder device, a digital video tape recorder device, and a digital communication device. In particular, the present invention relates to a data processing device that reduces the memory required for performing interpolation processing and mute processing based on the result of error correction.

[0002]

2. Description of the Related Art Conventionally, for example, in a device that handles voice information digitally, voice data is formed by digitizing analog voice information by an A / D converter, and so-called interleave processing is performed on the voice data. Give. Then, for example, 8 bits are used as one symbol in the audio data that has been subjected to this interleave processing.
An error correction code of 4 symbols (3
2.28 = C1 code) is added (total 32 symbols) and recorded or output to the outside.

A conventional data processing device for reproducing such audio data has a structure as shown in FIG.
In FIG. 2, the audio data is supplied to the error correction circuit 51 via the input terminal 50.

The error correction circuit 51 performs error correction processing (C1 processing) on the voice data for every 28 symbols based on the error correction code of 4 symbols. Then, the audio data after error correction is supplied to the deinterleave processing circuit 52, and the C1 processed data indicating the C1 processing result is C
The data is supplied to the 1-processing memory 57, an error flag is set for the audio data that cannot be error-corrected, and this is supplied to the error flag memory 55.

The C1 processing data is temporarily stored in the C1 processing memory 57 under the write control of the memory controller 58. The error flag is temporarily stored in the error flag memory 55 under the write control of the memory controller 56.

The deinterleave processing 52 applies deinterleave processing to the voice data after the error correction,
This is supplied to the interpolation processing circuit 53.

The memory controller 56, at the timing when the audio data is supplied to the interpolation processing circuit 53,
The error flag stored in the error flag memory 55 is read out and supplied to the interpolation processing circuit 53. When the error flag is supplied, the interpolation processing circuit 53 supplements the audio data that could not be error-corrected by interpolation processing and supplies it to the mute processing circuit 54.

The memory controller 58 reads the C1 processing data stored in the C1 processing memory 57 at the timing when the audio data is supplied to the mute processing circuit 54, and supplies it to the mute processing circuit 54. The mute processing circuit 54 determines whether the audio data can be interpolated by the interpolation processing in the interpolation processing circuit 53 based on the C1 processed data. When it is determined that the interpolation is possible, the audio data is output to the outside via the output terminal 59. If it is determined that interpolation is impossible, muting is performed so that the audio data is not output.

Thus, it is possible to prevent inaccurate voice data from being output and to output only correct voice data.

[0010]

In order to perform the interpolation process and the mute process, the error flag and the C1 process data are set at the timing when the audio data is supplied to the interpolation process circuit 53 and the mute process circuit 54. Each circuit 5
It is necessary to supply to 3,54. Therefore, the conventional data processing apparatus includes an error flag memory 55 that stores the error flag, a memory controller 56 that controls writing and reading of the error flag memory 55, and a C1 processing memory 5 that stores the C1 processing data.
7. It is necessary to provide a memory controller 58 for controlling writing and reading of the C1 processing memory 57,
There was a problem that the number of parts increased and the cost increased.

The problem is that the larger the amount of data handled in one data processing, the longer the time required for the error correction processing, the deinterleave processing, the interpolation processing and the like. Therefore, the storage capacity of the error flag memory 55 and the C1 processing memory. 57
It is necessary to increase the storage capacity of the device, which becomes more remarkable.

The present invention has been made in view of the above-mentioned problems, and even if the error flag memory 55, the memory controller 56, the C1 processing memory, and the memory controller 58 are not provided, the interpolation processing is performed at the matched timing,
An object of the present invention is to provide a data processing device that can perform mute processing and can reduce costs by reducing the number of parts.

[0013]

A data processing apparatus according to the present invention outputs error-correction-processed digital data based on the error-correction code to digital data to which an interleave process has been applied and an error-correction code is added. Error correction means for setting and outputting an error flag for digital data that could not be corrected, and digital data that has not been error-corrected based on the error flag from the error correction means are detected, and the error correction is performed. Error code converting means for converting all the digital data that could not be converted into a predetermined error code and outputting this error code together with the error-corrected digital data, and the digital data and error code from the error code converting means. Deinterleaving means for performing deinterleaving processing on the Error code detection means for detecting the error code from the digital data and the error code supplied from the processing means and outputting an error code detection signal; and based on the error code detection signal from the error code detection means, Among the digital data and the error code from the deinterleave processing means, the error code is interpolated to form accurate digital data, and the interpolation means is provided for outputting together with the digital data, thereby solving the above-mentioned problems. To do.

Further, the data processing apparatus according to the present invention counts the number of error codes within a predetermined time based on the error code detection signal from the error code detecting means, and the count value becomes a predetermined value or more. And a mute signal output unit for outputting a mute signal in response to the mute signal output unit, and a mute unit for performing a mute process on the digital data from the interpolation unit according to the mute signal from the mute signal output unit. Solve the problem.

Further, in the data processing apparatus according to the present invention, the error correction means performs error correction based on the Reed-Solomon code added to the digital data, and the mute signal output means detects the error code. Based on the error code detection signal from the means, the number of error codes within a predetermined time is counted to predict the error correction processing result in the error correction means and output a mute signal. To solve.

[0016]

In the data processing apparatus according to the present invention, when the interleave processing is performed and the digital data to which the error correction code such as the Reed-Solomon code is added is supplied, the error correction means is based on the Reed-Solomon code. Error correction processing of the digital data is performed, and the error-corrected digital data is supplied to the error code conversion means, and an error flag is set for the digital data that has not been error-corrected, and the error data is converted to the error code conversion means. Supply.

The error code conversion means detects digital data that has not been error-corrected based on the error flag from the error correction means, and converts all digital data that has not been error-corrected into a predetermined error code. Then, this error code is supplied to the deinterleaving means together with the digital data that has been subjected to the error correction processing.

The deinterleaving means performs deinterleaving processing on the digital data and the error code from the error code converting means and supplies them to the error code detecting means.

The error code detecting means detects the error code from the digital data and the error code supplied from the deinterleave processing means, forms an error code detection signal, and supplies this to the interpolating means.

The interpolation means performs an interpolation process on the error code of the digital data and the error code from the deinterleave processing means based on the error code detection signal from the error code detection means to obtain accurate digital data. Are formed and output together with the digital data.

The error code converting means converts all the digital data that cannot be corrected by the error correcting means into a predetermined error code. Therefore, the error code from the deinterleave means is interpolated. The error code detection signal from the error code detecting means can be supplied to the interpolating means at the timing of being supplied to the means.

Therefore, the error flag from the error correction means is temporarily stored in the memory, and the error flag is not read from the memory and supplied to the interpolation means at the timing when the digital data is supplied to the interpolation means. However, the interpolation process can be performed at the timing when the digital data (error code) that could not be subjected to the error correction is supplied to the interpolation means.

Therefore, the memory that temporarily stores the error flag and the memory controller that controls writing and reading of the memory can be omitted.

Next, in the data processing apparatus according to the present invention, the mute signal output means counts the number of error codes within a predetermined time based on the error code detection signal from the error code detection means, and this count is performed. A mute signal is supplied to the mute means when the value exceeds a predetermined value.

That is, when the count value is equal to or greater than the predetermined value, it means that there are many digital data that cannot be error-corrected by the error correction means, and the interpolation means cannot perform accurate interpolation processing. Is shown. Therefore, the error correction processing result in the error correction means is predicted by counting the number of error codes. Then, the mute signal is supplied to the mute means when the count value exceeds a predetermined value.

When the mute signal is supplied, the mute means mutes the audio data so as not to output it. As a result, it is possible to prevent incorrect audio data from being output.

Further, since the mute signal is output when the number of error codes is counted by the mute signal output means above a predetermined value, the digital data interpolated by the interpolation means is sent to the mute means. The mute signal can be supplied to the mute means at the supplied timing. Therefore, it is not necessary to store the error correction processing data, which is the data indicating the error correction processing result in the error correction means, in the memory and perform the mute processing based on the error correction processing data stored in the memory. A memory for storing correction processing data and a memory controller for controlling writing and reading of the memory can be omitted.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of a data processing apparatus according to the present invention will be described below with reference to the drawings. The data processing device according to the present invention is, for example, 16 bits or 12 bits.
The bits are digitized and subjected to interleaving processing, and a so-called Reed-Solomon code (32.28 = C1 code) of 4 symbols is added as a group of 28 symbols with 16 bits or 12 bits as one symbol and transmitted. The audio data is reproduced.

Specifically, as shown in FIG. 1, error correction (C1 processing) of voice data is performed based on the C1 code, and an error flag is set for the voice data which cannot be error-corrected and the voice data is output. The error correction circuit 1 and the voice data that has been subjected to error correction from the error correction circuit 1 are output as they are, and the voice data that cannot be subjected to the error correction is detected and coded (error code) based on the error flag. And an error code converter 2 for outputting.

The data processing apparatus outputs the deinterleave processing circuit 3 for deinterleaving the audio data from the error code converter 2 and the audio data from the deinterleave processing circuit 3 as they are, It has an error code detection circuit 4 for detecting the error code and outputting an error code detection signal, and an interpolation processing circuit 5 for interpolating the audio data based on the error code detection signal.

Further, the data processing apparatus predicts the C1 processing result in the error correction circuit 1 by counting the number of error codes from the error code detection signal from the error code detection circuit 4, and this counter value is A mute control circuit 7 that outputs a mute signal when the mute signal is equal to or more than a predetermined value, and a mute processing circuit 6 that performs a mute process so that audio data is not output when the mute signal is supplied from the mute control circuit 7.
And have.

Next, the operation of the data processing apparatus according to this embodiment will be described. First, for example, 16 bits (7FFF-8)
001: Hexadecimal display or 12 bits (7FF to 80)
The audio data, which has been digitized (1: hexadecimal display), subjected to interleave processing, and added with the C1 code, is supplied to the error correction circuit 1 via the data input terminal 8.

The error correction circuit 1 corrects the error of the voice data based on the C1 code, supplies the voice data to the error code converter 2, and corrects the voice data for which the error correction cannot be performed. An error flag is set and this is supplied to the error code converter 2.

The error code converter 2 supplies the audio data that has been able to perform the error correction processing to the deinterleave processing circuit 3 as it is, and the audio data that has not been error-corrected based on the error flag. The detected voice data that cannot be corrected is converted into an error code of 8000 (hexadecimal display) when the input voice data is 16 bits, and the input voice data is 12 bits. If it is, it is converted into an error code of 800 (hexadecimal display), and this is supplied to the deinterleave processing circuit 3.

The deinterleave processing circuit 3 performs deinterleave processing on the audio data from the error code converter 2 and supplies it to the error code detection circuit 4.

The error code detection circuit 4 supplies the voice data as it is to the interpolation processing circuit 5, and
An error code in the audio data is detected by detecting 8000 or 800, and an error code detection signal is supplied to the interpolation processing circuit 5 and the mute control circuit 7.

The interpolation processing circuit 5 performs interpolation processing on the audio data at the timing when the error code detection signal is supplied, and supplements the audio data that could not be error-corrected by the error correction circuit 1, and Mute processing circuit 6
Supply to.

In the data processing apparatus according to the present embodiment, the voice data that could not be error-corrected by the error correction circuit 1 is converted into an error code, the error code detection circuit 4 detects the error code, and the error code detection signal is interpolated. Processing circuit 5
Since the error code signal is supplied to the interpolation processing circuit 5, the error code signal can be supplied to the interpolation processing circuit 5 and the interpolation processing can be performed at the timing at which the audio data whose error cannot be corrected is supplied to the interpolation processing circuit 5. Therefore, an error flag memory for storing the error flag output from the error correction circuit 1 and writing of the error flag memory,
The memory controller that controls reading can be omitted.

On the other hand, the mute control circuit 7
Counts the number of error codes in units of interleave processing, for example, based on the error code detection signal from the error code detection circuit 4. Then, the mute signal is supplied to the mute processing circuit 6 when the count value exceeds a predetermined value.

That is, when the count value is equal to or larger than the predetermined value, it means that there are many audio data which cannot be error-corrected in the error correction circuit 1, and the interpolation processing circuit 5 can also perform accurate interpolation processing. It shows that there was not. Therefore, the C1 processing result is predicted by counting the number of error codes,
A mute signal is supplied to the mute processing circuit 6 when the count value exceeds a predetermined value.

When the mute signal is supplied, the mute processing circuit 6 mutes the audio data so that it will not be output.

This makes it possible to prevent incorrect audio data from being output. Further, since the mute signal is output when the number of error codes is counted by the mute control circuit 7 at a predetermined value or more, the audio data interpolated by the interpolation processing circuit 5 is output as the mute processing circuit 6. The mute signal is supplied to the mute processing circuit 6
Can be supplied to. Therefore, the C1 processing data indicating the C1 processing result in the error correction circuit 1 is stored in the C1 processing memory, and the C stored in the C1 processing memory is stored.
It is not necessary to perform the mute processing based on one processing data, and the C1 processing memory for storing the C1 processing data and the memory controller for controlling writing and reading of the C1 processing memory can be omitted.

As is clear from the above description, the data processing apparatus according to the present embodiment has an error flag memory for storing an error flag, a memory controller for controlling writing and reading of the error flag memory, and C
It is possible to omit the C1 processing memory that stores the C1 processing data indicating one processing result and the memory controller that controls writing and reading of the C1 processing memory. Therefore, the cost can be reduced by reducing the number of parts and simplifying the configuration.

In the above description of the embodiments, the data processing device according to the present invention handles audio data. However, if this is digital data such as video data or communication data, Anything is fine. Further, although the audio data to which the Reed-Solomon code is added is handled, any audio correction code may be used.

Although 16-bit and 12-bit voice data are handled, these are merely numerical values given for convenience of explanation. Therefore, it goes without saying that only 16 bits or only 12 bits may be handled, and 8 bits, 24 bits, 36 bits, etc. may be handled without departing from the technical idea of the present invention. It goes without saying that various modifications can be made if they exist.

[0046]

The data processing apparatus according to the present invention converts digital data that could not be error-corrected by the error correction means into an error code, detects the error code after deinterleave processing, and performs interpolation processing, Since the mute processing is performed, a memory that temporarily stores the error flag output from the error correction unit and a memory controller that controls writing and reading of the memory,
And a memory for storing error correction processing data which is data indicating an error correction processing result in the error correction means,
A memory controller that controls writing and reading of the memory can be omitted.

Therefore, by reducing the number of these components, the structure can be simplified and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a data processing device according to the present invention.

FIG. 2 is a block diagram of a conventional data processing device.

[Explanation of symbols]

1 ... Error correction circuit 2 ... Error code converter 3 ... ... Deinterleave processing circuit 4 Error code detection circuit 5 Interpolation processing circuit 6 ... Mute processing circuit 7 ... Mute control circuit 8 ...・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Data input terminal 9 ・ ・ ・ ・ ・ Data output terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-1-296460 (JP, A) Actual development Sho 60-93167 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11B 20/18

Claims (3)

(57) [Claims] 1. Digital data to which an interleave process has been applied and to which an error correction code has been added is subjected to error correction processing based on the error correction code and output, and an error flag for digital data that has not been error-corrected. And digital error data which cannot be error-corrected based on the error flag from the error-correction device and convert all the digital data which cannot be error-corrected into a predetermined error code. Error code conversion means for outputting the error code together with the digital data subjected to the error correction processing, deinterleaving means for deinterleaving the digital data and the error code from the error code conversion means, and the de-interleaving means. Digital data and error supplied from the interleave processing means Error code detecting means for detecting the error code from the error code and outputting an error code detecting signal; and digital data and error from the deinterleave processing means based on the error code detecting signal from the error code detecting means. Among the codes, the error code is subjected to interpolation processing to form accurate digital data, and an interpolation means for outputting together with the digital data is output, and a data processing device. 2. A mute which counts the number of error codes within a predetermined time based on an error code detection signal from the error code detection means and outputs a mute signal when the count value becomes equal to or larger than a predetermined value. 2. The data processing apparatus according to claim 1, further comprising a signal output unit and a mute unit for performing a mute process on the digital data from the interpolation unit according to a mute signal from the mute signal output unit. 3. The error correction means performs error correction based on the Reed-Solomon code added to the digital data, and the mute signal output means based on the error code detection signal from the error code detection means. 3. The data processing apparatus according to claim 2, wherein the number of error codes within a predetermined time is counted to predict the error correction processing result in the error correction means and output a mute signal.