JP3453980B2 - Identification signal processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an identification signal processing device for, for example, a second-generation high-definition television, and more specifically, in decoding an identification command having periodicity,
The present invention relates to an identification signal processing device that enables accurate decoding by including a storage unit for a period.

[0002]

2. Description of the Related Art In recent years, with the remarkable development of telecommunication technology, new media of wireless system and wired system have appeared one after another. A high-definition television (HDTV) with a high image quality and an aspect ratio of 16: 9, or a second-generation high-definition television (2nd generation) that realizes widening and high image quality while maintaining compatibility with current televisions. EDTV: Below, simply "E
"DTV-II") has also started broadcasting. The present invention is suitable for general application to video processing apparatuses, but as an example of video processing apparatus, EDTV-II that has reached a practical stage.
The receiver will be explained.

Regarding EDTV-II, BTA (Bro
Adcasting Technology Association: Broadcasting Technology Development Council) is considering adding "still image / film mode". For details of EDTV-II, see BTA, "2nd Generation EDTV System Study Report" issued on December 9, 1994, and "EDT-Mode" for still image / film mode.
A Study on Still Image / Film Mode Command in V-II "Television Engineering Society Technical Report ITE Technical R
Details are reported in eport Vol.19, No.17, PP.49-53 (Mar.1995).

An outline of the identification control signal of the EDTV-II according to the present invention will be described with reference to FIG. Figure 6 shows EDTV-
It is a figure which shows the outline | summary of the identification control signal of II, (a) is a figure which shows an identification control signal waveform, (b) is a figure which shows a bit position and identification content.

In FIG. 6A, the identification control signal used for automation of various controls on the receiver side is control information contained in the 22/285 line of each field, and is a horizontal synchronization signal Hsync (hereinafter , Simply described as “Hsync”) 1,
Color burst 2 consisting of a reference waveform of 9 cycles in π (radian) phase, NRZ (Non-Return Zero) 3 meaning 1/0 to which identification commands B1 to B5 are assigned, also "1" or "0" A color subcarrier in which the identification commands B6 to B23 are interpolated, which are defined as "1" if the information is modulated and have a phase opposite (0 phase) to the color burst 2 and "0" if the phase is the same (π phase). (Fsc) 4 and confirmation signal 5 composed of B25 to B27. The identification commands B1 to B23 are allocation numbers having a confirmation function for distinguishing from an existing video signal composed of 1 bit = 28 samples, and only B1 to B5 are NRZ waveforms in order to eliminate the influence of noise such as ghost. , And most of the rest is a modulated wave of the color subcarrier (fsc).

The confirmation signal 5 has a carrier frequency (4 / 7f).
sc) modulated 2.04 MHz period, ie 1
It is configured as a clock with a period of 7 samples. That is,
The phase of the subcarrier of (4/7 fsc) is extracted and used as the synchronization timing for decoding the reinforcement signal. Also, the identification command B1 assigned to NRZ3
B2 and B2 are fixed to "1" and "0", respectively, as references of the identification control signal.

FIG. 1B is a diagram showing the bit positions and identification contents as the mode identification information, which is made up of the bit number, the contents of the reference signal and the like, and the status storing the control information of 1/0. If a part of it is explained as the essential mode identification information, the letterbox B3 is the top priority necessary information for specifying the display format of the screen in the 16: 9 receiver, and the normal (4: 3) It is sometimes indicated by the status "0" and by letterbox (16: 9) by the status "1". The presence / absence of various reinforcement signals of B8 bit to B10 bit is necessary information for the purpose of preventing S / N deterioration in the absence of any reinforcement signal. The vertical temporal resolution enhancement signal VT of B8, the vertical high-frequency component VH of the luminance signal of B9, and the horizontal high-frequency component HH of the luminance signal of B10 (horizontal high: hereinafter simply referred to as "HH") have an aspect ratio (4: 3). ), The status is set to “0” without being multiplexed.

Information on the presence / absence of HH precombing of B11 is used when the horizontal resolution enhancement signal HH '(hereinafter simply referred to as "HH'") after frequency shift is multiplexed on the transmitting side without precombing, when the receiver On the side, this information gives H
This is important information because it is used for the purpose of stopping the demodulation of H ′ and preventing the crosstalk between the color signals C and HH. B18
6 bits of 23 to 23 are CRC (Cyclic Redund) for error correction.
ancy Check) code, which allows B3-23
1-bit error is corrected.

To explain the identification information according to the present invention in particular, B7 is an EDTV according to the VT and VH demodulation system.
-Frame A and frame B in the II encoder
(2 fields each) A total of 4 fields has a cycle of 1 cycle. Although B17 is undefined, it is currently considered to be "still image / film mode", and it is considered to send four patterns of information: still image, 24 frame film mode, 30 frame film mode, and normal signal depending on the video signal source to be sent. Has been done. If this is formally defined, the receiver will have to perform the appropriate scan line interpolation when it receives this mode. It should be noted that there are many uncertain factors in the diagram showing each bit position and the identification content, and may be adjusted in the future.

A specific example of the identification signal processing device of the EDTV-II receiver according to the present invention will be described with reference to FIG. FIG. 7 is a block circuit diagram showing an example of an identification signal processing device of an EDTV-II receiver according to the present invention.

The main configuration of the identification signal processing device in FIG. 7 is as follows: the input unit 6 and the video signal 22/22 of the video signal input to the input unit 6.
A bit decoding circuit 7 for detecting an identification command from the EDTV-II identification control signal superimposed on the 285 line, and an erroneous detection determination circuit 8 for determining whether or not the identification command detected by the bit decoding circuit 7 is correctly detected. A switch element 9 that selects an output value according to the false detection determination result c of the false detection determination circuit 8, a D-type flip-flop that outputs the value selected by the switch element 9 to the output unit 11 in response to the field clock a, etc. The output updating circuit 10 (hereinafter simply referred to as "D circuit") is generally configured.

The operation of the identification signal processing device of the EDTV-II receiver according to the present invention will be described.

The EDTV-II signal input to the input section 6 is input to the bit decoding circuit 7. In the bit decoding circuit 7, the identification commands B1 to B2 of the identification control signal (see FIG. 6B) superimposed on the input video signal.
3 is detected and output as the identification command detection value b. The identification command detection value b is each value of "1" and "0" of the 23 identification command bits B1 to B23. The erroneous detection determination circuit 8 inputs B1 to B23 of the identification command detection value b detected by the bit decoding circuit 7 and checks the detection result by using the check function inherent in the identification command detection value b. The check function included in the identification command is, for example, a parity check using the parity bit of B4 shown in FIG. 6B, a CRC check using the error correction code of B18 to B23, or the like. As a result of these checks, if even one is determined to be an error, the erroneous detection determination result c outputs a level indicating an error. As an example, the false detection determination result c is low level “L”.
Is normal, high level is “H”, false detection (error)
Shall be determined.

The switch element 9 is a bit decoding circuit 7
B1 to B23 of the identification command detection value b, which is the output of
B1 to B23 of the identification command output value d, which will be described later,
The selection is made in response to the error detection determination result c of the error detection determination circuit 8. That is, when the erroneous detection determination result c is determined to be "H" error, the identification command output value d is selected and "L" is selected.
If it is determined to be normal, the identification command detection value b of the bit decoding circuit 7 is selected. Output update circuit 10
Outputs the identification command value b or the like input in response to the rising edge of the field clock a as the identification command output value d to the output unit 11, and stores the output value until the next rising edge of the field clock a. That is, the input identification command value b is stored for a predetermined period and fed back to the error input side of the switch element 9. E
The DTV-II identification control signal is 22 / once per field.
It is a signal superimposed on 285H, and the detection result can be obtained once in a maximum of one field.

The decoding operation of the identification signal processing apparatus according to the present invention will be described with reference to the timing chart of FIG. 8 together with FIG. FIG. 8 is a diagram showing a decoding operation of the identification signal processing apparatus according to the present invention, (a) is a timing chart showing a normal identification command processing operation, and (b) is a timing chart.
FIG. 9 is a timing chart showing a processing operation of an identification command B7 having a periodic pattern.

In the operation example of the normal identification command of FIG. 8 (a), 22 / 285H is the line in which the identification control signal of the input video signal is present, and the identification is performed once for each field at this timing. The control signal decoding circuit operates. The field clock a is a timing pulse that rises once in the field in which the identification control signal is detected, and is the update timing of the output update circuit 10 in FIG. 7 and the output update timing of each identification command. Generated using. Then, the identification command detection value b is detected between the rising edge of 22 / 285H and the rising edge of the feed clock a, and the error detection determination circuit 8 makes an error detection determination during that time. The identification command detection value b in FIG. 8A indicates a general identification command switching timing for switching the broadcast mode. Further, the switch element 9 is activated by the erroneous detection determination result c of the erroneous detection determination circuit 8 in FIG. 7, and the output update circuit 10 outputs the identification command output value d. The ideal output value e in the figure is the ideal value of this output, and substantially matches the identification command output value d.

The state [A] in FIG. 8A is a case where the erroneous detection determination result c is "L" normal. Switch element 9
The identification command detection value b is selected by and is output to the identification command output value d at the timing of the field clock a.

Next, the state [B] is a case where the erroneous detection determination result c indicates "H" error. The identification command output value d is selected by the switch element 9 and output to the output unit 11 at the timing of the field clock a. That is, when the erroneous detection determination result c indicates an “H” error, the output update circuit 10 outputs the value stored in the previous value, so that the output value of the identification command output value d does not change. If the identification command detection value b is directly output to the output unit 11 without performing the previous value storage operation by the output update circuit 10, the identification command detection value b may include an error and the screen may There is a possibility of malfunction such as accidental switching. Therefore, the processing for storing the previous value is indispensable for the EDTV-II identification signal processing device.

However, when such a circuit processes an identification command having a periodic pattern such as B7, there is a possibility that the previous value cannot be saved normally. The reason will be described with reference to FIG.

In the operation example of the identification command B7 having the periodic pattern of FIG. 8B, the identification command B7 has a periodic pattern of one period in four fields as shown in the figure, and the output unit 11 outputs B7 ideally. Ideally, a value like the value f is output. State [A] in FIG. 8B
Indicates that the identification command detection result c is “L” normal, the identification command detection value b is selected by the switch element 9 as in FIG. 8A, and the identification command output value d is set at the timing of the field clock a. It is output to the output unit 11.

In the state [B], the erroneous detection determination result c is "H".
This is the case when an error is detected. As described above, the switch element 9 selects the identification command output value d and outputs it to the output unit 11 at the timing of the field clock a. That is, the value that should have been output as the B7 ideal output value f should output the value stored as the previous value because the erroneous detection determination result c indicates "H" error.
The identification command output value d will output an identification command output value d different from the B7 ideal output value f. Originally
In the identification command B7, "L" represents the frame A and "H"
Represents the frame B, and conversely, storing the previous value causes a malfunction of the frame. In addition, there is a problem that the identification control signal for reproducing the EDTV-II signal cannot be normally decoded and the displayed image is affected.

[0022]

SUMMARY OF THE INVENTION The present invention has been made in view of such problems, and the problem is, for example, EDTV.
-In an identification signal processing device that processes the output of the identification command detected in II by storing the previous value to prevent malfunction, the identification that improves the timing shift due to the processing of the identification command having periodicity and enables accurate decoding It is to provide a signal processing device.

[0023]

In order to solve such a problem, the identification signal processing device of the first invention is configured to include the identification command bit 7 included in the identification control signal, for example, in the second generation high definition television signal. In an identification signal processing device of a broadcast signal receiver for receiving and processing a broadcast signal in which an identification command having a periodic pattern having several fields such as "frame number" as one period is received, the identification command is transmitted from the identification control signal. The demodulation means for decoding, the erroneous detection determination means for determining whether or not the identification command is correctly detected, and the detection value of the demodulation means and the period storage means described later are selected according to the determination result of the erroneous detection determination means. The selecting means to output and the cycle of the identifying command having the periodicity, which is obtained by extracting the identifying command having the periodicity from the output value of the selecting means. And a period storing means for storing the output value. Then, when the erroneous detection determining means detects an erroneous detection, the output value of the cycle storing means is selected and output instead of the demodulating means. As a result, the identification command B
For the identification command having a periodic pattern such as 7, it becomes possible to store the previous value to prevent malfunction, and prevent malfunction of the reinforcement signal decoding device or screen mode switching device that responds to the output of the identification command. be able to.

In the identification signal processing device of the second invention, the identification control signal has a plurality of cycles such as "still image / film mode" of the identification command bit 17 included in the second generation high definition television signal. In an identification signal processing device of a broadcast signal receiver for receiving and processing a broadcast signal including an identification command having a pattern, demodulation means for decoding the identification command from an identification control signal and whether or not the identification command is correctly detected. Whether or not the detection value of the demodulation means and the period storage means described later is selected and output according to the determination result of the error detection determination means, and the periodicity is determined from the output value of the selection means. The present invention is provided with a cycle storing means for extracting the inputted identification command and inputting it, and storing the common multiple of the cycle of the identification command having the periodicity. When the erroneous detection determining means detects an erroneous detection, the selecting means selects and outputs the output value of the cycle storing means. As a result, it becomes possible to deal with an identification command having a plurality of periodic patterns such as the identification command B17 which is currently under consideration, and the previous value can be stably stored to prevent malfunction.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the accompanying drawings. The conventional E
The same parts as those in the drawing showing the DTV-II identification signal processing apparatus are designated by the same reference numerals.

First, referring to FIG. 1, the EDTV-of the present invention.
The configuration of the II receiver will be described. FIG. 1 shows the EDTV of the present invention.
FIG. 3 is a block circuit diagram showing an example of an II receiver.

The configuration of the EDTV-II receiver of the present invention comprises an antenna 12 for receiving a broadcast signal, a tuner 13 for demodulating the broadcast signal, and a video intermediate frequency circuit V for performing amplification / video detection.
IF (Video Intermediate Frequency) 14, A / D converter 1 for performing analog-to-digital conversion of received broadcast signals
5. A three-dimensional Y / C separator 16 into which a digitally converted composite video signal is input in parallel, a motion detector 17, an identification control signal processor 18 and a timing generator 19 according to the present invention, and a three-dimensional Y C / HH 'separator 20 for separating the separated C + HH' from the / C separator 16, an HH demodulator 21 for demodulating the separated HH ', and a color signal C output from the C / HH' separator 20 The color difference signal R-
A color demodulator 22 for outputting Y and BY, an adder 23 for adding YL output from the three-dimensional Y / C separator 15 and HH output from the HH demodulator 21, and R, G, and
It is composed of a matrix 24 for converting into a B signal, a CRT (cathode ray tube) 25 as a display means, and the like. The identification signal processing device section according to the present invention is the identification control signal processor 17 and the timing generator 18.

The operation of the EDTV-II receiver of the present invention having such a configuration will be described.

The antenna 12 receives the broadcast signal and outputs the RF signal.
A signal is generated and the RF signal is output to the tuner 13 at the next stage. The tuner 13 carries out an operation of band amplification and conversion into a video intermediate frequency signal, and an operation of selecting a desired broadcast signal by a music selecting means (not shown). The VIF 14 removes, amplifies, and video-detects the interfering wave of the broadcast signal converted into the VIF signal by the tuner 13, extracts the composite video signal, and outputs the composite video signal to the A / D converter 15. A / D
The converter 15 converts the composite video signal into a digital composite video signal suitable for the following processing.

In the three-dimensional Y / C separator 16, for example, a digitized composite video signal is stored in a memory, and addition / subtraction is performed between adjacent scanning lines in a moving image and between fields in a still image to move. By combining these based on the result of the detector 17, the luminance signal YL
And the color signal C + HH 'are separated. The luminance signal YL is output to the adder 23 at the next stage. The identification control signal processor 18 according to the present invention decodes and outputs an identification signal for identifying EDTV-II broadcasting and various control information necessary for decoding. The timing generator 19 digitally generates and outputs various timing pulses required for the EDTV-II receiver.

On the other hand, C + HH 'separated by the three-dimensional Y / C separator 16 is input to the C / HH' separator 20 in the next stage. The C / HH 'separator 20 separates the color signals C and HH', and the color signal C is demodulated by the color demodulator 22 into color difference signals RY and BY, which are output to the matrix 24. HH 'is sent to the HH demodulator 21, decoded by synchronous detection, etc., and output to the adder 23 as the original HH. The adder 23 adds YL and HH and outputs it to the matrix 24 as a broadband luminance signal Y in the EDTV-II system. CR in the next stage in matrix 24
After conversion into R, G, and B signals suitable for T25, the signals are output to the CRT 25 for information display.

Embodiment 1 Continuing on, a concrete example of an identification signal processing apparatus for an EDTV-II receiver according to the present invention will be described with reference to FIG. 2A and 2B are views showing an embodiment 1 of an identification signal processing device for an EDTV-II receiver of the present invention. FIG. 2A is a block circuit diagram of the identification signal processing device of the present invention, and FIG. 3 is a block circuit diagram showing a configuration example of a cycle storage circuit included in the identification signal processing device of FIG.

The essential configuration of the identification signal processing device of the present invention is as follows:
Input unit 6, 22/28 of the video signal input to the input unit 6
Bit decoding circuit 7 as demodulation means for decoding the identification command from the EDTV-II identification control signal superimposed on the 5th line, erroneous determination as to whether or not the identification command detected by the bit decoding circuit 7 is correctly detected A switch element 9 as a selection means for selecting an output value according to the determination results of the detection determination circuit 8 and the erroneous detection determination circuit 8,
Output updating circuit 1 for outputting the value selected by the switch element 9 to the output unit 11 in response to the field clock a
0 and as a feature of the present invention, it is configured by a cycle storage circuit 100 that feeds back the output value of the output update circuit 10 as an input and stores a predetermined cycle. The identification command detection value b detected by the bit decoding circuit 7 is B
These are the values of the identification command bits 1 to B23.

The operation of the identification signal processing device of the EDTV-II receiver of the present invention will be described.

The EDTV-II signal input to the input section 6 is input to the bit decoding circuit 7. The bit decoding circuit 7 identifies each of the identification commands B1 to B23 of the identification control signal (see FIG. 6B) superimposed on the input video signal.
Is detected and output as the identification command detection value b. The erroneous detection determination circuit 8 receives B1 to B23 of the identification command detection value b detected by the bit decoding circuit 7, and checks the detection result by using the above-mentioned check function inherent in the identification command detection value b. . As a result of these checks, if at least one is determined to be an error, the false detection determination result c outputs an "H" level indicating an error, and outputs a "L" level indicating a normal state in the normal case.

The switch element 9 is a bit decoding circuit 7
B1 to B23 of the identification command detection value b, which is the output of
Other than the output value B7 of the cycle storage circuit 100 and the identification command output value d7 described later (B1 to B6, B8 to B2).
3) and are selected according to the determination result of the erroneous detection determination circuit 8. That is, when the erroneous detection determination result c is determined to be an “H” error, the output value B7 of the cycle saving circuit 100 and the identification command output values d of B1 to B6 and B8 to B23 (B7).
Other than) is selected, and when it is determined to be normal, the identification command detection value b is selected as it is. The output update circuit 10 outputs the identification command value selected by the switch element 9 as the identification command output value d to the output unit 11 in response to the rising edge of the field clock a and stores the output value until the next rising edge of the field lock a. To do. As will be described in detail later, the cycle storage circuit 100 responds to the rising edge of the field clock a and outputs B1 of the identification command output value d.
Of B23 to B23, B7 having a periodic pattern is input, delayed by 3 fields, and output to the switch element 9.

Next, an example of the structure of the cycle storage circuit included in the identification signal processing device of the present invention will be described with reference to FIG.

The cycle storage circuit of the identification signal processing apparatus of the present invention is constructed as shown in FIG. That is, among the B1 to B23 of the identification command output value d output from the output update circuit 10 of FIG.
Input section 101 which receives as input, D circuit 1 which updates the input value to the output value in response to the rise of the field clock a
02, 103, 104 and the output unit 105. The cycle storage circuit 1 of the identification signal processing device of the present invention
The circuit configuration of 00 is not limited to the one described above, and it goes without saying that another configuration having the same function may be used.

The operation of the cycle storage circuit of the identification signal processing apparatus of the present invention having such a configuration will be described.

The D circuit 102 in FIG. 2B stores the inputted identification command B7 having periodicity for one field period in synchronization with the rising edge of the field clock a and updates the input value. Similarly, the D circuit 103 updates the input output value of the D circuit 102 in response to the rise of the field clock a. The D circuit 104 also updates the output by the same process. As a result, the output value of the D circuit 104 can be delayed by 3 field clocks from the output of the output update circuit 10, and a cycle storage circuit that stores the sequence of 4 field cycles together with the output update circuit 10 is realized.

The decoding processing operation of the identification signal processing apparatus of the present invention will be described with reference to the timing charts of FIGS. FIG. 3 is a timing chart showing the decoding processing operation of the identification signal processing device of the present invention.

22 / 285H in FIG. 3 is a line in which the identification control signal of the input video signal is present,
At this timing, the identification control signal decoding circuit operates once per field. The field clock a is the update timing of the output in FIG.
The identification command detection value b is detected between the rising timing of 285H and the rising edge of the feed clock a, and the erroneous detection judgment is performed during the detection of the erroneous detection.
Is output as. The output value x of the cycle storage circuit is a value delayed by 3 fields from the identification command detection value b generated by the cycle storage circuit 100 described above. Then, the switch element 9 operates based on the erroneous detection determination result c of the erroneous detection determination circuit 8, and the output update circuit 10 outputs the identification command output value d. The B7 ideal output value f in FIG. 3 is the ideal value of this output.

Here, the state [A] in FIG. 3 is a case where the erroneous detection determination result c is "L" normal. The switch element 9 selects the identification command detection value b and outputs the identification command output value d at the timing of the field clock a.

In the state [B], the erroneous detection determination result c is "H".
This is the case when an error is indicated. The output value B7 of the cycle storage circuit 100 is selected by the switch element 9, and is output to the output unit 11 via the output update circuit 10 as the identification command output value d at the timing of the field clock a. As a result, it becomes possible to store the previous value for the identification command having the periodic pattern to prevent malfunction, and prevent malfunction of the reinforcement signal decoding device or screen mode switching device that responds to the output of the identification command. You can

As described above, in the identification signal processing apparatus of the present invention, in the processing of the identification command such as B7 in which one field is several fields, a new cycle storage circuit 100 is added to store the previous value in one cycle unit. (4 fields, 1 cycle in this example). Then, the erroneous detection determination circuit 8
Indicates a "H" error, the stored periodic pattern (in this example, the period of four fields before) is selected and output. As a result, it is possible to perform stable previous value storage output for a periodic identification command such as B7. Further, with the configuration as shown in FIG. 3, when there is no erroneous detection, the output is the identification command detection value b detected in that field, which is also effective for identification command processing that requires prompt response. is there.

Embodiment 2 The identification command B17 of the EDTV-II identification control signal is B
It is under consideration as "still image / film mode" at TA. According to this, a configuration in which several fields are set to one cycle like B7 described above is considered, and four modes of 24 frame film mode, 30 frame film mode, still image mode, and normal mode are examined depending on the cyclic pattern. Has been done. The present embodiment is an example in which the identification signal processing device is applied to the identification command B17, which is shown in FIGS.
This will be described with reference to FIG.

First, the identification command B17 according to the present invention.
Will be described with reference to FIG. FIG. 4 shows the ED of the present invention.
It is a conceptual diagram which shows the identification command B17 periodic pattern concerning Embodiment 2 of the identification signal processing apparatus of a TV-II receiver.

In the "still image / film mode" under consideration, the 24 frame film mode has a periodic pattern of 1 cycle in 5 fields, the 30 frame film mode has 1 cycle in 2 fields, and the still image mode is "1". Is continuously expressed, and in the normal mode, it is expressed by continuous “0”. Even in the case of having a periodic pattern of a plurality of lengths like this, it is possible to add a previous value storage function by adding a period storage circuit in which B7 is replaced with B17 in FIG. 2A of the present invention. Become.

The structure of this embodiment will be described with reference to FIG. 2A. The input unit 6 and the input EDTV-II will be described.
A bit decoding circuit 7 that detects an identification command from an identification control signal, an erroneous detection determination circuit 8 that determines whether the identification command is correctly detected, and a switch element that selects an output value according to the determination result of the erroneous detection determination circuit 8. 9, an output update circuit 10 that outputs the value selected by the switch element 9 to the output unit 11 in response to the field clock a, and the output update circuit 10 is a feature of this embodiment.
B17 is taken out from the output value of and the cycle storage circuit 100 'is used as an input. That is, the cycle storage circuit 10
Since the identification command B17 that inputs 0'has a plurality of periodic patterns of 5 fields 1 period, 2 fields 1 period, 1 field 1 period, take the common multiple of these and consider it as 10 fields 1 period. To form a cycle storage circuit 100 'having a cycle of 10 fields. In addition,
The following operations will be omitted because they overlap.

Furthermore, a configuration example of the cycle storage circuit of the present embodiment will be described with reference to FIG. FIG. 5 shows the EDTV of the present invention.
FIG. 9 is a block circuit diagram showing a configuration example of a cycle storage circuit included in the second embodiment of the identification signal processing device of the −II receiver.

The cycle storage circuit of this embodiment is shown in FIG.
Of B1 to B23 of the identification command output value d output from the output update circuit 10 in (a), the input unit 106 that receives B17 having the above-described periodic pattern as an input, and the input value in response to the rising of the field clock a. Circuit 107 to D circuit 115 for updating the output value to the output value, and the output section 11
It is composed of 6.

The operation of the cycle storage circuit of this embodiment having the above configuration will be described.

The D circuit 107 in FIG. 5 stores the input identification command B17 having periodicity for one field period in synchronization with the rising edge of the field clock a and updates the input value. Similarly, the D circuit 108 receives the D circuit 1 input in response to the rising edge of the field clock a.
The output value of 07 is updated. The output is updated by the same processing in the D circuit 109 and thereafter. As a result, the output value of the D circuit 115 can be delayed from the output of the output updating circuit 10 by 9 field clocks.
A cycle storage circuit that stores a sequence of 10 field cycles together with 0 is realized.

The present invention is not limited to the above embodiment,
Various embodiments can be adopted. For example, in this embodiment, an EDTV-II is used as an example of an identification signal processing device.
Although the receiver has been described, it is needless to say that the invention can be applied to other AV devices such as video devices, recordable disk devices, recording medium integrated monitor devices, projector devices, and the like. That is, by decoding the identification signal processing device of the present invention as an integrated circuit IC in these AV devices or by programmatically incorporating it in another ASIC for a specific purpose, the identification control signals of these AV devices are decoded. Can be reliably performed. Needless to say, the present invention can be developed into various forms without being limited to the above-described embodiment.

As described above, according to the identification signal processing apparatus of the first aspect of the invention, the identification command processing having the periodic pattern of one period in several fields, such as the identification command of the EDTV-II identification control signal, is processed. In the above, the cycle storage means is provided to store the output value of the identification command for the same cycle pattern, and when an error is detected, the output value of the cycle storage means is selected and output. This allows
For the identification command having the periodic pattern, it becomes possible to save the previous value to prevent malfunction, and it is possible to prevent malfunctions such as a reinforcement signal decoding device that responds to the output of the identification command and screen mode switching. .

In the identification signal processing device of the second invention, for example, an identification command having a plurality of periodic patterns such as "still image / film mode" of the identification command bit B17 included in the second generation high definition television signal is provided. In the process (1), the cycle saving means is provided to save the common multiple of the cycle pattern, and when an error is detected, the output value of the cycle saving means is selected and output. As a result, for example, it becomes possible to deal with an identification command having a plurality of periodic patterns such as the identification command B17 currently under consideration, and the previous value can be stably stored to prevent malfunction.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an example of an EDTV-II receiver of the present invention.

2A and 2B are diagrams showing Embodiment 1 of an identification signal processing device for an EDTV-II receiver of the present invention, in which FIG. 2A is a block circuit diagram of the identification signal processing device of the present invention, and FIG. It is a block circuit diagram which shows the structural example of the period preservation | save circuit which exists in the identification signal processing apparatus of invention.

FIG. 3 is a timing chart showing a decoding processing operation of the identification signal processing device of the present invention.

FIG. 4 is a conceptual diagram showing an identification command B17 periodic pattern according to the second embodiment of the identification signal processing device of the EDTV-II receiver of the present invention.

FIG. 5 is a block circuit diagram showing a configuration example of a period storage circuit included in the second embodiment of the identification signal processing device of the EDTV-II receiver of the present invention.

6A and 6B are diagrams showing an outline of an identification control signal of EDTV-II, FIG. 6A is a diagram showing an identification control signal waveform, and FIG. 6B is a diagram showing bit positions and identification contents.

FIG. 7 is a block circuit diagram showing an example of an identification signal processing device of an EDTV-II receiver according to the present invention.

8A and 8B are diagrams showing a decoding operation of the identification signal processing device according to the present invention, in which FIG. 8A is a timing chart showing a processing operation of a normal identification command, and FIG. 8B shows an identification command B7 having a periodic pattern. It is a timing chart figure which shows a processing operation.

[Explanation of symbols]

1 Horizontal sync signal Hsync 2 color burst 3 NRZ 4-color subcarrier (fsc) 5 confirmation signal 6,101,106 Input section 7-bit decoding circuit 8 False detection judgment circuit 9 switch elements 11,105,116 Output section 10 Output update circuit 12 antennas 13 tuners 14 VIF 15 A / D converter 16 Three-dimensional Y / C separator 17 Motion detector 18 Identification control signal processor 19 Timing generator 20 C / HH 'separator 21 HH demodulator 22 color demodulator 23 adder 24 matrix 25 CRT 100,100 ′ cycle storage circuit 102,103,104 D circuit 107 to 115 D circuit HH high frequency luminance signal HH 'Horizontal resolution enhancement signal after frequency shift VH Luminance signal vertical high frequency component VT vertical time resolution enhancement signal

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kazuo Watanabe 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) Reference JP-A-7-193758 (JP, A) JP-A 8-251506 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/44-5/46 H04N ^7/ 08-7/081

Claims (4)

(57) [Claims] 1. An identification signal processing device of a receiver for receiving and processing a broadcast signal on which an identification control signal having a periodicity is embedded, the demodulation for demodulating the identification command from the identification control signal. Means, an erroneous detection determination means for determining whether or not the identification command is correctly detected, a selection means for selecting a predetermined detection value according to a determination result of the erroneous detection determination means, and an output value of the selection means The erroneous detection determining means detects erroneous detection by extracting the identification command having the periodicity as an input and saving the output value for the period of the identification command having the periodicity. At this time, the identification signal processing device is characterized in that the selecting means selects and outputs the output value of the cycle storing means. 2. The identification command having the periodicity is a second command.
The identification signal processing device according to claim 1, wherein the identification signal bit is a "frame number" of an identification command bit B7 included in a next generation high definition television signal. 3. An identification signal processing device of a receiver for receiving and processing a broadcast signal on which an identification control signal in which identification commands having a plurality of periodicities are embedded is received, and the identification command is demodulated from the identification control signal. Demodulating means, erroneous detection determining means for determining whether or not the identification command is correctly detected, selecting means for selecting a predetermined detection value according to the determination result of the erroneous detection determining means, and the selecting means The identification command having the periodicity is extracted from the output value and is inputted, and a cycle storage means for storing the common multiple of the period of the identification command having the periodicity is provided, and the false detection determination means makes a false detection. An identification signal processing device, characterized in that, when detected, the output value of the cycle storage means is selected and output by the selection means. 4. The identification command having the periodicity is a second command.
4. The identification signal processing device according to claim 3, wherein the identification command bit B17 included in the next-generation high-definition television signal is "still image / film mode".