JPH04256294A - Television receiver - Google Patents

Abstract

PURPOSE:To alter the signal processing for a received video signal with an identification signal from a broadcasting station without the intervention of user operation. CONSTITUTION:An identification signal detecting circuit 48 detects the identification signal inserted into the received video signal and outputs detection pulses to a loading circuit 9. The loading circuit 49 supplies an address output based upon the detection pulses to a ROM 51. The ROM 51 is stored with a program for normal television broadcast reception and a program for wide-aspect television broadcast reception and a program based upon the detection pulses is supplied by the loading circuit 49 to respective DSPs of a DSP array group 52. Thus, the DSP array group 52 performs a signal process based upon the detection pulses and the signal processing of the DSP array group 52 can be controlled on the broadcasting station side.

Description

[Detailed description of the invention]

[Object of the invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver suitable for realizing a plurality of types of video processing by switching the program applied to a digital signal processor.

0002

2. Description of the Related Art FIGS. 10 to 13 and 14 are a block diagram and an explanatory diagram, respectively, for explaining a digital signal processor (hereinafter referred to as DSP). These block diagrams and explanatory diagrams are provided in the document “A GENERAL PU
RPOSE PROGRAM MABLE VIDEO
SIGNAL PROCESSOR” (IEEE Tr.
Answers on Consumer El
electronics Vol. 35 No. 3 AUG
UST 1989) and indicates a DSP for video signal processing.

FIG. 10 shows a DSP chip 100 for video. The DSP chip 100 is composed of a DSP 101 having five systems of data ports so as to enable connection between a plurality of DSPs. Clock generator 102 creates an internal clock based on an external clock. The initial controller 103 is supplied with initial data and a reset signal, and when given a chip address indicating this DSP chip 100, performs predetermined initial settings.

FIG. 14 is an explanatory diagram for explaining the architecture of a DSP.

[0005] The DSP has three systems of ALE (
Arithmetic and Logic Ele
ment) and two systems of ME (Me
It has 5 systems of OB (output buffer). The three ALE systems, the two ME systems, and the five OB systems are controlled by programs P1 to P10, respectively.

FIG. 11 shows the configuration of ALE.

[0007] ALE has ports 105 to 107 for taking in data, and each port 105 to 107
Data A, B, and C input through the shifter 1 respectively.
08 to 110 and multiplexers 111 to 1
13 to an ALU (logical operation unit) 114.

FIG. 12 shows the configuration of the ME.

Address data is applied to an adder 116 via a port 115, added to a predetermined value, and further applied to a RAM 118 via a multiplexer 117. On the other hand, data is input via port 119,
It is applied to RAM 18 via multiplexer 120. RAM 18 is a 512×12 static memory.

FIG. 13 shows three DSPs 122 to 124.
The figure shows a DSP chip 121 configured by. The DSPs 122 to 124 are interconnected using data ports, and each DSP 12
2 to 124 each have one system of data ports for data transfer with the outside.

[0011] In recent years, the above-mentioned D
The number of devices that use SP to perform digital processing is increasing. For example, patent application No. 2-846 filed earlier by the applicant.
DSP is also employed in the "Image Reproducing Apparatus" described in Specification No. 28.

According to this proposal, a television receiver is constructed that utilizes a plurality of DSPs to realize a plurality of functions. A plurality of processing programs are prepared to realize a plurality of functions, and these processing programs are switched by a timing signal created during a vertical or horizontal blanking period of a video signal transmission period. For example, this timing signal switches the processing program of each DSP so that normal television video processing is performed during the video period and ghost cancellation processing is performed during the non-video period.

By the way, in recent years, with the spread of large display devices, there has been a demand for higher image quality, and since the fall of 1989, the first generation EDTV (Extended Definition TV) has been introduced.
TV broadcasting has begun. Furthermore, the second generation E is used to improve image quality.
Research on television broadcasting using DTV is also being conducted. One of these is the wide aspect television receiver (hereinafter referred to as wide TV), which expands the aspect ratio of the screen.
) is being considered. Wide TV is the current NTS
The aspect ratio is expanded to 5:3 or 16:9 while maintaining compatibility with C-scheme television receivers.

[0014] By applying the above-described image reproducing device to such a wide TV, it is possible to easily switch the display between the current NTSC television broadcast and the second generation EDTV television broadcast.

However, in this case, the display must be switched on the image reproducing device, and the broadcasting station must
It is not possible to display images by switching between the SC method and the EDTV method.

[0016]

[Problem to be Solved by the Invention] Conventionally, in television receivers, the program given to each DSP is changed on the receiver side, so the broadcast station side can freely display the intended video. There was a problem that it could not be displayed on the display screen.

The present invention has been made in view of this problem, and uses an identification signal inserted at a broadcasting station to
An object of the present invention is to provide a television receiver capable of displaying images intended by a broadcasting station by making it possible to switch programs given to an SP.

[Configuration of the invention]

[Means for Solving the Problems] A television receiver according to claim 1 of the present invention includes receiving means for receiving a video signal from a transmitting side into which an identification signal can be inserted at a predetermined timing;
a first program memory that stores a plurality of programs for signal processing the video signal; a rewritable second program memory; and the video signal received based on the program read from the second program memory. a synchronization separation circuit that separates a synchronization signal from the video signal received by the reception means; and a synchronization separation circuit that uses the synchronization signal to generate a timing signal indicating a predetermined timing at which the identification signal is inserted. a timing generation circuit that detects the identification signal from the received video signal at the timing of the timing signal and outputs a detection pulse; and loading means for storing the loaded program in the second program memory, and the television receiver according to claim 2 of the present invention is characterized in that the identification signal detection means is constituted by a digital code. It is characterized by detecting an identification signal.

[0019]

According to claims 1 and 2 of the present invention, the timing generation circuit uses a synchronization signal to generate a timing signal indicating the timing of the identification signal inserted on the transmitting side. The identification signal detection means detects the identification signal at the timing of this timing signal and provides a detection pulse to the loading means. The loading means selects a program stored in the first program memory based on the detection pulse, and stores this program in the second program memory. The arithmetic processing means performs video processing based on the second program memory. The identification signal is inserted on the transmitting side, and the processing of the arithmetic processing means is switched by an operation on the transmitting side.

[0020]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a television receiver according to the present invention. This embodiment allows the broadcasting station to switch between NTSC video and EDTV wide aspect video displayed on the display screen of a terminal receiver. Further, FIG. 2 is a block diagram showing an encoder on the broadcasting station side. This encoder is “A WIDE
SCREENEDTV” (IEEE TRANSAC
TIONS ON CONSUMERELECTRON
ICS AUGUST 1989).

First, referring to the encoder shown in FIG.
A method of creating a video signal from a broadcasting station for displaying TSC video or EDTV wide aspect video will be described.

On the broadcasting station side, first, a wide aspect video signal with an aspect ratio of 16:9 (the band of the luminance signal Y is 5.6 MHz, and the bands of the color difference signals I and Q are each 2 MHz) is used.
．． 0MHz, 0.67MHz), a signal at the center of the screen corresponding to the aspect ratio of 4:3 (hereinafter referred to as center signal), and a signal at the side of the screen corresponding to the left and right edges of the screen ( (hereinafter referred to as side signal).

[0023] The center signal is time-expanded by 4/3,
The luminance signal component (4.2 MHz) and color difference signal components I and Q (I: 1.5 MHz, Q: 0.5 MHz) are sent to preprocessors 21 and 24, respectively, which perform multiplexing without degrading the image quality in the center of the screen. Given.

The luminance signal component of the side portion of the screen is divided into luminance signals Y1, Y2, and Y3 of three types of frequency components and transmitted by three types of multiplexing methods. That is, the luminance signal component Y1
has a band of 0 to 0.9 MHz, is time-compressed to 1/4, and then multiplexed onto the horizontal overscan portion (shaded portion) of the center signal. The luminance signal from the preprocessor 21 is output to a synthesis circuit 26.

The luminance signal Y2 is 0.9 in the first field.
It has a band of 5.6 MHz to 5.6 MHz, and diagonal high-frequency components are removed, and time is expanded twice on average. The time-expanded luminance signal Y2 is given to the frequency shift circuit 22,
The frequency is 6/5fsc (fsc is color subcarrier frequency) (
4.3 MHz), and the field phase is frequency shifted by the inverted subcarrier. This luminance signal Y2 is given to the combining circuit 26, and the luminance signal Y2 of the center part of the screen is
It is three-dimensionally frequency multiplexed from 4 MHz to 4 MHz.

The luminance signal Y3 is 0.9 in the second field.
It has a band of 2.7 MHz to 2.7 MHz, and time is compressed to 1/2. Furthermore, regarding the luminance signal Y3, the data is rearranged using a buffer memory or the like, and the frequency is shifted by a subcarrier of 10/13 fsc (2.8 MHz) in a frequency shift circuit 23. Frequency shift circuit 23
The output is given to the combining circuit 26 and multiplexed into the vertical overscan area (hatched area).

Luminance signals Y1 to Y3 from the synthesis circuit 26
is applied to a precombing circuit 28 for motion-adaptive precombing, and is band-limited to horizontal and vertical two-dimensional diagonal high frequencies in the moving image area.

On the other hand, the color difference signals I and Q at the side of the screen are 2
The signal is divided into two types of frequency components C1 and C2 and transmitted using two types of multiplexing methods. That is, the signal C1 has a frequency band of 0.
to 0.12 MHz, time-compressed to 1/4 times, and multiplexed into the horizontal overscan area of the color difference signals I and Q at the center of the screen. The frequency band of the color difference signal I is 0.12 to 2.0 MHz, and the frequency band of the color difference signal Q is 0.12 to 0.67 MHz, and the signal C2 is time-compressed four times. Furthermore, the signal C2 is changed in frequency to 1/7fsc (0.5M
Hz) with line and field phase inversion subcarriers. The signal C2 from the frequency shift circuit 25 is applied to the synthesis circuit 27, and is three-dimensionally frequency multiplexed into the color difference signals I and Q at the center of the screen.

The signals C1 and C2 from the synthesis circuit 27 are applied to a precombing circuit 29, where they are subjected to motion adaptive precombing, and the horizontal high frequency range of the moving image area is band-limited to 0.5 MHz. Further, the color difference signals I and Q from the precombing circuit 29 are converted to 3.58 MHz by the quadrature modulation circuit 30.
is orthogonally modulated by the chrominance subcarrier. The luminance signal Y from the precombing circuit 28 and the color signal C from the quadrature modulation circuit 30 are multiplexed in a combining circuit 31 and sent out.

[0030] This video signal is received and decoded on the receiving side. An identification signal is inserted into this video signal to distinguish the broadcasting system. This identification signal is inserted and transmitted, for example, at a position delayed by a predetermined time from the burst signal on the 263rd line. By inserting this identification signal, the broadcasting station indicates that it is wide aspect television broadcasting, and
No identification signal is inserted during SC television broadcasting.

On the other hand, on the receiving side, as shown in FIG.
F) The signal is given to the tuning circuit 42. A tuning signal is given to the tuning circuit 42 (not shown), and the tuning circuit 4
2 selects the channel based on the channel selection signal and transmits the intermediate frequency (
IF) signal and provides it to the audio intermediate frequency amplification and detection circuit 43 and the video intermediate frequency amplification and detection circuit 44. The video intermediate frequency amplification/detection circuit 44 detects the IF signal and outputs a baseband video signal.

The audio intermediate frequency amplification and detection circuit 43 performs audio detection on the audio intermediate frequency signal included in the IF signal from the channel selection circuit 42 and outputs the audio detection output to the audio signal processing circuit 45 . The audio signal processing circuit 45 performs various processes such as audio multiplexing, volume, sound quality, and balance, and supplies the audio signal to the speaker 46 for audio output.

On the other hand, the video signal from the video intermediate frequency amplification/detection circuit 44 is sent to the A/D converter 47 and the identification signal detection circuit 4.
8 is also given. The A/D converter 47 converts the analog video signal into a digital signal and sends it to the DSP array group 52.
It is designed to be given to The identification signal detection circuit 48 detects the identification signal inserted into the input video signal, and outputs a detection pulse that becomes high level (hereinafter referred to as "H") to the load circuit 49 at the detected timing. Further, the power-on detection circuit 50 is configured to apply a pulse to the load circuit 49 when it detects that the power is turned on. Based on the detection pulse from the identification signal detection circuit 48 and the pulse from the power-on detection circuit 50, the load circuit 49 outputs a signal of a predetermined value to the ROM as an address output.
51 and a DSP array group 52.

FIG. 3 is a block diagram showing a specific configuration of the identification signal detection circuit 48, load circuit 49, power-on detection circuit 50, ROM 51, and one DSP of the DSP array group 52 in FIG.

The video signal from the video intermediate frequency amplification/detection circuit 44 is inputted to the synchronization separation circuit 61 and the slice circuit 63 via the input terminal 60 of the identification signal detection circuit 48 . The synchronization separation circuit 61 separates the synchronization signal from the video signal and supplies it to the timing circuit 62. The timing circuit 62 uses the synchronization signal from the synchronization separation circuit 61 to detect the 263rd line of the vertical blanking period,
A latch pulse is applied to the latch circuit 65.

On the other hand, the slice circuit 63 receives a slice level signal at a terminal 64, slices the video signal inputted through the input terminal 60 at this slice level, binarizes it, and sends the binarized pulse to the latch circuit. Give to 65. The latch circuit 65 detects whether or not an identification signal is inserted into the video signal by latching the binarization pulse of the slice circuit 63 at the timing of the latch pulse from the timing circuit 62, and detects whether or not the identification signal is inserted into the video signal. outputs a detection pulse of "H" to the load circuit 49, and when the detection pulse is not inserted, the detection pulse is set to "L" and output to the load circuit 49.

The detection pulse is input to the state memory 66, comparison circuit 67 and offset generation circuit 68 of the load circuit 49. The state memory 66 stores the state of the detection pulse of the previous field and supplies it to the comparison circuit 67. The comparison circuit 67 compares the detection pulse from the identification signal detection circuit 48 with the detection pulse of the previous field, and outputs the comparison result to a flip-flop (hereinafter referred to as FF) 70 via an OR circuit 69. The FF 70 is set by the "H" output of the OR circuit 69 and provides a reset signal to the address counter 71, and also controls the state memory 66. The address counter 71 is reset by the reset signal and starts counting. The count output of the address counter 71 is outputted via the adder 72 as a read address of the ROM 51. The adder 72 includes an offset generation circuit 68.
A predetermined value is given from . The offset generation circuit 68 gives a predetermined value "b" to the adder 72 when the detection pulse is "H", and gives a predetermined value "0" to the adder 72 when the detection pulse is "L". It looks like this. The adder 72 adds the output of the offset generation circuit 68 and the output of the address counter 71 and provides the result to the ROM 51 as an address output. Also,
The OR circuit 69 of the load circuit 49 has a power-on detection circuit 5.
A pulse from 0 is also given.

The power-on detection circuit 50 includes resistors R1 to R
4, transistors T1 and T2, a Zener diode ZD, and a one-shot multivibrator 73. Resistors R1 and R2 are connected in series between the power supply terminal 74 and the reference potential point.
, R2 are connected to the base of transistor T1. The emitter of the transistor T1 is connected to a reference potential point via a Zener diode ZD, and the collector is connected to the power supply terminal 74 via a resistor R3 and to the base of the transistor T2. The emitter of transistor T2 is connected to power supply terminal 74,
The collector is connected to a reference potential point via a resistor R4, and is also connected to the input end of a one-shot multivibrator 73.

When the power is turned on, as the voltage at the power supply terminal 74 increases, the voltage at the connection point of the resistors R1 and R2 becomes higher than the Zener voltage of the Zener diode ZD,
Transistors T1 and T2 are turned on. Then, the one-shot multivibrator 73 is triggered and a pulse is output. That is, when the power is turned on,
The pulse from the one-shot multivibrator 73 is O
It will be given to the FF 70 via the R circuit 69,
Regardless of the state of the state memory 66, the offset generation circuit 6
An address output based on the output of 8 will be output.

FIG. 4 is an explanatory diagram showing an address map of the ROM 51. A program for receiving normal NTSC television broadcasting is stored at addresses 0 to a, and a program for receiving wide aspect television broadcasting is stored at addresses b to c. The address of the ROM 51 is specified by the output of the adder 72 of the load circuit 49, and the stored program is supplied to each DSP of the DSP array group 52.

DSP 74 in FIG. 3 represents one DSP in DSP array group 52. Program memory 7
The program from the ROM 51 is applied to the ROM 51 via the switch 76, and the stored program whose read address is designated via the switch 77 is applied to the ALE 78 via the switch 76. The switch 77 selects the address output from the program counter 79 and the address output from the address counter 71 of the load circuit 49 and applies the selected address to the program memory 75.

Switches 76 and 77 are F of the load circuit 49.
Controlled by F70. When FF70 is set, switch 76 selects ROM51, and switch 76 selects ROM51.
7 selects the address counter 71. That is, F.F.
70 is set, a program based on the address output from the adder 72 is read from the ROM 51 and written into the program memory 75 based on the address output from the address counter 71. Program memory 7
When the last address of 5 is written, the FF 70 is reset, and the address of the program memory 75 is specified by the program counter 79, and the stored program is outputted to the ALE 78 via the switch 76.

The ALE 78 performs predetermined signal processing based on the program from the program memory 75. terminal 9
1 to 94 are connected to each terminal of each adjacent DSP, and signals from the terminals 91 to 94 are applied to the ALE 78 via the switch 90, processed by the ALE 78, and outputted from the terminals 91 to 94.

In FIG. 1, the DSP array group 52 has 4×
It is composed of 16 DSP groups D1 to D16 arranged in four arrays. As described above, each DSP group D1 to D16 of the DSP array group 52 has a program memory 75, and the program can be rewritten with the program in the ROM 51 using the switch 76. Each DSP group D1 to D16 implements processing functions based on programs stored in the program memory 75. That is, the DSP array group 52 is given a program from the ROM 51 and can perform processing for receiving normal television broadcasting or processing for receiving wide aspect broadcasting.

When a video processing program for normal television broadcast reception is given from the ROM 51 to the DSPD1 to D16, the DSP groups D1 and D2 perform Y/C separation, and the DSP groups D5 and D9 perform three-dimensional filter processing. , DSP groups D14 and D15 reproduce the center signal whose time has been expanded by 4/3 on the broadcasting station side, and DSP group D16
provides a center signal to the D/A converter 96, and also performs mask processing on the left and right ends of the monitor 98. Furthermore, DSP
Group D3 separates color difference signals I and Q, and DSP groups D4,
D8 performs three-dimensional filter processing on color difference signals and
The P groups D11 and D12 reproduce the original screen center signal by 3/4 times time compression, and the DSP group D12 supplies this reproduced output to the D/A converter 95, and also outputs the signal from the monitor 9.
The left and right end portions of 8 are masked. On the other hand, when the video processing program for wide aspect signal reception from the ROM 51 is given to the DSP array group 52, the DSP groups D1 and D2 perform Y/C separation processing and
The SP groups D5 and D9 are the luminance signals Y1 that have been subjected to three-dimensional filter processing and multiplexed in the horizontal overscan portion.
and frequency-multiplexed luminance signal Y2, and DS
The P groups D14 and D15 time-compress the center signal by 3/4 to reproduce the original center signal, and expand the side signal by 4 times to restore the original side signal. Furthermore, DSP group D
13, the luminance signal Y2 is frequency shifted by a subcarrier of 6/5 fsc and time compressed by 1/2 times, and the first
The side part of the screen of the field is reproduced, the DSP group D6 rearranges the data, and the DSP group D10 performs a frequency shift using a 6/5 fsc subcarrier and double time expansion to reproduce the side part of the screen of the second field. and DSP group D
16 combines the outputs of the DSP groups D15, D13, and D10 and outputs the result to the D/A converter 96.

Regarding color difference signals, DSP group D3
performs separation processing of the color difference signals I and Q, and the DSP group D4
, D8 performs three-dimensional filter processing, and the DSP group D11
, D12 time-compress the center signal by 3/4 times and return it to the original center signal, and the DSP group D12 outputs the output to the D/A converter 95.

The D/A converters 95 and 96 convert the input signals into analog signals and output them to the matrix circuit 97. The matrix circuit 97 performs matrix processing on the luminance signal from the D/A converter 96 and the color difference signal from the D/A converter 95 to create R, G, and B video signals and outputs them to the monitor 98. ing.

Next, the operation of the television receiver configured as described above will be explained with reference to FIGS. 5 to 7. 5 is a timing chart for explaining the operation of the identification signal detection circuit 48. FIG. 5(a) shows the identification signal included in the video signal from the broadcasting station, and FIG. 5(c) shows a latch pulse from the timing generation circuit 62, and FIG. 5(d) shows a detection pulse from the latch circuit 65.

The RF signal induced in the antenna 41 is applied to the channel selection circuit 42. The channel selection circuit 42 selects a channel based on the channel selection signal, converts it into an IF signal, and supplies the signal to an audio intermediate frequency amplification/detection circuit 43 and a video intermediate frequency amplification/detection circuit 44 . The IF signal is detected by the audio intermediate frequency amplification/detection circuit 43, and then subjected to audio multiplexing processing and various processing such as volume, sound quality, and balance in the audio signal processing circuit 45, and is outputted as audio from the speaker 46.

On the other hand, the baseband video signal detected by the video intermediate frequency amplification and detection circuit 44 is given to the identification signal detection circuit 48, and after being converted into a digital signal by the A/D converter 47, it is sent to the DSP array. Group 5
2 DSP group D1.

As shown in FIG. 5(a), the identification signal is inserted at a position a predetermined number of clocks apart from the trailing edge of the 263rd line of the vertical blanking period based on the clock of the color burst signal. . The video signal into which the identification signal has been inserted is applied to a slice circuit 63 and also to a synchronization separation circuit 61 to separate the synchronization signal. The timing generation circuit 62 detects the timing of the 263rd line in which the identification signal is inserted by counting the synchronization signals based on the burst signal, and calculates the timing for a predetermined number of clocks based on the clock of the color burst signal. A latch pulse shown in FIG. 5(c) is generated at a remote position.

On the other hand, the slicing circuit 63 binarizes the video signal by slicing the video signal at the slice level indicated by the dotted line in FIG. The latch circuit 65 latches the binarized pulse from the slice circuit 63 at the timing of the latch pulse and outputs it as a detection pulse. Therefore, Figure 5
When the identification signal is inserted as shown in the figure, the detection pulse becomes "H", and when the identification signal is not inserted, the detection pulse becomes "L".

[0053] Here, it is assumed that the processing function for receiving normal television broadcasting is realized on the broadcasting station side. That is, in this case, no identification signal is inserted into the 263rd line of the vertical blanking period on the transmitting side. FIG. 6 is a flowchart showing the operation in this case.

Since no identification signal is inserted into the video signal from the video intermediate frequency amplification/detection circuit 44, the detection pulse of the identification signal detection circuit 48 becomes "L". If no identification signal is inserted in the previous field, that is,
When normal television broadcast reception processing is being performed, the output of the state memory 66 and the detection pulse are the same, and the FF 70 is not set by the output of the comparison circuit 67. Therefore, in this case, DSP array group 5
The switch 76 of each DSP of 2 continues to select the program memory 75, and the switch 77 continues to select the program counter 79. In this way, the DSP array group 52
continues processing for normal television broadcast reception.

On the other hand, when an identification signal is inserted in the previous field and processing for wide aspect broadcast reception is performed, the output of the state memory 66 and the detection pulse are different, and the output of the comparison circuit 67 FF70 is set. Then, the address counter 71 is reset, the switches 76 and 77 are switched, and the program from the ROM 51 is stored in the program memory 75 of each DSP according to the address output of the address counter 71. In this case, the output of the offset generation circuit 68 is "0", the storage area of the NTSC program is designated in the ROM 51, and this program is stored in the program memory 75. When the final address of the program memory 75 is written, the FF 70 is reset, and the program for normal television broadcast reception stored in the program memory 75 is read out by the program counter 79 and given to the ALE 78.

Thus, in this case, the DSP array group 52 operates based on the flowchart of FIG. That is, in step S1 of FIG.
The video signal input via the DSP group D1 and D2 performs Y/C separation. Regarding the luminance signal component, three-dimensional filter processing is performed in the next step S2. That is, the luminance signal is given to the DSP groups D5 and D9,
Luminance signal Y multiplexed in the horizontal overscan part
1 is separated.

The luminance signal of the center portion of the screen is supplied from the DSP group D13 to the DSP group D14. DSP group D14
In the next step S3, time compression is performed, and the center signal, which has been time-expanded by 4/3, is reproduced to the original signal at the broadcast station side. The DSP group D16 performs the next step S4.
This luminance signal is supplied to the D/A converter 96 to be converted into an analog signal, and processing for masking the left and right ends of the monitor 98 is performed.

On the other hand, regarding the color signal, step S5
The processes from S8 to S8 are performed. In step S5, DS
Color difference signals I and Q are separated from the color signal by the P group D3. In the next step S6, three-dimensional filter processing is performed. That is, the DSP groups D4 and D8 separate the signal C1 of the side part of the screen that is multiplexed in the horizontal overscan part.

In the next step S7, the DSP group D11
, D12 reproduce the original center signal through 3/4 time compression, similar to the luminance signal component. DSP group D
12 outputs this center signal to the D/A converter 95 in the next step S8. Also, in this case, D
The SP group D12 also performs processing for masking the left and right ends of the monitor 98.

The luminance signals and color difference signals from the D/A converters 96 and 95 are subjected to matrix processing by a matrix circuit 97, and a monitor 98 is provided with R, G, and B signals at the center of the screen. Further, the side portion of the screen is masked, and a predetermined black level is displayed, for example. In this way, the center portion of the screen with an aspect ratio of 4:3 is displayed on the screen of the monitor 98.

On the other hand, it is assumed that the DSP array group 52 realizes a processing function for displaying wide aspect video of the EDTV system. In this case, an identification signal is inserted into the 263rd line of the vertical blanking period on the transmitting side. FIG. 7 shows the operation when receiving wide aspect television broadcasting of EDTV.

Since the identification signal is inserted into the video signal, the detection pulse of the identification signal detection circuit 48 becomes "H". If the DSP array group 52 is performing processing for wide aspect television broadcast reception in the previous field, the output of the state memory 66 and the detection pulse will be the same, and the FF 70 will not be reset by the output of the comparison circuit 67. Switches 76 and 77 cannot be switched. Therefore, the DSP array group 52 continues processing for wide aspect television broadcast reception.

On the other hand, when normal television broadcast reception processing is being performed in the previous field, the output of the state memory 66 and the detection pulse are different, and the comparison circuit 6
FF70 is set by the output of 7. In this case, the output of the offset generation circuit 68 is "b", and the ROM 51 is designated as a storage area for the wide aspect program. Switch 76,7 by FF70
7 is switched, and the wide aspect program from the ROM 51 is stored in the program memory 75 according to the address output from the address counter 71. When the final address of program memory 75 is written, FF70
The switches 76 and 77 are switched by ALE78.
is given a program for wide aspect reception from the program memory 75 in response to the address output from the program counter 79, and performs signal processing.

That is, in this case, the DSP array group 52 operates based on the flowchart of FIG. First, in step S11, the video signal input via the DSP group D1 is converted to Y by the DSP groups D1 and D2.
/C is separated. In the next step S12, the luminance signal component is subjected to three-dimensional filter processing by the DSP groups D5 and D9. As a result, the luminance signal Y1 multiplexed in the horizontal overscan portion and the luminance signal Y2 frequency multiplexed are separated.

In the next step S13, the luminance signal of the center portion of the screen and the luminance signal Y1 are reproduced. That is, the DSP groups D14 and D15 time-compress the luminance signal at the screen center by 3/4 times and return it to the original center signal, and time-expand the luminance signal Y1 at the screen side by 4 times and return it to the original side signal. . On the other hand, the luminance signal Y2 is frequency-shifted by the DSP group D13 using a subcarrier having a frequency of 6/5 fsc, and is further time-compressed by a factor of 1/2 (step S14). As a result, the signal of the screen side portion of the first field is reproduced.

Furthermore, the luminance signal from the DSP group D2 is
In step S15, the data is given to the DSP group D6 and rearranged, frequency-shifted by a 6/5 fsc subcarrier and further time-expanded by a factor of two by the DSP group D10. In this way, in step S15, the luminance signal of the screen side portion of the second field is reproduced. Next step S16
, luminance signals Y1, Y2, Y3 from DSP groups D15, D13, D10 are combined in DSP group D16 and
/A converter 96.

On the other hand, the color signals separated in step S11 are processed in steps S17 to S21. That is, the DSP group D3 separates the color difference signals I and Q from the color signals in step S17. In the next step S18,
By the DSP groups D4 and D8, similarly to the luminance signal,
A three-dimensional filter process is performed to separate the signals C1 and C2.

In the next step S19, the center signal is reproduced by the DSP groups D11 and D12 with time compression of 3/4 times. On the other hand, regarding the color difference signals I and Q of the side portion of the screen, in step S20, 1/7
The frequency is shifted using the fsc subcarrier, the time is compressed to 1/4, and the signal is combined with the signal at the center of the screen.

In the next step S21, the signals C1 and C2 obtained in steps S19 and S20 are combined and supplied to the D/A converter 95. The luminance signals and color difference signals from the D/A converters 96 and 95 are subjected to matrix processing by a matrix circuit 97. In this way, the R, G, and B signals of wide aspect broadcasting are supplied to the monitor 98, and an image with an aspect ratio of 16:9 is displayed on the display screen.

When the power is turned on, the FF 70 is set by a pulse from the power-on detection circuit 50, and a program corresponding to the presence or absence of the identification signal is transferred from the ROM 51 to the program memory 75.

In this way, in this embodiment, an identification signal is inserted at the broadcasting station, and this identification signal is detected by the identification signal detection circuit 48, so that the DSP array group 5
The program stored in the program memory 75 of each DSP of 2 is switched, and different video processing is automatically performed without user operation when the power is turned on or when the identification signal changes. That is, a predetermined image intended by the broadcasting station is displayed on the display screen of the terminal receiver.

FIG. 8 is a block diagram showing an identification signal detection circuit according to another embodiment of the present invention. In FIG. 8, the same components as those in FIG. 3 are given the same reference numerals, and their explanations will be omitted. This embodiment corresponds to the identification signal shown in FIG. Figure 9
As shown in the figure, a relatively wide pulse 131 and a relatively narrow pulse 13 are superimposed on the 263rd line of the video signal.
2 consecutively constitute the identification signal. When this video signal is sampled using a clock with a frequency of 8/5 fsc, the pulse 131 is “H” (“1”) for 3 clock periods.
, and after two clock periods "L"("0"), pulse 132 is "H" for one clock period.

Such a video signal is inputted to the sync separation circuit 61 and slice circuit 63 of the identification signal detection circuit 133 via the input terminal 60. Timing generation circuit 13
4 provides a latch pulse to the latch circuit 65, and also generates a clock having a frequency of 8/5 fsc and provides it to the shift register 135. The shift register 135 receives binary pulses sequentially from the slice circuit 63, and
By shifting with a clock of 5 fsc, a 7-bit code string obtained by sampling the video signal is generated and outputs Q1 to Q7 are output. shift register 135
The output of is given to the match number detection circuit 136. The match number detection circuit 136 is supplied with the data string "1110010", compares this data string with the output from the shift register 135, and provides the number of matching data (match number) to the comparator 137. The comparator 137 is supplied with data "6", subtracts the data "6" from the number of matches, and provides a positive or negative comparison result to the latch circuit 65. The latch circuit 65 latches the output of the comparator 137 at the timing of the latch pulse from the timing generating circuit 134 and outputs it from the output terminal 138.

Next, the operation of the embodiment configured as described above will be explained with reference to Table 1. Table 1 below shows the relationship between the Q1 to Q7 outputs of the shift register and the number of matches at timings A to P of each clock. Note that the first column of Table 1 shows each data of the data string "1110010" input to the match number detection circuit 136, and the underlines in Table 1 indicate each of these data and the output Q1 of the shift register. This shows agreement with Q7.

[0075]

[Table 1]

[0076]

In this embodiment, the identification signal inserted in the 263rd line of the video signal is sampled at an 8/5 fsc clock and converted into a bit string, similar to the teletext broadcasting currently being broadcast. As shown in Table 1, the pulse 131 of the identification signal is sampled for the first time at timing B, and the output Q of the shift register 135 is
1 becomes “1”. At this point, as is clear from the comparison between the first column of Table 1 and the timing B column, the number of matches is 2. Thereafter, clocks are sequentially generated from the timing generation circuit 134, and the outputs Q1 to Q7 of the shift register 135 change. For example, timing G
, the pulse 132 of the identification signal is sampled and the output Q1 becomes "1".

Comparator 137 receives data “6” from the number of matches.
is subtracted and a positive or negative comparison result is output. Therefore, when the number of matches reaches 7, the output of comparator 137 becomes positive. At timing H, the output Q1 of the shift register 135
Q7 to Q7 become "0100111", which matches all the data strings shown in the first column. As a result, the number of matches becomes 7, and the output of comparator 137 becomes positive. Then,
The detection pulse from the latch circuit 65 changes from "L" to "H".

At timings other than timing H, the number of matches is 4 or less, the comparison result of comparator 137 is negative, and the detection pulse is "L". Furthermore, when no identification signal is inserted into the video signal, the number of matches is always 3 and the detection pulse remains "L". In this way, the identification signal can be reliably detected.

In this embodiment, since the comparator 137 compares the number of matches with "6", even if the video signal is distorted due to noise in the signal transmission path, the outputs Q1 to Q7 of the shift register 135 If the number of errors is 1 or less, the identification signal will not be erroneously detected.

Other functions and effects are similar to those of the embodiment shown in FIG.

It should be noted that the present invention is not limited to the above-mentioned embodiments; for example, an example has been shown in which a program for receiving NTSC television broadcasting and a program for receiving wide aspect television broadcasting are switched, but other Programs can also be provided to the DSP to perform other signal processing. Furthermore, in the above embodiment, switching between two systems, the NTSC system and the wide aspect television system, was shown.
Increase the types of identification signals, increase the number of output bits of the match number detection circuit and shift register, make the output of the state memory multiple bits, provide multiple values output from the offset generation circuit, and store multiple programs in ROM. Multi-method identification and signal processing can be achieved by

[0083]

[Effects of the Invention] As explained above, according to the present invention, by making it possible to switch the processing of the arithmetic processing means using the identification signal inserted at the broadcasting station, the video intended by the broadcasting station can be displayed. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a television receiver according to the present invention.

FIG. 2 is a block diagram showing an encoder on the broadcasting station side.

[FIG. 3] Identification signal detection circuit 48 and load circuit 4 in FIG. 1
9. A block diagram showing a specific configuration of a power-on detection circuit 50, a ROM 51, and one DSP of the DSP array group 52.

FIG. 4 is an explanatory diagram showing an address map of the ROM 51 in FIG. 1.

5 is a timing chart for explaining the operation of the identification signal detection circuit 48 in FIG. 1. FIG.

FIG. 6 is a flowchart for explaining the operation of the embodiment.

FIG. 7 is a flowchart for explaining the operation of the embodiment.

FIG. 8 is a block diagram showing an identification signal detection circuit according to another embodiment of the present invention.

FIG. 9 is a waveform diagram showing an identification signal.

FIG. 10 is a block diagram for explaining a digital signal processor.

FIG. 11 is a block diagram for explaining a digital signal processor.

FIG. 12 is a block diagram for explaining a digital signal processor.

FIG. 13 is a block diagram for explaining a digital signal processor.

FIG. 14 is an explanatory diagram for explaining a digital signal processor.

[Explanation of symbols]

48...Identification signal detection circuit 49...Load circuit 51...ROM 52...DSP array group

Claims (2)

[Claims] 1. Receiving means for receiving a video signal from a transmitting side into which an identification signal can be inserted at a predetermined timing; a first program memory storing a plurality of programs for signal processing the video signal; a possible second program memory; arithmetic processing means for video processing the received video signal based on a program read from the second program memory; and separation of a synchronization signal from the video signal received by the receiving means. a synchronization separation circuit, a timing generation circuit that uses the synchronization signal to generate a timing signal indicating a predetermined timing at which the identification signal is inserted, and detects the identification signal from the received video signal at the timing of the timing signal. and a loading means for storing a program loaded from the first program memory into the second program memory based on the detection pulse. television receiver. 2. The television receiver according to claim 1, wherein the identification signal detection means detects an identification signal composed of a digital code.