JP3452011B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP3452011B2
JP3452011B2 JP2000027318A JP2000027318A JP3452011B2 JP 3452011 B2 JP3452011 B2 JP 3452011B2 JP 2000027318 A JP2000027318 A JP 2000027318A JP 2000027318 A JP2000027318 A JP 2000027318A JP 3452011 B2 JP3452011 B2 JP 3452011B2
Authority
JP
Japan
Prior art keywords
heat sink
heat
insulating substrate
semiconductor device
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000027318A
Other languages
Japanese (ja)
Other versions
JP2001217363A (en
Inventor
隆一 齋藤
保夫 近藤
潤也 金田
清光 鈴木
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Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000027318A priority Critical patent/JP3452011B2/en
Publication of JP2001217363A publication Critical patent/JP2001217363A/en
Application granted granted Critical
Publication of JP3452011B2 publication Critical patent/JP3452011B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置、及び
半導体装置用ヒートシンクに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a heat sink for a semiconductor device.

【０００２】[0002]

【従来の技術】電子デバイスによる電力やエネルギーの
変換，制御に関連した技術、特にオン，オフモードで用
いられる電力用電子デバイスとその応用技術としての電
力変換システムがパワーエレクトロニクスシステムであ
る。2. Description of the Related Art A technique related to conversion and control of electric power and energy by an electronic device, in particular, a power electronic device used in an on / off mode and a power conversion system as its application technique is a power electronic system.

【０００３】電力変換のため、各種のオン，オフ機能を
持つ電力用半導体素子が用いられている。この半導体素
子としては、ｐｎ接合体を内蔵し、一方向のみの導電性
をもつ整流ダイオードをはじめ、種々のｐｎ接合の組合
せ構造により、サイリスタ，バイポーラトランジスタ，
ＭＯＳＦＥＴ等が実用化され、更には絶縁ゲート型バイ
ポーラトランジスタ（ＩＧＢＴ）やゲート信号によりタ
ーンオフ機能を併せもつゲートターンオフサイリスタ
（ＧＴＯ）も開発されている。For power conversion, power semiconductor elements having various on / off functions are used. As this semiconductor element, a thyristor, a bipolar transistor, a rectifier diode having a built-in pn junction and having conductivity in only one direction, a thyristor, a bipolar transistor,
MOSFET and the like have been put to practical use, and further, an insulated gate bipolar transistor (IGBT) and a gate turn-off thyristor (GTO) having a turn-off function by a gate signal have also been developed.

【０００４】これらの電力用半導体素子は、通電により
発熱し、その高容量化，高速化に伴い発熱量も増大する
傾向にある。発熱に起因する半導体素子の特性劣化，短
寿命化を防止するためには、放熱部を設け、半導体素子
及びその近傍での温度上昇を抑制する必要がある。銅
は、熱伝導率が３９３Ｗ／ｍ・Ｋと大きく、かつ低価格
であるため、放熱部材として一般に用いられている。し
かし、電力用半導体素子を備える半導体装置の放熱部材
は、熱膨張率が４.２×１０-6／℃のＳｉと接合される
ため、熱膨張率がこれに近い放熱部材が望まれる。銅は
熱膨張率が１７×１０-6／℃と大きいため、半導体素子
との半田接合性は好ましくなく、ＭｏやＷといった熱膨
張率がＳｉと近い材料を放熱部材として用いたり、半導
体素子と放熱部材の間に設けたりしている。These power semiconductor elements generate heat when energized, and the amount of heat generation tends to increase as their capacity and speed increase. In order to prevent the deterioration of the characteristics of the semiconductor element and the shortening of the life due to heat generation, it is necessary to provide a heat radiating portion to suppress the temperature rise in the semiconductor element and its vicinity. Copper has a large thermal conductivity of 393 W / m · K and is low in price, and is generally used as a heat dissipation member. However, since a heat dissipation member of a semiconductor device including a power semiconductor element is bonded to Si having a thermal expansion coefficient of 4.2 × 10 −6 / ° C., a heat dissipation member having a thermal expansion coefficient close to this is desired. Since copper has a large coefficient of thermal expansion of 17 × 10 −6 / ° C., its solderability to a semiconductor element is not preferable, and a material having a coefficient of thermal expansion similar to Si such as Mo or W is used as a heat dissipation member, It is also provided between the heat dissipation members.

【０００５】一方、電子回路を一つの半導体チップ上に
集積させた集積回路（ＩＣ）は、その機能に応じたメモ
リー，ロジック，マイクロプロセッサ等に分類される。
ここでは電力用半導体素子に対し、電子用半導体素子と
呼ぶ。これらの半導体素子は、年々集積度や演算速度が
増加し、それに伴い発熱量も増大している。ところで、
一般に電子用半導体素子は、外気から遮断して故障や劣
化を防止する目的で、パッケージ内に収納されている。
この多くは、半導体素子がセラミックスにダイボンディ
ングされ、密封されているセラミックスパッケージ及び
樹脂で封止されているプラスチックパッケージである。
また、高信頼性，高速化に対応するために、複数個の半
導体装置を一つの基板上に搭載したマルチチップモジュ
ール（ＭＣＭ）も製造されている。On the other hand, integrated circuits (ICs) in which electronic circuits are integrated on one semiconductor chip are classified into memories, logics, microprocessors and the like according to their functions.
Here, the power semiconductor element is referred to as an electronic semiconductor element. The integration degree and the operation speed of these semiconductor elements are increasing year by year, and accordingly, the amount of heat generation is also increasing. by the way,
Generally, an electronic semiconductor device is housed in a package for the purpose of shutting off from outside air and preventing failure or deterioration.
Most of these are a ceramic package in which a semiconductor element is die-bonded to a ceramic and sealed, and a plastic package in which a resin is sealed.
In addition, a multi-chip module (MCM) in which a plurality of semiconductor devices are mounted on one substrate is manufactured in order to cope with high reliability and high speed.

【０００６】プラスチックパッケージは、リードフレー
ムと半導体素子の端子がボンディングワイヤにより接続
され、これを樹脂で封止する構造になっている。近年
は、半導体素子の発熱量の増大に伴い、リードフレーム
に熱放散性を持たせたパッケージや熱放散のための放熱
板を搭載するパッケージも出現している。熱放散のため
には、熱伝導率の大きい銅系のリードフレームや放熱板
が多用されているが、Ｓｉとの熱膨張差による不具合が
懸念されている。The plastic package has a structure in which the lead frame and the terminal of the semiconductor element are connected by a bonding wire and this is sealed with resin. 2. Description of the Related Art In recent years, as the amount of heat generated by a semiconductor element increases, a package in which a lead frame has heat dissipation properties and a package in which a heat dissipation plate for heat dissipation are mounted have also appeared. For heat dissipation, a copper-based lead frame and a heat dissipation plate, which have high thermal conductivity, are often used, but there is a concern about a problem due to a difference in thermal expansion from Si.

【０００７】一方、セラミックスパッケージは、配線が
プリントされたセラミック基板上に半導体素子が搭載さ
れ、金属やセラミックのキャップで密封する構造を持
つ。さらに、セラミック基板にはＣｕ−ＭｏやＣｕ−Ｗ
の複合材料あるいはコバール合金などが接合され、放熱
板として用いられているが、それぞれの材料において低
熱膨張化あるいは高熱伝導化とともに加工性の向上，低
コストが要求されている。On the other hand, the ceramic package has a structure in which a semiconductor element is mounted on a ceramic substrate on which wiring is printed and sealed with a metal or ceramic cap. Furthermore, Cu-Mo and Cu-W are used for the ceramic substrate.
These composite materials or Kovar alloy are joined and used as a heat dissipation plate, but each material is required to have low thermal expansion or high thermal conductivity as well as improved workability and low cost.

【０００８】ＭＣＭはＳｉ，金属、あるいはセラミック
スの基板上に形成された薄膜配線に複数個の半導体素子
をベアチップで搭載し、これをセラミックスパッケージ
に入れ、リッドで封止する構造を持つ。放熱性が要求さ
れる場合には、パッケージに放熱板や放熱フィンを設置
する。金属製の基板材料として、銅やアルミニウムが使
用されており、これらは熱伝導度が高いという長所を持
つが、熱膨張係数が大きく半導体素子との整合性が悪
い。このため、高信頼性ＭＣＭの基板にはＳｉや窒化ア
ルミニウム（ＡｌＮ）が用いられている。また、放熱板
はセラミックスパッケージと接合されるため、熱膨張率
の点でパッケージ材料と整合性が良く、熱伝導率が大き
な材料が望まれている。The MCM has a structure in which a plurality of semiconductor elements are mounted as bare chips on a thin film wiring formed on a substrate of Si, metal, or ceramics, which are placed in a ceramics package and sealed with a lid. When heat dissipation is required, a heatsink or heatsink is installed on the package. Copper and aluminum are used as the metal substrate material, and they have the advantage of high thermal conductivity, but have a large coefficient of thermal expansion and poor compatibility with semiconductor devices. Therefore, Si or aluminum nitride (AlN) is used for the substrate of the highly reliable MCM. Further, since the heat dissipation plate is bonded to the ceramics package, a material having good compatibility with the package material in terms of thermal expansion coefficient and high thermal conductivity is desired.

【０００９】以上のように、半導体素子を搭載した半導
体装置は、いずれもその動作において熱を発生し、素子
温度が上昇すると半導体素子の機能を損ねる恐れがあ
る。このため、発生する熱を外部に放散するための熱伝
導性に優れた放熱板等の放熱部分が必要となる。放熱板
は、直接あるいは絶縁層を介して半導体素子と接合され
るため、熱伝導性だけでなく、熱膨張の点でも半導体素
子との整合性が要求される。As described above, any semiconductor device having a semiconductor element generates heat during its operation, and there is a possibility that the function of the semiconductor element may be impaired if the element temperature rises. Therefore, a heat radiating portion such as a heat radiating plate having excellent thermal conductivity for radiating generated heat to the outside is required. Since the heat dissipation plate is bonded to the semiconductor element directly or through the insulating layer, not only the thermal conductivity but also the consistency with the semiconductor element is required in terms of thermal expansion.

【００１０】現在用いられている半導体素子は、主にＳ
ｉ及びＧａＡｓである。これらの熱膨張係数は、それぞ
れ２.６×１０-6〜３.６×１０-6／℃，５.７×１０-6
〜６.９×１０-6／℃である。これらに近い熱膨張係数
をもつ放熱板材料には、従来よりＡｌＮ，ＳｉＣ，Ｍ
ｏ，Ｗ，Ｃｕ−Ｗ等が知られているが、これらは単一材
料であるため、熱伝達係数と熱伝導率を任意にコントロ
ールすることは困難であるとともに、加工性に乏しくコ
ストが高いという問題がある。そこで特開平8−78578号
公報にはＣｕ−Ｍｏ焼結合金、特開平9−181220 号公報
にはＣｕ−Ｗ−Ｎｉ焼結合金、特開平9−209058 号公報
にはＣｕ−ＳｉＣ焼結合金、特開平9−15773号公報には
Ａｌ−ＳｉＣが提案されている。さらに、接合材料とし
て主に用いられる半田を省略して放熱板やセラミックス
絶縁基板とを直接接合することにより、組立てを容易に
し、熱抵抗を低減したセラミック絶縁基板−放熱板直接
接合構造について、１９９６年国際パワーコンバージョ
ン会議（ＰＣＩＭ‘９６Europe）予稿集６８３ページに
て提案されている。Currently used semiconductor elements are mainly S
i and GaAs. These thermal expansion coefficients, respectively 2.6 × 10 -6 ~3.6 × 10 -6 /℃,5.7×10 -6
˜6.9 × 10 −6 / ° C. Heat sink materials with a thermal expansion coefficient close to those of AlN, SiC, M
O, W, Cu-W, etc. are known, but since these are single materials, it is difficult to arbitrarily control the heat transfer coefficient and the thermal conductivity, and the workability is poor and the cost is high. There is a problem. Therefore, JP-A-8-78578 discloses a Cu-Mo sintered alloy, JP-A-9-181220 discloses a Cu-W-Ni sintered alloy, and JP-A-9-209058 discloses a Cu-SiC sintered alloy. JP-A-9-15773 proposes Al-SiC. Further, regarding a ceramic-insulating-substrate-radiating-plate direct-bonding structure that facilitates assembly by directly joining a radiating plate and a ceramics insulating substrate by omitting solder that is mainly used as a bonding material, 1996 Proposed in 683 pages of the Annual International Power Conversion Conference (PCIM'96 Europe).

【００１１】[0011]

【発明が解決しようとする課題】前記の従来公知の複合
材は、両成分の比率を変えることによって熱伝達係数及
び熱伝導率を広範囲にコントロールできるが、塑性加工
性が低く、薄板の製造が困難であり、更に製造工程が多
くなるものである。このため前記のセラミック絶縁基板
−放熱板直接接合構造についても製造工程が多くなり、
また、所望の形状によって低熱抵抗性を付与することが
困難であった。また、前記公知の複合材料放熱板とセラ
ミック絶縁基板との直接接合部位の高信頼化に適した構
造についても明確ではなかった。また、前記公知の構造
では半導体装置の低熱抵抗化に限界があった。The above-mentioned conventionally known composite material can control the heat transfer coefficient and the thermal conductivity in a wide range by changing the ratio of both components, but has a low plastic workability and is not suitable for the production of a thin plate. It is difficult and the number of manufacturing steps is increased. Therefore, the number of manufacturing steps also increases for the above-mentioned ceramic insulating substrate-heat sink direct bonding structure,
Further, it is difficult to impart low heat resistance with a desired shape. Further, the structure suitable for improving the reliability of the directly-bonded portion between the publicly known composite heat sink and the ceramic insulating substrate has not been clarified. Further, the known structure has a limit in reducing the thermal resistance of the semiconductor device.

【００１２】[0012]

【課題を解決するための手段】本発明は上記の課題を考
慮してなされたものである。The present invention has been made in consideration of the above problems.

【００１３】本発明に係るセラミック絶縁基板−放熱板
直接接合構造ヒートシンク及びこれを用いた半導体装置
は、放熱板材料が金属と該金属よりも熱膨張係数が小さ
い無機化合物粒子とを有し、前記化合物粒子は断面の面
積率が前記粒子の全体の９５％以上が互いに連なった複
雑形状の塊となって分散していることを特徴とする。In the heat sink of the ceramic insulating substrate-radiating plate direct joining structure and the semiconductor device using the same according to the present invention, the radiator plate material includes a metal and inorganic compound particles having a thermal expansion coefficient smaller than that of the metal. The compound particles are characterized in that the area ratio of the cross-section is 95% or more of the whole particles and dispersed as a complex-shaped mass that is continuous with each other.

【００１４】本発明に係るセラミック絶縁基板−放熱板
直接接合構造ヒートシンク及びこれを用いた半導体装置
は、放熱板材料が金属と該金属よりも熱膨張係数が小さ
い無機化合物粒子とを有し、前記化合物粒子は単独で存
在する粒子の数が断面で100μｍ四方内に１００個以下
であり、残りの前記化合物粒子は互いに連なった複雑形
状の塊となって分散していることを特徴とする。In the heat sink of the ceramic insulating substrate-radiating plate direct bonding structure and the semiconductor device using the same according to the present invention, the radiation plate material has a metal and inorganic compound particles having a thermal expansion coefficient smaller than that of the metal. The compound particles are characterized in that the number of particles present independently is 100 or less in a 100 μm square in a cross section, and the remaining compound particles are dispersed as a complex-shaped mass that is continuous with each other.

【００１５】本発明に係るセラミック絶縁基板−放熱板
直接接合構造ヒートシンクは、放熱板材料が金属と該金
属よりも熱膨張係数が小さい無機化合物粒子とを有し、
前記化合物粒子はヴィッカース硬さが３００以下である
ことを特徴とする。In the heat sink of the ceramic insulating substrate-radiating plate direct joining structure according to the present invention, the radiating plate material includes a metal and inorganic compound particles having a thermal expansion coefficient smaller than that of the metal.
The compound particles have a Vickers hardness of 300 or less.

【００１６】本発明に係るセラミック絶縁基板−放熱板
直接接合構造ヒートシンク及びこれを用いた半導体装置
は、放熱板材料が金属と該金属よりも熱膨張係数が小さ
い無機化合物粒子とを有し、２０℃での熱伝導率１ｗ／
ｍ・Ｋ当りの２０〜１５０℃での平均熱膨張係数の増加
率が０.０２５〜０.０３５ppm／℃ であることを特徴と
する。In the heat sink of the ceramic insulating substrate-radiating plate direct joining structure and the semiconductor device using the same according to the present invention, the radiating plate material has a metal and inorganic compound particles having a thermal expansion coefficient smaller than that of the metal. Thermal conductivity at ℃ 1w /
It is characterized in that the rate of increase of the average coefficient of thermal expansion per m · K at 20 to 150 ° C is 0.025 to 0.035 ppm / ° C.

【００１７】本発明に係るセラミック絶縁基板−放熱板
直接接合構造ヒートシンク及びこれを用いた半導体装置
は、放熱板材料が金属と該金属よりも熱膨張係数が小さ
い無機化合物粒子とを有し、前記化合物粒子は互いに連
なり塊となって分散しており、前記塊は塑性加工によっ
て伸ばされた方向に延びていることを特徴とする。In the heat sink and the semiconductor device using the ceramic insulating substrate-radiating plate direct joining structure according to the present invention, the radiating plate material has a metal and inorganic compound particles having a thermal expansion coefficient smaller than that of the metal. The compound particles are continuous with each other and dispersed as a lump, and the lump extends in the direction in which it is stretched by plastic working.

【００１８】本発明に係るセラミック絶縁基板−放熱板
直接接合構造ヒートシンク及びこれを用いた半導体装置
は、放熱板材料が銅と酸化銅粒子とを有し、前記酸化銅
粒子は断面の面積率で前記粒子の全体の９５％以上が互
いに連なった複雑形状の塊となって分散していることを
特徴とする。In the heat sink and the semiconductor device using the ceramic insulating substrate-radiation plate direct bonding structure according to the present invention, the heat radiation plate material has copper and copper oxide particles, and the copper oxide particles have a cross-sectional area ratio. It is characterized in that 95% or more of the entire particles are dispersed in the form of a lump having a complicated shape that is continuous with each other.

【００１９】本発明に係るセラミック絶縁基板−放熱板
直接接合構造ヒートシンク及びこれを用いた半導体装置
は、セラミック絶縁基板の表裏面には配線パターンが形
成された表面金属層及び裏面金属層が接合されている構
造であることを特徴とする。In the ceramic insulating substrate-radiating plate direct joining structure heat sink and the semiconductor device using the same according to the present invention, the front and back surfaces of the ceramic insulating substrate are joined to the front metal layer and the back metal layer having the wiring pattern formed thereon. It is characterized by the structure.

【００２０】本発明に係るセラミック絶縁基板−放熱板
直接接合構造ヒートシンク及びこれを用いた半導体装置
は、セラミック絶縁基板表裏面金属層が銅よりなり、裏
面銅金属層と銅と酸化銅粒子とからなる放熱板は固着接
合されていることを特徴とする。A ceramic insulating substrate-radiating plate direct joining structure heat sink according to the present invention and a semiconductor device using the same include a ceramic insulating substrate having a front and back metal layer made of copper, and a back copper metal layer, copper and copper oxide particles. The heat radiating plate is fixedly joined.

【００２１】本発明に係るセラミック絶縁基板−放熱板
直接接合構造ヒートシンク及びこれを用いた半導体装置
は、セラミック絶縁基板の表面には配線パターンが形成
された表面金属層が接合され、セラミック裏面には金属
層が接合されておらず放熱板と直接接合されている構造
であることを特徴とする。The ceramic insulating substrate-radiating plate direct joining structure heat sink according to the present invention and the semiconductor device using the same include a surface metal layer having a wiring pattern formed on the surface of the ceramic insulating substrate and a ceramic back surface on the back surface of the ceramic. The structure is characterized in that the metal layer is not bonded and is directly bonded to the heat dissipation plate.

【００２２】本発明に係るセラミック絶縁基板−放熱板
直接接合構造ヒートシンク及びこれを用いた半導体装置
は、放熱板内部に冷媒を通す空隙が設けられていること
を特徴とする。さらに、放熱板内部に設けられた冷媒を
通すための空隙は板厚方向に平行な薄い放熱部フィンと
フィン空隙が繰り返し配置されたものであって、放熱部
フィン厚さとフィン空隙間隔の少なくともいずれかは２
mm以下であり、好ましくは１mm以下であることを特徴と
する。さらに、半導体装置の放熱板には冷媒を注入，排
出する接続口が設けられていることを特徴とする。A ceramic insulating substrate-radiating plate direct joint structure heat sink and a semiconductor device using the same according to the present invention are characterized in that a gap is formed inside the radiating plate for passing a coolant. Further, the space provided inside the heat dissipation plate for passing the refrigerant is formed by repeatedly arranging thin heat dissipation part fins and fin spaces parallel to the plate thickness direction, and at least one of the heat dissipation part fin thickness and the fin space. Or 2
It is characterized in that it is less than or equal to mm, and preferably less than or equal to 1 mm. Further, the heat dissipation plate of the semiconductor device is provided with a connection port for injecting and discharging the refrigerant.

【００２３】本発明に係るセラミック絶縁基板−放熱板
直接接合構造ヒートシンク及びこれを用いた半導体装置
は、放熱板裏面に空冷フィンが設けられていることを特
徴とする。さらに、放熱板裏面に設けられた空冷フィン
は板厚方向に平行な薄いフィンが繰り返し配置されたも
のであって、フィン厚さとフィン間隔の少なくともいず
れかは２mm以下であり、好ましくは１mm以下であること
を特徴とする。The heat sink of the ceramic insulating substrate-radiation plate direct joining structure and the semiconductor device using the same according to the present invention are characterized in that air cooling fins are provided on the back surface of the heat radiation plate. Further, the air-cooling fins provided on the back surface of the heat sink are thin fins arranged parallel to the plate thickness direction repeatedly, and at least one of the fin thickness and the fin interval is 2 mm or less, preferably 1 mm or less. It is characterized by being.

【００２４】本発明のセラミック絶縁基板−放熱板直接
接合構造ヒートシンク及びこれを用いた半導体装置の放
熱板材料として、銅と酸化銅粒子から構成される前記の
ごとき材料を用いることにより、セラミック絶縁基板と
放熱板の熱膨張係数差を小さくすることができるため、
温度変化時のセラミック絶縁基板−放熱板直接接合部分
やセラミックへの熱応力を低減でき、接続信頼性が高く
なる。また、温度変化時のそりも低減できる。さらに、
銅と酸化銅粒子から構成される材料ではヴィッカース硬
さが３００以下であるため、セラミック絶縁基板と放熱
板の熱膨張係数差が無視できない値である場合において
も銅と酸化銅粒子から構成される放熱板が変形すること
により熱応力が緩和され、直接接合部分やセラミックの
劣化が避けられる。これと同時に前記材料の熱伝導率が
高いため放熱性能が高い。Ceramic Insulating Substrate-Radiation Plate Direct Bonding Structure of the Present Invention A ceramic insulating substrate is obtained by using the above-mentioned material composed of copper and copper oxide particles as a heat sink of a heat sink and a semiconductor device using the same. Since the difference in thermal expansion coefficient between the heat sink and the heat sink can be reduced,
When the temperature changes, the thermal stress on the ceramic insulating substrate-heat sink direct joint part and the ceramic can be reduced, and the connection reliability is improved. In addition, warpage when the temperature changes can be reduced. further,
Since the material composed of copper and copper oxide particles has a Vickers hardness of 300 or less, it is composed of copper and copper oxide particles even when the difference in thermal expansion coefficient between the ceramic insulating substrate and the heat dissipation plate is not negligible. Deformation of the heat sink relieves thermal stress and avoids deterioration of the direct joint portion and ceramics. At the same time, the heat conductivity of the material is high, so that the heat dissipation performance is high.

【００２５】また、本発明のセラミック絶縁基板−放熱
板直接接合構造ヒートシンク及びこれを用いた半導体装
置のセラミック絶縁基板は、銅等の金属からなる金属層
を表裏面に有し、裏面銅金属層と銅と酸化銅粒子とから
なる放熱板が固着接合されていることにより接合強度は
著しく強固になり、接続信頼性が向上する。Further, the ceramic insulating substrate-radiating plate direct joining structure heat sink of the present invention and the ceramic insulating substrate of the semiconductor device using the same have the metal layers made of metal such as copper on the front and back surfaces, and the back surface copper metal layer. Since the heat radiating plate made of copper and copper oxide particles is fixedly joined, the joining strength is remarkably strengthened, and the connection reliability is improved.

【００２６】また、本発明のセラミック絶縁基板−放熱
板直接接合構造ヒートシンク及びこれを用いた半導体装
置の放熱板は、放熱板内部に水などの冷媒を通すための
冷却フィンまたは裏面に空冷フィンを設けているため効
率的な放熱が可能となる。とりわけ銅と酸化銅粒子から
構成される前記のごとき材料を用いているため加工性が
容易なことから、放熱部フィン厚さとフィン空隙間隔の
少なくともいずれかは２mm以下であり、好ましくは１mm
以下にすることが容易なため熱伝達率の高いフィンが形
成でき、放熱性能をさらに高くすることができる。Further, the heat sink of the ceramic insulating substrate-radiating plate direct joint structure of the present invention and the heat radiating plate of the semiconductor device using the same have cooling fins for passing a coolant such as water inside the heat radiating plate or air cooling fins on the back surface. Since it is provided, efficient heat dissipation is possible. In particular, since the above-mentioned materials composed of copper and copper oxide particles are used, the workability is easy. Therefore, at least one of the fin thickness of the heat radiation part and the fin gap is 2 mm or less, preferably 1 mm.
Since it is easy to make the following, it is possible to form a fin having a high heat transfer rate, and it is possible to further improve the heat dissipation performance.

【００２７】また、放熱板内部に水などの冷媒を通すた
めの冷却部を設けてあって、放熱板には冷媒を注入，排
出する接続口が設けられているため電力変換装置の構成
が容易である。Further, since a cooling portion for passing a coolant such as water is provided inside the heat radiating plate, and the heat radiating plate is provided with a connection port for injecting and discharging the coolant, the construction of the power conversion device is easy. Is.

【００２８】[0028]

【発明の実施の形態】本発明の実施例を以下図面を用い
て説明する。 （実施例１）図１は本発明に係る半導体装置の断面図で
あり、例えばパワー半導体モジュールである。半導体素
子１０１は例えばＩＧＢＴやパワーＭＯＳであり、セラ
ミック絶縁基板１０９，放熱板１１０上に搭載されてい
る。半導体素子１０１の裏面は半田などの接合材１０２
によってセラミック絶縁基板１０９上の表面金属配線パ
ターン１０６に接続されている。チップ表面側はＡｌ等
からなる太線ワイヤ１０３によってチップ表面電極とセ
ラミック絶縁基板上の金属配線パターン111が接続され
るといった公知の構造となっている。チップ表面はゲル
やモールドレジン１０５によりコーティングされ、各電
極端子は外部引き出し端子に接続され、これらはプラス
チック製のケース１０４内に実装されている。本発明に
おいては、これらのモールドレジン１０５とケース１０
４が一体材料で構成されたトランスファモールド構造で
もよい。このようなパワー半導体モジュールが熱伝導グ
リース等を介して電力変換器の共通ヒートシンク上に実
装され、適宜配線バーを接続することにより電力変換装
置が構成されている。本実施例の特徴の一つとするとこ
ろはパワー半導体モジュールの裏面側で放熱を行う部分
の構造に関するものである。すなわち、セラミック絶縁
基板１０９裏面の金属層１０７は放熱板１１０に直接接
合され一体化直接接合構造ヒートシンクとなっている。
すなわちセラミック絶縁基板１０９裏面の金属層１０７
と放熱板１１０の間には接合材としての半田はなく接合
界面１０８で直接接合している。セラミック絶縁基板10
9は例えばＡｌＮからなり、表裏面には例えばＣｕから
なる金属層１０６，１１１，１０７があらかじめ銀ロー
などの公知の方法で接合されている。裏面Ｃｕ金属層１
０７の表面にはＮｉ等の通常用いられるメッキ層はな
い。放熱板１１０はＣｕとＣｕ2Ｏ粒子から構成されて
おり、従って熱処理を施すことによってＣｕ金属層１０
７と金属接合を形成し、強固な直接接合部位１０８を構
成している。Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a sectional view of a semiconductor device according to the present invention, for example, a power semiconductor module. The semiconductor element 101 is, for example, an IGBT or a power MOS, and is mounted on the ceramic insulating substrate 109 and the heat sink 110. The back surface of the semiconductor element 101 is a bonding material 102 such as solder.
Is connected to the surface metal wiring pattern 106 on the ceramic insulating substrate 109. The chip surface side has a known structure in which the chip surface electrode and the metal wiring pattern 111 on the ceramic insulating substrate are connected by a thick wire 103 made of Al or the like. The chip surface is coated with gel or mold resin 105, each electrode terminal is connected to an external lead terminal, and these are mounted in a plastic case 104. In the present invention, these mold resin 105 and case 10 are used.
A transfer mold structure in which 4 is made of an integral material may be used. Such a power semiconductor module is mounted on a common heat sink of a power converter via a heat conductive grease or the like, and a wiring bar is appropriately connected to form a power converter. One of the features of the present embodiment relates to the structure of the portion that radiates heat on the back surface side of the power semiconductor module. That is, the metal layer 107 on the back surface of the ceramic insulating substrate 109 is directly bonded to the heat dissipation plate 110 to form an integrated direct bonding heat sink.
That is, the metal layer 107 on the back surface of the ceramic insulating substrate 109
There is no solder as a bonding material between the heat dissipation plate 110 and the heat dissipation plate 110, and they are directly bonded at the bonding interface 108. Ceramic insulating substrate 10
9 is made of, for example, AlN, and metal layers 106, 111, 107 made of, for example, Cu are joined to the front and back surfaces in advance by a known method such as silver brazing. Back side Cu metal layer 1
There is no Ni or other commonly used plating layer on the surface of 07. The heat radiating plate 110 is composed of Cu and Cu 2 O particles, and therefore, by heat treatment, the Cu metal layer 10 is formed.
7 and a metal joint are formed to form a strong direct joint portion 108.

【００２９】ここで、放熱板材料についてさらに詳述す
る。放熱板１１０は熱膨張係数が１５×１０-6／℃以
下、熱伝導率が１３０Ｗ／ｍ・Ｋ、ヴィッカース硬度が
300以下である。材料は、例えば銅（Ｃｕ）と第一酸化
銅（Ｃｕ2Ｏ）との複合材からなる。特に、放熱板材料
は、Ｃｕ2Ｏを２０〜８０体積％含むＣｕ合金からな
り、前記Ｃｕ2Ｏ 相及びＣｕ相がそれぞれ分散した組織
を有し、室温から３００℃における熱膨張係数が５×１
０-6〜１４×１０-6／℃及び熱伝導率が３０〜３２５Ｗ
／ｍ・Ｋであるものが好ましい。表１に本材料の組成に
対する熱膨張係数と熱伝導率を示している。Ｃｕ2Ｏ の
含有率が３０ｗｔ％の場合は熱膨張係数が１３×１０-6
／℃以下、熱伝導率が２３０Ｗ／ｍ・Ｋ、ヴィッカース
硬度が３００以下であり、Ｃｕ2Ｏ含有率が４０ｗｔ％
の場合は熱膨張係数が１１×１０-6／℃以下、熱伝導率
が１８０Ｗ／ｍ・Ｋ、ヴィッカース硬度が３００以下で
ある。また、ＣｕとＡｌ2Ｏ3の複合材，ＣｕとＳｉＯ2
の複合材、あるいはＣｕとＣｕ2ＯとＡｌ2Ｏ3の複合材
など、上記の数値範囲を満たすものであるならばどのよ
うな材質でもかまわない。図１０は熱伝導率(ｘ）と熱
膨張係数(ｙ）との関係を示す線図である。図中のＮｏ
はサンプルＮｏである。これらの関係はｙ＝０.０３１
ｘ＋４.６５ によって求められる値以上で、ｙ＝０.０
３１ｘ＋５.９５で求められる値以下となる。従って、
傾斜は２０℃の熱伝導率１Ｗ／ｍ・Ｋ当りの２０〜２５
０℃での平均熱膨張係数として０.０２５〜０.０３５pp
m／℃ とするものが好ましい。Here, the heat dissipation plate material will be described in more detail. The heat sink 110 has a coefficient of thermal expansion of 15 × 10 −6 / ° C. or less, a thermal conductivity of 130 W / m · K, and a Vickers hardness.
It is less than 300. The material is, for example, a composite material of copper (Cu) and cuprous oxide (Cu 2 O). In particular, the heat radiating plate material is made of Cu alloy containing Cu 2 O 20 to 80% by volume, has the Cu 2 O phase and Cu phase is dispersed respectively tissue, thermal expansion coefficient of 5 × at 300 ° C. from room temperature 1
0 −6 to 14 × 10 −6 / ° C. and thermal conductivity of 30 to 325 W
It is preferably / m · K. Table 1 shows the coefficient of thermal expansion and the thermal conductivity with respect to the composition of this material. When the Cu 2 O content is 30 wt%, the coefficient of thermal expansion is 13 × 10 −6
/ ° C or less, thermal conductivity is 230 W / mK, Vickers hardness is 300 or less, and Cu 2 O content is 40 wt%
In the case of, the coefficient of thermal expansion is 11 × 10 −6 / ° C. or less, the thermal conductivity is 180 W / m · K, and the Vickers hardness is 300 or less. Also, a composite material of Cu and Al 2 O 3 , Cu and SiO 2
Any material may be used as long as it satisfies the above numerical range, such as a composite material of No. 2 or a composite material of Cu, Cu 2 O and Al 2 O 3 . FIG. 10 is a diagram showing the relationship between the thermal conductivity (x) and the thermal expansion coefficient (y). No in the figure
Is a sample No. These relationships are y = 0.031
x = 4.65 or more, and y = 0.0
It is less than or equal to the value obtained by 31x + 5.95. Therefore,
The slope is 20 to 25 per 20 ° C thermal conductivity 1 W / m · K
As an average coefficient of thermal expansion at 0 ° C, 0.025 to 0.035 pp
It is preferably m / ° C.

【００３０】前記Ｃｕ2Ｏの結晶粒は放熱板１１０の厚
さ方向に平行に配向されていることが望ましい。すなわ
ち、Ｃｕ2Ｏを２０〜８０体積％含み、前記Ｃｕ2Ｏ相及
びＣｕ相が配向した組織を有し、室温から３００℃にお
ける熱膨張係数が５×10-6〜１４×１０-6／℃であり、
また熱伝導率が３０〜３２５Ｗ／ｍ・Ｋで、かつ配向方
向の熱伝導率が配向方向に直角な方向の２倍以上とする
ものが好ましい。配向した組織とするには例えば鍛造法
が用いられる。表２は、レーザーフラッシュ法による熱
伝導率の測定結果を示すが、鍛造しない焼結のままの状
態では、熱伝導率の異方性は認められない。しかし、鍛
造することによって異方性が生じ、Ｃｕ相及びＣｕ2Ｏ
相の配向方向（鍛伸方向）に対して平行なＬ方向の熱伝
導率は、それに直角なＣ方向（鍛造方法）の２倍以上の
値を示している。The Cu 2 O crystal grains are preferably oriented parallel to the thickness direction of the heat sink 110. That is, it has a structure in which Cu 2 O is contained in an amount of 20 to 80% by volume, the Cu 2 O phase and the Cu phase are oriented, and the coefficient of thermal expansion from room temperature to 300 ° C. is 5 × 10 −6 to 14 × 10 −6 / ℃,
Further, it is preferable that the thermal conductivity is 30 to 325 W / m · K and the thermal conductivity in the orientation direction is at least twice as high as that in the direction perpendicular to the orientation direction. For example, a forging method is used to form an oriented structure. Table 2 shows the measurement results of the thermal conductivity by the laser flash method, but the anisotropy of the thermal conductivity is not recognized in the as-sintered state without forging. However, forging causes anisotropy, and Cu phase and Cu 2 O
The thermal conductivity in the L direction, which is parallel to the orientation direction of the phase (forging direction), is twice or more the value in the C direction (forging method) orthogonal thereto.

【００３１】[0031]

【表１】 [Table 1]

【００３２】[0032]

【表２】 [Table 2]

【００３３】金属層が接合されているセラミック絶縁基
板１０９と放熱板１１０はあらかじめ直接接合処理を行
って一体化直接接合構造ヒートシンク部材として扱う方
が好ましい。図５は一体化直接接合工程を示したもので
ある。すなわち、表裏のＣｕ合金層が効ローなどにより
接合されたＡｌＮ等のセラミック絶縁基板１０９をＮｉ
等のメッキを施さない状態にて準備し、メッキを施さな
い状態のＣｕ−Ｃｕ2Ｏ複合材からなる放熱板１１０に
接合する。接合には例えば不活性雰囲気中の熱処理法を
用いる。熱処理によりＣｕ−Ｃｕ2Ｏ複合材表面とＣｕ
金属層表面が接合部位１０８にて金属結合を形成する。
このような直接接合処理後Ｎｉメッキなどを施し、一体
化直接接合構造ヒートシンクが形成される。このような
工程の代わりに条件を適宜設定することにより、Ｃｕ−
Ｃｕ2Ｏ複合材の焼結あるいは鍛造時点にセラミック絶
縁基板をセットして焼結あるいは鍛造と接合を同時に行
えば一体化ヒートシンクの形成はさらに容易である。一
体化直接接合構造ヒートシンクは放熱板１１０をハンド
リングできるため取り扱いが容易でセラミックへの衝撃
によるセラミック割れが起こりにくい。従って、セラミ
ック厚さを通常用いられる０.６３５mm よりも薄くして
熱抵抗をさらに低減することができる。この際、放熱板
１１０としてＣｕ−Ｃｕ2Ｏ 複合材を用いているためセ
ラミック絶縁基板１０９との熱膨張係数差が小さいこと
により、また、ヴィッカース硬さが３００以下であるた
め熱膨張係数差が無視できない値である場合においても
Ｃｕ−Ｃｕ2Ｏ複合材が熱応力により変形することによ
り、セラミック側への応力が緩和されセラミック割れや
クラック等の劣化が避けられる。It is preferable that the ceramic insulating substrate 109 and the heat radiating plate 110 to which the metal layers are bonded are directly bonded in advance and treated as an integrated direct bonding structure heat sink member. FIG. 5 shows the integrated direct joining process. That is, the ceramic insulating substrate 109 made of AlN or the like, in which the Cu alloy layers on the front and back sides are bonded together by Ni
Etc. are prepared in a state where no plating is applied, and are joined to the heat dissipation plate 110 made of a Cu—Cu 2 O composite material in a state where no plating is applied. For joining, for example, a heat treatment method in an inert atmosphere is used. Cu-Cu 2 O composite surface and Cu by heat treatment
The metal layer surface forms a metallurgical bond at the bond site 108.
After such a direct bonding process, Ni plating or the like is performed to form an integrated direct bonding structure heat sink. By appropriately setting the conditions instead of such steps, Cu-
If the ceramic insulating substrate is set at the time of sintering or forging of the Cu 2 O composite material, and the sintering or forging and the bonding are simultaneously performed, the formation of the integrated heat sink is further facilitated. Since the heat sink of the integrated direct-bonding structure can handle the heat sink 110, it is easy to handle and ceramic cracking due to impact on the ceramic is unlikely to occur. Therefore, the ceramic thickness can be made thinner than the normally used 0.635 mm to further reduce the thermal resistance. At this time, since the Cu—Cu 2 O composite material is used as the heat dissipation plate 110, the difference in the coefficient of thermal expansion from the ceramic insulating substrate 109 is small, and since the Vickers hardness is 300 or less, the difference in the coefficient of thermal expansion is large. Even when the value is not negligible, the Cu—Cu 2 O composite material is deformed by thermal stress, so that the stress to the ceramic side is relaxed and deterioration of ceramic cracks or cracks can be avoided.

【００３４】図２（ａ）は上記の直接接合処理プロセス
を鑑みて示している実施例であり、図１との差異はセラ
ミック絶縁基板が放熱板１５０に埋め込まれた形状とな
っていることにある。このような構造はＣｕ−Ｃｕ2Ｏ
複合材の焼結あるいは鍛造時点にセラミック絶縁基板を
セットして焼結あるいは鍛造と接合を同時に行うプロセ
スにより特に容易に実現しやすいものである。この場
合、セラミックが露出した縁面部分の絶縁性が確保する
ために、放熱板材料がセラミック絶縁基板１０９のセラ
ミックが露出した表面部分にまで回り込まないことが必
要である。このような構造とすることにより半導体チッ
プ１０１直下の放熱板１５０の厚さを薄くすることが可
能なため熱抵抗が小さくなり、放熱性がさらに向上す
る。FIG. 2 (a) shows an embodiment shown in view of the above-mentioned direct bonding process. The difference from FIG. 1 is that the ceramic insulating substrate is embedded in the heat sink 150. is there. Such structures Cu-Cu 2 O
It is particularly easy to realize by a process of setting a ceramic insulating substrate at the time of sintering or forging a composite material, and simultaneously performing sintering or forging and joining. In this case, in order to ensure the insulating property of the edge portion where the ceramic is exposed, it is necessary that the heat dissipation plate material does not go around to the surface portion of the ceramic insulating substrate 109 where the ceramic is exposed. With such a structure, the thickness of the heat dissipation plate 150 directly below the semiconductor chip 101 can be reduced, so that the thermal resistance is reduced and the heat dissipation is further improved.

【００３５】さらに他の構造として図２（ｂ）に示すよ
うに放熱板１６０はセラミック絶縁基板１０９の下部に
は存在せずセラミック絶縁基板１０９の周辺にのみ一体
化接合されていてもよい。この場合、Ｃｕ−Ｃｕ2Ｏ複
合材放熱板１６０とセラミック絶縁基板１０９裏面の金
属層１０７との直接接合は周辺部１６１，１６２にてな
される。この構造の場合には放熱性はさらに向上する。As another structure, as shown in FIG. 2B, the heat dissipation plate 160 may not be present under the ceramic insulating substrate 109 and may be integrally joined only around the ceramic insulating substrate 109. In this case, the Cu—Cu 2 O composite heat sink 160 and the metal layer 107 on the back surface of the ceramic insulating substrate 109 are directly joined at the peripheral portions 161 and 162. With this structure, the heat dissipation is further improved.

【００３６】以上のように、金属層が接合されているセ
ラミック絶縁基板１０９とＣｕ−Ｃｕ2Ｏ 複合材放熱板
１１０が直接金属接合されているため、接合部分の接続
信頼性が高く、また、半田がなくセラミック厚さも薄く
できることから熱抵抗も低減でき、さらに、あらかじめ
直接接合処理を行って一体化直接接合構造ヒートシンク
を形成することによりその後の組立てが容易になるとい
う効果がある。As described above, since the ceramic insulating substrate 109 to which the metal layer is joined and the Cu—Cu 2 O composite heat sink 110 are directly metal-joined, the connection reliability of the joint portion is high and Since there is no solder and the thickness of the ceramic can be made thin, the thermal resistance can be reduced, and further, by directly performing a direct bonding process to form an integrated direct bonding structure heat sink, there is an effect that subsequent assembly is facilitated.

【００３７】また、セラミック絶縁基板に接合されてい
る金属層としてＣｕ以外の金属、例えば、Ａｌの場合で
も接合条件を適宜設定すればＣｕ−Ｃｕ2Ｏ複合材放熱
板との直接接合は可能である。Further, even when the metal layer bonded to the ceramic insulating substrate is a metal other than Cu, for example, Al, direct bonding with the Cu—Cu 2 O composite heat sink is possible by appropriately setting the bonding conditions. is there.

【００３８】以上では、Ｃｕ−Ｃｕ2Ｏ複合材放熱板と
セラミック絶縁基板の裏面金属層との直接接合構造を説
明しているが、裏面金属層は必ずしも必須のものではな
い。すなわち、セラミック絶縁基板のセラミック表面と
Ｃｕ−Ｃｕ2Ｏ複合材を直接接合する構造でも構わな
い。この場合の接合方法は、銀ローをロー材として用い
る方法やＭｎ等のメタライズをあらかじめセラミックに
施し接合する方法や直接接合する方法でもよい。いずれ
の方法でもＣｕ−Ｃｕ2Ｏ複合材を放熱板に用いること
による前出のような効果は同様に達成される。Although the direct bonding structure between the Cu—Cu 2 O composite heat sink and the back surface metal layer of the ceramic insulating substrate has been described above, the back surface metal layer is not always essential. That is, the structure may be such that the ceramic surface of the ceramic insulating substrate and the Cu—Cu 2 O composite material are directly bonded. In this case, the joining method may be a method of using silver brazing material as a brazing material, a method of preliminarily applying metallization such as Mn to ceramics, or a method of direct joining. In either method, the same effect as described above can be achieved by using the Cu—Cu 2 O composite material for the heat dissipation plate.

【００３９】尚、セラミック絶縁基板はＡｌＮの法にＡ
ｌ2Ｏ3，ＢｅＯなど他の材質でも本発明の構造が適用で
きるのは言うまでもない。尚、それぞれ熱膨張係数が異
なるため、放熱板との熱膨張係数差を例えば５×１０-6
／℃以下に設定するなどの配慮が必要である。 （実施例２）図３は本発明に係る半導体装置の他の実施
例の断面図である。半導体チップ１０１は例えばＩＧＢ
ＴやパワーＭＯＳであり、その他主な部分の構造は図１
と同様である。本実施例では複数のモジュールを実装す
る時の共通ヒートシンクは必要なく、パワー半導体モジ
ュールのセラミック絶縁基板−放熱板一体化直接接合構
造ヒートシンク２１０の放熱板内部に冷却用のフィンが
設けられている。冷媒には例えば水が用いられ、パワー
モジュールを底面から見た図である図４に示したよう
に、注入口３０１，排出口３０２を放熱板底面に設けて
冷却水が循環される。冷却フィンの寸法、すなわちフィ
ン部１２２の厚さ寸法と空隙部１２１の間隔寸法は循環
冷却水用ポンプの能力等によっても影響されるため一概
には決まらないが、一般的には微細寸法にすることによ
りフィンの熱伝達係数が増加し、放熱能力が向上する。
本発明では冷却フィンが形成される放熱板にCu-Cu2O 複
合材を用いているため加工が容易であり、微細なフィン
を容易に形成できる。すなわち従来のＣｕ放熱板では１
mm程度の肉厚及び間隔形成が限界だったのに対し、０.
３mm 程度の肉厚及び間隔形成も容易である。このた
め、熱伝達係数は約２倍とすることが可能であり、放熱
性能が容易に向上できる。The ceramic insulating substrate is AN
It goes without saying that the structure of the present invention can be applied to other materials such as l 2 O 3 and BeO. Since the coefficients of thermal expansion are different, the difference in coefficient of thermal expansion from the heat sink is, for example, 5 × 10 −6.
Consideration such as setting below / ° C is necessary. (Embodiment 2) FIG. 3 is a sectional view of another embodiment of the semiconductor device according to the present invention. The semiconductor chip 101 is, for example, an IGB
T and power MOS, the structure of the other main parts is shown in FIG.
Is the same as. In this embodiment, a common heat sink is not required for mounting a plurality of modules, and cooling fins are provided inside the heat radiating plate of the ceramic insulating substrate-heat radiating plate integrated direct joining heat sink 210 of the power semiconductor module. For example, water is used as the coolant, and as shown in FIG. 4 which is a bottom view of the power module, the inlet 301 and the outlet 302 are provided on the bottom surface of the heat dissipation plate to circulate the cooling water. The dimensions of the cooling fins, that is, the thickness dimension of the fin portion 122 and the gap dimension of the void portion 121 are not unconditionally determined because they are influenced by the capacity of the circulating cooling water pump, etc. As a result, the heat transfer coefficient of the fins increases, and the heat dissipation ability improves.
In the present invention, since the Cu—Cu 2 O composite material is used for the heat dissipation plate on which the cooling fins are formed, the processing is easy and the fine fins can be easily formed. That is, it is 1 in the conventional Cu heat sink.
Whereas the limit was the wall thickness of about mm and the gap formation,
It is easy to form a wall thickness of about 3 mm and space. Therefore, the heat transfer coefficient can be doubled, and the heat dissipation performance can be easily improved.

【００４０】尚、フィン高さ、すなわち放熱板の厚さ方
向の設定も熱伝達係数に影響を及ぼすため適宜設定され
ることが必要である。前述のようにＣｕ−Ｃｕ2Ｏ複合
材の配向を制御し、放熱板の板厚方向、すなわち、フィ
ン高さ方向の熱伝導率を高くする構造とすることが放熱
上好ましい。この場合、フィンのアスペクト比（フィン
高さ／フィン幅）の設定はフィン材料の熱伝導率の異方
率（フィン高さ方向（放熱板板厚方向）熱伝導率／フィ
ン幅方向（放熱板面方向）熱伝導率）に対応して設定す
る。通常均質なフィン材料の場合のアスペクト比は７前
後程度に設定されるが、例えば、放熱板への配向性の付
与により熱伝導率の異方率が１以上となった場合、アス
ペクト比は熱伝導率の異方率と正の相関をもって設定さ
れる。すなわち、熱伝導率の異方率が２の場合、アスペ
クト比の最適値は通常の最適値より増加し、１〜２倍の
値に設定される。Note that the fin height, that is, the setting in the thickness direction of the heat sink affects the heat transfer coefficient, so it must be set appropriately. As described above, it is preferable in terms of heat dissipation to control the orientation of the Cu—Cu 2 O composite material and increase the thermal conductivity in the thickness direction of the heat dissipation plate, that is, in the fin height direction. In this case, the fin aspect ratio (fin height / fin width) is set by the anisotropy of the heat conductivity of the fin material (fin height direction (heat sink plate thickness direction) heat conductivity / fin width direction (heat sink plate). Set in accordance with (plane direction) thermal conductivity). Normally, the aspect ratio is set to about 7 in the case of a homogeneous fin material. For example, when the anisotropic ratio of thermal conductivity becomes 1 or more due to the orientation of the heat sink, the aspect ratio is It is set with a positive correlation with the anisotropy of conductivity. That is, when the anisotropic coefficient of thermal conductivity is 2, the optimum value of the aspect ratio is increased from the normal optimum value and is set to a value 1 to 2 times.

【００４１】セラミック絶縁基板−放熱板一体化直接接
合構造ヒートシンク２１０の加工方法の一例を図６に示
す。板状の、例えば、４mm厚程度の放熱を準備し、放熱
板にフィンを切削加工する。その後、１mm厚程度の薄板
１７１を加工面に直接金属接合する。この際セラミック
絶縁基板１０９との接合熱処理と同時に行うと工程が簡
便である。最後に、フィン内部及び表面の金属部全体に
Ｎｉなどのメッキを行う。フィン内部もメッキを行うこ
とによって冷却水による腐食が効果的に防止できる。
尚、このような工程の代わりにセラミック絶縁基板１０
９と放熱板との接合熱処理後、放熱板にフィンを切削加
工し、その後に薄板１７１を接合する工程でもかまわな
い。FIG. 6 shows an example of a method for processing the heat sink 210 having a ceramic insulating substrate-radiation plate integrated direct bonding structure. Prepare a plate-shaped heat radiation with a thickness of, for example, about 4 mm, and cut fins on the heat radiation plate. After that, a thin plate 171 having a thickness of about 1 mm is directly metal-bonded to the processed surface. At this time, if the heat treatment for bonding with the ceramic insulating substrate 109 is performed at the same time, the process is simple. Finally, plating of Ni or the like is performed on the inside of the fin and the entire metal portion on the surface. Corrosion due to cooling water can be effectively prevented by plating the inside of the fins.
Incidentally, instead of such a process, the ceramic insulating substrate 10
After the heat treatment for joining 9 and the heat radiating plate, a fin may be cut on the heat radiating plate and then the thin plate 171 may be joined.

【００４２】図４では破線にて放熱板内部の構造が示し
てあり、上記の微細なフィンは直線状のパターン３０３
となっている。注入口３０１，排出口３０２付近には微
細なフィンパターンはなく、水が広がり、また、集まり
やすくなっている。図示はしていないが半導体チップ１
０１は熱伝達係数が大きい微細フィンパターン部303の
位置に配置されると放熱性が向上するため好ましい。
尚、パワー半導体モジュールは取り付け部３０４にて電
力変換器の実装板に取り付けられる。In FIG. 4, the internal structure of the heat sink is shown by the broken line, and the fine fins described above have a linear pattern 303.
Has become. There is no fine fin pattern in the vicinity of the inlet 301 and the outlet 302, and water spreads and is easy to collect. Semiconductor chip 1 (not shown)
01 is preferably arranged at the position of the fine fin pattern portion 303 having a large heat transfer coefficient, because the heat dissipation is improved.
The power semiconductor module is attached to the mounting plate of the power converter at the attachment portion 304.

【００４３】このようなパワー半導体モジュールの適用
にはなんら制限が加わるものではないが、本実施例の水
冷一体化モジュールは電気自動車やハイブリッド電気自
動車に好適である。すなわち、これらのシステムでは水
冷機構をすでに備えている場合が多いため、この水冷循
環系に本発明のモジュール冷却を組入れればよい。 （実施例３）図７は本発明に係る半導体装置の他の実施
例の断面図である。半導体チップ１０１は例えばＩＧＢ
ＴやパワーＭＯＳであり、その他主な部分の構造は図１
と同様である。本実施例では共通ヒートシンクは必要な
く、パワー半導体モジュールのセラミック絶縁基板−放
熱板一体化直接接合構造ヒートシンクの放熱板710背面
に空冷用のフィンが設けられている。空冷フィンはＣｕ
−Ｃｕ2Ｏ複合材放熱板で構成されている。空冷フィン
の幅７２２及び間隔７２１及びこれらの高さは空冷ファ
ンの能力や気流の方向にも影響されるため一概には決ま
らないが、前述実施例２と同様にＣｕ−Ｃｕ2Ｏ 複合材
を用いることによって微細なフィンパターンが形成可能
なため放熱性能を向上するのに好適である。この構造で
は、冷媒が必要でなく自然空冷や強制空冷と言った簡便
な方法で冷却できるため電力変換システムを安価にする
ことができる。The application of such a power semiconductor module is not limited, but the water-cooled integrated module of this embodiment is suitable for an electric vehicle or a hybrid electric vehicle. That is, since these systems often already have a water cooling mechanism, the module cooling of the present invention may be incorporated into this water cooling circulation system. (Embodiment 3) FIG. 7 is a sectional view of another embodiment of the semiconductor device according to the present invention. The semiconductor chip 101 is, for example, an IGB
T and power MOS, the structure of the other main parts is shown in FIG.
Is the same as. In this embodiment, a common heat sink is not necessary, and fins for air cooling are provided on the back surface of the heat sink 710 of the ceramic insulating substrate-heat sink integrated direct bonding structure heat sink of the power semiconductor module. Air-cooled fin is Cu
It is composed of -cu 2 O composite radiator plate. The width 722 of the air-cooling fins, the space 721, and the heights thereof are not unconditionally determined because they are influenced by the capacity of the air-cooling fan and the direction of the air flow, but the Cu—Cu 2 O composite material is used as in the second embodiment. By using it, a fine fin pattern can be formed, which is suitable for improving heat dissipation performance. With this structure, a cooling medium is not required and cooling can be performed by a simple method such as natural air cooling or forced air cooling, so that the power conversion system can be made inexpensive.

【００４４】上記の実施例１，２，３ではパワー半導体
モジュールで説明しているが、これに限定する必要がな
いことは言うまでもない。すなわち、金属層が表面に接
合された部材と放熱板を有するものであれば本発明の直
接接合構造を採用でき、高い放熱性と信頼性を確保でき
る。例えば、半導体チップが半導体論理素子とする場
合、本発明構造を適用することにより論理素子の動作周
波数を向上させてもチップの温度が限界以上に上昇する
ことがなくなり、論理処理速度を向上できる。この場合
の構造は基本的に図１の半導体チップ１０１を上記素子
に置き換えたものであるが、チップ表面接続構造や端子
やモールド構造など本発明の対象とする部位以外の構造
は適宜公知の構造が適用されてよい。また、半導体素子
はメモリーやシステムＬＳＩやパワー素子等の他の素子
であっても同様の効果が得られる。 （実施例４）図８は本発明の他の実施例の高周波半導体
素子の断面図を示したものである。ＳｉあるいはＧａＡ
ｓ等からなる高周波半導体チップ８０１はＣｕ−Ｃｕ2
Ｏ複合材からなるベース基板８１４上に直接接合されて
いる。高周波半導体チップ８０１表面の電極はワイヤ８
０３によって端子８０４に接続されている。端子８０４
はセラミックやガラスからなる絶縁材８０５でロウ材８
１０，８１２を用いて封止されている。さらに枠体８０
６，シール材８０７がロー材８１２で接合され、シール
材８０７と蓋体８０８と溶接接合されることにより高周
波半導体素子が完成する。高周波半導体チップ８０１の
裏面には金属層８１３が設けてあり、この金属層８１３
は例えばＣｕから構成されている。前記の実施例と同様
に金属層８１３とＣｕ−Ｃｕ2Ｏ 複合材からなるベース
基板８１４は金属接合されている。また、Ｃｕ−Ｃｕ2
Ｏ 複合材からなるベース基板８１４には水冷冷却フィ
ン８０２が設けられている。高周波半導体チップ８０１
は高周波，高出力で動作させるため発生する熱を効率よ
く放散する必要があり、また、温度上昇によるチップ８
０１への熱応力や温度変化による繰り返し熱歪みを低減
することが必要である。ベース基板８１４が熱膨張係数
が１５×１０-6／℃以下、熱伝導率が130Ｗ／ｍ・Ｋ以
上の材料、例えば、Ｃｕ−Ｃｕ2Ｏ 複合材から構成さ
れ、これが高周波半導体チップ８０１に直接接合されて
いるため放熱性がよく、また、高周波半導体チップ８０
１との熱膨張係数差が小さいため熱応力が小さい。従っ
て、高周波半導体素子を高周波，高出力で効率よく安定
に動作させることができ高信頼性を確保できる。また、
水冷冷却フィン８０２を設けることにより放熱性能はさ
らに向上している。図９は本実施例の高周波半導体素子
の内部構造を示す斜視図を示している。Ｃｕ−Ｃｕ2Ｏ
複合材で高周波半導体チップが囲まれているため電磁シ
ールドとして機能し、電磁ノイズが漏洩することもなく
安定に動作できる。Although the power semiconductor module has been described in the first, second and third embodiments, it goes without saying that it is not necessary to limit to this. That is, as long as the metal layer has a member joined to the surface and a heat sink, the direct joining structure of the present invention can be adopted, and high heat dissipation and reliability can be secured. For example, when the semiconductor chip is a semiconductor logic element, by applying the structure of the present invention, the temperature of the chip does not rise above the limit even if the operating frequency of the logic element is improved, and the logic processing speed can be improved. The structure in this case is basically the semiconductor chip 101 of FIG. 1 replaced with the above element, but the structure other than the target part of the present invention, such as the chip surface connection structure, the terminal, and the mold structure, is an appropriately known structure. May be applied. The same effect can be obtained even if the semiconductor element is another element such as a memory, a system LSI, or a power element. (Embodiment 4) FIG. 8 is a sectional view of a high frequency semiconductor device according to another embodiment of the present invention. Si or GaA
The high-frequency semiconductor chip 801 made of s etc. is Cu-Cu 2
It is directly bonded onto a base substrate 814 made of an O composite material. The electrode on the surface of the high-frequency semiconductor chip 801 is the wire 8
It is connected to the terminal 804 by 03. Terminal 804
Is an insulating material 805 made of ceramic or glass and a brazing material 8
It is sealed by using 10,812. Further frame 80
6. The sealing material 807 is joined by the brazing material 812, and the sealing material 807 and the lid body 808 are joined by welding to complete the high-frequency semiconductor element. A metal layer 813 is provided on the back surface of the high frequency semiconductor chip 801, and the metal layer 813 is provided.
Is made of, for example, Cu. Similar to the above-described embodiment, the metal layer 813 and the base substrate 814 made of the Cu—Cu 2 O composite material are metal-bonded. In addition, Cu-Cu 2
A water-cooled cooling fin 802 is provided on a base substrate 814 made of an O 2 composite material. High frequency semiconductor chip 801
Needs to efficiently dissipate the heat generated in order to operate at high frequency and high output.
It is necessary to reduce repetitive thermal strain due to thermal stress on No. 01 and temperature change. The base substrate 814 is made of a material having a thermal expansion coefficient of 15 × 10 −6 / ° C. or less and a thermal conductivity of 130 W / m · K or more, for example, a Cu—Cu 2 O composite material, which is directly attached to the high frequency semiconductor chip 801. Since they are joined together, the heat dissipation is good, and the high frequency semiconductor chip 80
The thermal stress is small because the difference in the coefficient of thermal expansion from No. 1 is small. Therefore, the high frequency semiconductor element can be efficiently and stably operated at high frequency and high output, and high reliability can be secured. Also,
By providing the water cooling fins 802, the heat dissipation performance is further improved. FIG. 9 is a perspective view showing the internal structure of the high frequency semiconductor device of this embodiment. Cu-Cu 2 O
Since the high-frequency semiconductor chip is surrounded by the composite material, it functions as an electromagnetic shield and can operate stably without leakage of electromagnetic noise.

【００４５】また、高周波半導体素子はＳｉやＧａＡｓ
としたがＧａＮ，ＳｉＣ，ダイアモンド等の他の高周波
半導体素子であっても同様の効果が得られる。また、本
発明の構造は接合信頼性が高いため、２００℃から５０
０℃といった高温で動作可能な半導体チップを搭載する
場合にも好適である。The high frequency semiconductor element is made of Si or GaAs.
However, similar effects can be obtained with other high-frequency semiconductor elements such as GaN, SiC, and diamond. In addition, since the structure of the present invention has high bonding reliability,
It is also suitable for mounting a semiconductor chip that can operate at a high temperature of 0 ° C.

【００４６】[0046]

【発明の効果】以上に述べたように本発明によれば、組
立て性に優れ、高信頼性と高熱伝導性を有するセラミッ
ク絶縁基板−放熱板直接接合構造ヒートシンク、これを
用いた半導体装置、及び、これを用いた電力変換装置あ
るいは高周波トランジスタ装置が得られる。As described above, according to the present invention, a ceramic insulating substrate-radiating plate direct joint structure heat sink having excellent assembling property, high reliability and high thermal conductivity, a semiconductor device using the same, and A power converter or a high frequency transistor device using the same can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明に係る半導体装置の断面図。FIG. 1 is a cross-sectional view of a semiconductor device according to the present invention.

【図２】本発明に係る半導体装置の断面図。FIG. 2 is a sectional view of a semiconductor device according to the present invention.

【図３】本発明に係る半導体装置の断面図。FIG. 3 is a sectional view of a semiconductor device according to the present invention.

【図４】本発明に係る半導体装置の底面斜視図。FIG. 4 is a bottom perspective view of a semiconductor device according to the present invention.

【図５】本発明に係るセラミック絶縁基板−放熱板直接
接合構造ヒートシンクの製造工程説明図。FIG. 5 is an explanatory view of the manufacturing process of the heat sink of the ceramic insulating substrate-radiating plate direct joining structure according to the present invention.

【図６】本発明に係るセラミック絶縁基板−放熱板直接
接合構造ヒートシンクの製造工程説明図。FIG. 6 is an explanatory view of the manufacturing process of the heat sink of the ceramic insulating substrate-radiating plate direct joining structure according to the present invention.

【図７】本発明に係る半導体装置の断面図。FIG. 7 is a sectional view of a semiconductor device according to the present invention.

【図８】本発明に係る半導体装置の断面図。FIG. 8 is a sectional view of a semiconductor device according to the present invention.

【図９】本発明に係る半導体装置の断面図。FIG. 9 is a cross-sectional view of a semiconductor device according to the present invention.

【図１０】熱膨張係数と熱伝導率との関係を示す線図。FIG. 10 is a diagram showing the relationship between the coefficient of thermal expansion and the thermal conductivity.

【符号の説明】[Explanation of symbols]

１０１，８０１…半導体素子、１０２…半田、１０３…
ワイヤ、１０４…ケース、１０５…ゲルまたはモールド
レジン、１０６，１０７，１１１…セラミック絶縁基板
上に接合された金属層、１０８…金属層と放熱板の接合
面、１０９…セラミック絶縁基板、１１０，１５０，１
６０，２１０，７１０，８１４…放熱板、１２２，７２
２…放熱フィン、３０１，３０２…冷媒注入排出口、８
０４…端子、８１３…半導体チップに接合された金属
層。101, 801 ... Semiconductor element, 102 ... Solder, 103 ...
Wires, 104 ... Case, 105 ... Gel or mold resin, 106, 107, 111 ... Metal layer bonded on ceramic insulating substrate, 108 ... Bonding surface of metal layer and heat sink, 109 ... Ceramic insulating substrate, 110, 150 , 1
60, 210, 710, 814 ... Heat sink, 122, 72
2 ... Radiating fins, 301, 302 ... Refrigerant inlet / outlet port, 8
04 ... Terminal, 813 ... Metal layer bonded to semiconductor chip.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 清光 茨城県日立市大みか町七丁目１番１号 株式会社 日立製作所 日立研究所内 (56)参考文献 特開 平８−83864（ＪＰ，Ａ) 特開 平９−97865（ＪＰ，Ａ) 特開 昭64−59986（ＪＰ，Ａ) 特開 昭58−101465（ＪＰ，Ａ) 特開 昭64−12404（ＪＰ，Ａ) 特開2001−73047（ＪＰ，Ａ) 国際公開00／34539（ＷＯ，Ａ１) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 - 23/15 H01L 23/36 - 23/373 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyomitsu Suzuki 1-1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (56) Reference JP-A-8-83864 (JP, A) Kaihei 9-97865 (JP, A) JP-A 64-59986 (JP, A) JP-A 58-101465 (JP, A) JP-A 64-12404 (JP, A) JP-A 2001-73047 (JP , A) International publication 00/34539 (WO, A1) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/12-23/15 H01L 23/36-23/373

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】半導体素子と、信号を入出力する配線と、
金属層が接合された絶縁基板と、放熱板とを有する半導
体装置において、前記放熱板と絶縁基板に接合されてい
る金属層は直接接合され、前記放熱板はＣｕとＣｕ 2 Ｏ
との複合材からなることを特徴とする半導体装置。1. A semiconductor element and wiring for inputting and outputting a signal,
In a semiconductor device having an insulating substrate to which a metal layer is joined and a heat sink, the metal layer joined to the heat sink and the insulating substrate is directly joined, and the heat sink is made of Cu and Cu 2 O.
Wherein a Rukoto such a composite material with. 【請求項２】半導体素子と、信号を入出力する配線と、
絶縁基板と、放熱板とを有する半導体装置において、前
記放熱板と絶縁基板は直接接合され、前記放熱板はＣｕ
とＣｕ 2 Ｏ との複合材からなることを特徴とする半導体
装置。2. A semiconductor element and wiring for inputting and outputting a signal,
In a semiconductor device having an insulating substrate and a heat dissipation plate, the heat dissipation plate and the insulation substrate are directly bonded, and the heat dissipation plate is made of Cu.
Wherein a Rukoto such a composite material and Cu 2 O. 【請求項３】金属層を有する半導体素子と、信号を入出
力する配線と、放熱板とを有する半導体装置において、
前記放熱板と半導体素子に接合されている金属層は直接
接合され、前記放熱板はＣｕとＣｕ 2 Ｏ との複合材から
なることを特徴とする半導体装置。3. A semiconductor device having a semiconductor element having a metal layer, wiring for inputting and outputting signals, and a heat sink,
The heat sink and the metal layer joined to the semiconductor element are directly joined, and the heat sink is made of a composite material of Cu and Cu 2 O.
Wherein a Rukoto such. 【請求項４】前記放熱板は熱膨張係数が１５×１０-6℃
以下、熱伝導率が１３０Ｗ／ｍＫ以上、ヴィッカース硬
度が３００以下であることを特徴とする請求項１〜３記
載の半導体装置。4. The heat dissipation plate has a coefficient of thermal expansion of 15 × 10 −6 ° C.
4. The semiconductor device according to claim 1, wherein the thermal conductivity is 130 W / mK or more and the Vickers hardness is 300 or less. 【請求項５】前記Ｃｕ2Ｏの結晶粒はＣｕの結晶粒の加
工方向に延伸していることを特徴とする請求項１〜３記
載の半導体装置。Wherein said Cu 2 O crystal grains semiconductor device of claim 1, wherein the extends in processing direction of the crystal grains of the Cu. 【請求項６】前記放熱板は内部に冷媒を通す空隙を有す
るフィンが設けられていることを特徴とする請求項１〜
５記載の半導体装置。6. The heat dissipating plate is provided with a fin having a void for passing a refrigerant therein.
5. The semiconductor device according to item 5 . 【請求項７】前記放熱板は裏面に空冷フィンが設けられ
ていることを特徴とする請求項１〜５記載の半導体装
置。Wherein said heat sink device according to claim 1-5, wherein the cooling fins are provided on the back surface.
JP2000027318A 2000-01-31 2000-01-31 Semiconductor device Expired - Lifetime JP3452011B2 (en)

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EP2398049A3 (en) * 2003-08-22 2012-12-19 The Kansai Electric Power Co., Inc. Semiconductor device and method of producing the same, and power conversion apparatus incorporating this semiconductor device
JP4682775B2 (en) * 2005-09-27 2011-05-11 セイコーエプソン株式会社 Microchannel structure, heat exchange system, and electronic device
JP4605009B2 (en) * 2005-12-28 2011-01-05 三菱マテリアル株式会社 Power module manufacturing method
JPWO2008081848A1 (en) * 2006-12-28 2010-04-30 隆也 久世 Cooling device, electronic heating element cooling external kit, and electronic heating element assembly with cooling device
JP2008270294A (en) * 2007-04-16 2008-11-06 Sumitomo Electric Ind Ltd Heat sink member and semiconductor device
JP2009071102A (en) * 2007-09-14 2009-04-02 Omron Corp Power module structure
JP5467407B2 (en) * 2007-10-22 2014-04-09 Ｄｏｗａメタルテック株式会社 Aluminum-ceramic bonded body
JP5695306B2 (en) * 2009-08-24 2015-04-01 リコー電子デバイス株式会社 Electronic circuit component and manufacturing method thereof
JP2013211287A (en) * 2012-03-30 2013-10-10 Mitsubishi Materials Corp Substrate for power module with heat sink, manufacturing method of the same, and substrate for power module
JPWO2015174198A1 (en) * 2014-05-13 2017-04-20 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP6302803B2 (en) 2014-09-09 2018-03-28 日立オートモティブシステムズ株式会社 Power semiconductor module, method for manufacturing the same, and power conversion device
US10290602B2 (en) 2015-07-08 2019-05-14 Sumitomo Electric Industries, Ltd. Semiconductor device and method of making semiconductor device
DE102018217456B4 (en) * 2018-10-11 2020-07-09 Conti Temic Microelectronic Gmbh Electronic control device and method for manufacturing an electronic control device
JP7435416B2 (en) 2020-11-19 2024-02-21 株式会社明電舎 Series connected devices

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