JP3450983B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor devices, and more particularly to a dynamic random access memory (hereinafter referred to as DRAM) improved so as to reduce a junction leak .

[0002]

2. Description of the Related Art FIG. 18 is a sectional view of a conventional DRAM. The DRAM is formed on the semiconductor substrate 1. The main surface of the semiconductor substrate 1 is divided into an element formation region and an element isolation region. Elements such as NMOS and PMOS transistors are formed in the element formation region. The element isolation region is formed so as to surround the element formation region, and has an isolation insulating film 5 for electrically isolating adjacent element formation regions.

The element formation region is roughly divided into a memory cell portion and a peripheral circuit portion. The memory cell section includes a capacitor 20 for electrically storing information and an NMOS transistor connected to the capacitor 20. In the peripheral circuit portion, NMOS and PMOS transistors forming a circuit for inputting / outputting information stored in the capacitor are formed.

A conventional method of manufacturing such a DRAM is
The figure will be described. Referring to FIG. 19, oxide film 2 and nitride film 3 are formed on P-type silicon substrate 1. These are patterned by photolithography. afterwards,
0.15 μm to 0.40 μm from the main surface of the semiconductor substrate 1
Trench 4 is formed in the main surface of semiconductor substrate 1 by etching the silicon to a certain depth.

Referring to FIG. 20, a trench 4 is filled with an insulating material such as an oxide film or a nitride film or a composite film with polysilicon or the like, which is then CMP (Chemical Mechanical).
The trench isolation insulating film 5 is flattened by polishing, etc.
To form.

With reference to FIG. 21, the memory cell portion and the NMOS portion of the peripheral circuit portion are masked with a resist 40, phosphorus is ion-implanted into the p-channel transistor region of the peripheral circuit portion, and 0. Punch-through stopper layer 6 (N type) having an impurity concentration peak within 2 μm, and channel cut layer 7 (N-type) having an impurity concentration peak near the bottom of the trench at a position deeper than punch-through stopper layer 6.
Type), a position 0.7 deeper than the channel cut layer 7
Well 8 having a peak of the impurity concentration in μm to 1.4 μm
(N type) are formed respectively.

Referring to FIG. 22, the PMOS region is masked with a resist 41, and boron is ion-implanted into the n-channel transistor region of the memory cell portion and the peripheral circuit portion.
The punch-through stopper layer 9 (P type) having a peak impurity concentration within 0.2 μm from the main surface, and the channel-cut layer 10 (having a peak impurity concentration near the bottom of the trench at a position deeper than the punch-through stopper layer 9 ( P type), a position 0.7 μm deeper than the channel cut layer 10
Well 11 with peak impurity concentration at ~ 1.4 μm
(P type) are formed respectively. The resist 41 is removed.

Referring to FIG. 23, a gate oxide film is formed (not shown) in the main surface of a semiconductor substrate, a polycrystalline silicon film, a tungsten silicide film, and a silicon oxide film are formed, and these are photographed. The gate electrode 42 is formed by patterning by plate-making technology and etching.
Next, only the p-channel transistor region is covered with a resist (not shown), and the N-type LDD-type source / drain region 1 is formed in the memory cell part and the NMOS part by ion implantation.
2 to form a low density portion. Next, only the n-channel transistor region is covered with a resist (not shown), and the low concentration portion of the P-type LDD type source / drain region 13 is formed by the ion implantation method. Next, a sidewall spacer 4 made of an oxide film or a nitride film is formed on the sidewall of the gate electrode.
5 is formed.

Next, only the p-channel transistor region is covered with a resist (not shown), and arsenic is formed near the main surface so as to be shallower than the punch-through stopper layer 9 by the ion implantation method, and the N-type source / drain region 12 is formed. Form a high-concentration portion. Next, only the n-channel transistor region is covered with a resist (not shown), and boron is implanted by an ion implantation method to form a high concentration portion of the P type source / drain region 13.

Referring to FIG. 24, interlayer insulating film 18 is formed to cover gate electrode 42. Thereafter, the polysilicon plugs 16 and 19, the bit line 1 7, to form a storage node 20. Next, a capacitor insulating film is formed so as to cover the storage node 20 (not shown),
A cell plate is formed so as to cover the storage node 20 through the capacitor dielectric film (not shown). Next, after depositing an interlayer insulating film (not shown), this is etched so that the peripheral transistor section and the cell plate section of the memory cell section are opened to form a metal contact (not shown). Next, after depositing the Al-Cu film,
The DRAM is completed by etching this into a predetermined pattern to form metal wiring.

FIG. 25 is a profile of the impurity concentration in the cross section taken along the line XY in FIG. Figure 2
5 , it can be seen that the concentration profiles of the N-type source / drain region 12, punch-through stopper layer 9, channel cut layer 10, and well 11 overlap.

[0012]

The miniaturization of semiconductor memories is advancing year by year. Along with this, the gate length of the MOS transistor exceeds 0.1 μm, and development is underway. A problem with such a fine transistor is a punch-through problem in which the depletion layer on the drain side extends and connects to the source. In order to suppress this, referring to FIG. 18, the source / drain diffusion layer 1
A method of forming shallowly 2 and forming an impurity layer 9 called a punch-through stopper near the main surface so that the depletion layer does not spread in the substrate is often used.

However, in this structure, FIG. 18 and FIG.
5, the N-type diffusion layer 12 of the source / drain portion and the P-type diffusion layer 9 of the punch through stopper are in contact with each other at a high concentration. As the miniaturization progresses, it is necessary to suppress the extension of the depletion layer, so that the diffusion layer 12 is formed shallower,
The joining surface becomes higher in density. When such a PN junction is formed, the expansion of the depletion layer is suppressed, but on the other hand, the bending of the band on the junction surface becomes sharp and the electric field becomes strong. This leads to an increase in leak current in the substrate direction when a voltage is applied to the source / drain in order to operate the device. In a DRAM in which electric charges are stored in a capacitor to store information, it is important to reduce the leakage of the stored electric charge. Therefore, it is not preferable to use a transistor having such a problem in a memory cell.

An object of the present invention is to solve the above problems, and it is an object of the present invention to provide an improved semiconductor device capable of reducing charge leakage.

[0015]

[0016]

A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate. A trench isolation oxide film for isolating one element region from another element region is provided in the main surface of the semiconductor substrate. A gate electrode is provided on the element region of 1. A pair of source / drain regions of the first conductivity type having an LDD structure including a high-concentration portion and a low-concentration portion are provided on both sides of the gate electrode in the main surface of the first element region. There is. Toward the substrate from the main surface of the semiconductor substrate, Ri second conductivity type punch-through stopper layer spread further, the punch
It is in contact with the through stopper layer and below it,
Lower layer of the second conductivity type with a thin concentration near the through-stopper layer
There are departments . One of the sources on the semiconductor substrate
A capacitor connected to the drain region is provided. A bit line connected to the other source / drain region is provided on the semiconductor substrate. In the semiconductor substrate, the second conductivity type channel cut layer is provided only directly below the trench isolation oxide film.
The apparatus further in the direction it suited <br/> into the substrate from the surface of the semiconductor substrate, deeper than the upper <br/> Symbol punch-through stopper layer from the bottom of the source / drain regions, further the lower layer
Of the source / dray , which spreads to the low density area of
Concentration than the high concentration portion of the emission region is formed thinly, the first
A conductivity type impurity diffusion layer is provided.

[0017]

According to the semiconductor device of the second aspect , the depth of the trench for forming the trench isolation oxide film is 0.15 μm to 0.4 from the main surface of the semiconductor substrate.
It is set to 0 μm.

[0019]

According to the semiconductor device of the third aspect , at the PN junction between the second-conductivity-type channel cut layer and the first-conductivity-type impurity diffusion layer, the respective impurity concentrations are 2 × 10 ¹⁷ / cm 3. It is described below.

According to the semiconductor device of the fourth aspect , the impurity diffusion layer is provided only under the one source / drain region to which the capacitor is connected.

[0022]

[0023]

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a sectional view of a DRAM according to the first embodiment.
FIG. 1A is a cross-sectional view of the memory cell portion, and FIG.
FIG. 3 is a cross-sectional view of a semiconductor device including a memory cell section and peripheral circuits. In these figures, the same or corresponding parts as those of the conventional apparatus shown in FIG. 18 are designated by the same reference numerals, and the description thereof will not be repeated.

Referring to FIGS. 1A and 1B, a trench isolation oxide film 5 for isolating one element region from another element region is provided in the main surface of P type silicon substrate 1. There is.

FIG. 2 is a plan view of the silicon substrate having the trench isolation oxide film 5. Referring to FIG. 2, the trench isolation oxide film 5 has one element region 50a and another element region 5a.
It is provided to separate from 0b.

Returning to FIGS. 1A and 1B, the gate electrode 42 is provided on one element region.

FIG. 3 shows X'- in FIGS. 1 (a) and 1 (b).
The impurity concentration profile in the cross section along the Y ′ line is shown.

Referring to FIGS. 1A and 1B and FIG. 3, in the LDD structure including high-concentration and low-concentration portions on both sides of the gate electrode 42 in the main surface of one element region. A pair of N
A type source / drain region 12 is provided. From the main surface of the silicon substrate 1 toward the substrate, and spread P-type punch-through stopper layer 9, further Panchisuru
-Punch-through in contact with the stopper layer 9 and the lower layer
-Light concentration near stopper layer 9, peak at deeper position
There is a P-type lower layer portion having a concentration. This lower layer is
Physically, it is the well 11 . A capacitor 20 connected to one of the source / drain regions 12 is provided on the silicon substrate. The capacitor 20 and one source / drain region 12 are connected by a polysilicon plug 19. On the silicon substrate 1, the other source /
A bit line 17 connected to the drain region is provided. The bit line 17 and the other source / drain region 12 are connected by a polysilicon plug 16. In the direction it unsuitable from the surface of the silicon substrate 1 in the substrate, the source / drain
From the bottom of the in-region 12 to a depth deeper than the punch-through stopper layer 9 , and as a lower layer, the well 11 is thinned to the above concentration.
The N-type low-concentration impurity diffusion layer 15 extends to the open portion. Low concentration impurity diffusion layer 15 of N-type has a density lower than the high concentration portion of the source over the scan / drain region 12. The P-type channel cut layer 7 a is provided only in the silicon substrate 1 and just below the trench isolation oxide film 5.
Here, the low-concentration impurity diffusion layer 15 is a high-concentration source /
Inside the well 11 without forming a PN junction with the drain region 12
To form a PN junction, and such a PN junction contains a high concentration.
It becomes a junction between the areas that do not come.

According to the present embodiment, since the P type channel cut layer 7a is provided only directly under the trench isolation oxide film 5, the source / drain N type diffusion layer 12 is
Since it is possible to further reduce the number of high-concentration junctions with the P-type diffusion layer that is the channel cut layer 7a, it is possible to reduce the leak current.

FIG. 4 is an enlarged view of a portion where the low concentration N type diffusion layer 15, the P type channel cut layer 7a and the trench isolation insulating film 5 are present. FIG. 5 shows an impurity concentration profile in a cross section taken along the line VV in FIG.
P-type channel cut layer 7a and low-concentration N-type impurity diffusion layer 1
At the PN junction with 5, the impurity concentration of each is 2
It is set to be less than or equal to × 10 ¹⁷ / cm ³ . Since the concentration of the part where the PN junction is formed is minimized,
Even if a voltage is applied to the drain, the leak current in the substrate direction is reduced.

In order to reduce the junction leakage current, unlike the above method, referring to FIG. 18, the trench isolation 5 is deeply formed and the channel cut layer 10 is deeply formed, so that the N-type is formed. A method of lowering the concentration of the PN junction between the source / drain region 12 and the channel cut layer 10 may be considered. However, in this method, the trench 4
Since the trench is formed deeply, it becomes difficult to fill the trench, which is not preferable.

Further, referring to FIG. 18, there is also a method of lowering the impurity concentration of channel cut layer 10, but this method is not preferable because it lowers the element isolation characteristics.

On the other hand, the method according to the first embodiment can reduce the leak current without causing such a problem.

Further, in the first embodiment, N of the peripheral circuit section is used.
Also on the MOS transistor side, a channel cut layer 7a is provided immediately below the trench isolation insulating film 5. By forming in this way, the N of the peripheral circuit section is
Also in the MOS transistor, the source / drain N-type diffusion layer can be reduced in the number of portions of the channel cut layer 7a that are joined to the P-type diffusion layer at a high concentration, and the leakage current can be reduced.

Next, a method of manufacturing the DRAM according to the first embodiment shown in FIGS. 1A and 1B will be described.

Referring to FIG. 6, oxide film 2 and nitride film 3 are sequentially formed on P-type silicon substrate 1, for example. By the photoengraving technique, the oxide film 2 and the nitride film 3 in the portion where the trench isolation insulating film is formed are removed by etching,
After that, from the main surface of the silicon substrate 1 to 0.15 μm
The trench 4 is formed by etching the silicon to a depth of about 0.40 μm.

Then, referring to FIG. 7, boron ions are vertically implanted only into the bottom portion of trench 4 using the etching mask as a mask to form P type channel cut layer 7a. After that, the oxide film 2 and the nitride film 3 are removed.

With reference to FIG. 8, a trench 4 is filled with an insulating material such as an oxide film or a nitride film or a composite film with polysilicon or the like, and is flattened by CMP or the like to form the trench isolation insulating film 5. Form.

Referring to FIG. 9, a portion of the peripheral circuit portion other than the n-channel transistor region is masked with a resist 40, phosphorus is ion-implanted into the p-channel transistor region, and the impurity concentration is adjusted within 0.2 μm from the main surface. N-type punch-through stopper layer 6 having a peak, N-type channel cut layer 7 having a peak of impurity concentration near the bottom of the trench at a deeper position than that, further deeper position 0.7 μm
N-type wells 8 each having an impurity concentration peak at ˜1.4 μm are formed.

Referring to FIG. 10, the p-channel transistor region of the peripheral circuit portion is masked with a resist 40, boron is ion-implanted into the n-channel transistor region of the memory cell portion and the peripheral circuit portion, and 0.2 μm from the main surface. A P-type punch through stopper layer 9 having an impurity concentration peak is formed therein, and a P-type well 11 having an impurity concentration peak is formed at a deeper position of 0.7 μm to 1.4 μm. The resist 40 is removed.

Referring to FIG. 11, after a gate oxide film is formed by thermal oxidation (not shown), a polycrystalline silicon film, a tungsten silicide film, and a silicon oxide film are formed (not shown), a photoengraving process is performed. Then, these are patterned by etching to form the gate electrode 42.

Next, only the p-channel transistor region is covered with a resist (not shown), and an N-type is formed by an ion implantation method.
A low concentration portion of the mold source / drain region 12 is formed.
Next, only the n-channel transistor region is covered with a resist, and the P-type source / drain region 1 is formed by ion implantation.
3 to form a low-density portion.

After that, an oxide film or a nitride film is formed on the surface of the silicon substrate 1, and these are etched back to form sidewall spacers 45 on the side walls of the gate electrode 42.

Next, the memory cell portion is covered with a resist, phosphorus is ion-implanted, and the low concentration N-type diffusion layer 15 having a concentration lower than that of the high concentration portion of the source / drain region is formed so as to wrap the punch through stopper layer 9. To form.

Referring to FIG. 12, an interlayer insulating film 18 is formed on silicon substrate 1, and storage is performed in this interlayer insulating film 18 so that a part of the surface of the drain portion of the memory cell portion is exposed. A node contact hole is formed. A polysilicon film is deposited on the silicon substrate 1 so as to fill the storage node contact hole, and this is patterned to form a polysilicon plug 19 and a storage node 20. After that, a capacitor dielectric film is formed and a cell plate is formed (not shown).

After that, an interlayer insulating film is further deposited, and this is etched so as to expose a part of the cell plate portion of the peripheral transistor portion and the memory cell portion to form a metal contact (not shown). Next, Al-Cu
A metal wiring is formed by depositing a film and patterning it. This completes the DRAM.

Although various channel engineering techniques are known for forming an NMOS transistor, for those having a source / drain region, a punch-through stopper layer, and an N-type diffusion layer as a profile in the depth direction, Either one can be applied.

In this embodiment, referring to FIG. 11, the gate electrode 42 is used as a mask to form the low-concentration N-type diffusion layer 15 surrounding the punch-through stopper layer 9.
Although the method of implanting an impurity has been illustrated, the present invention is not limited to this. Referring to FIG. 12, after forming a storage node contact hole, ion implantation is performed from this contact hole to obtain a low concentration. The N-type diffusion layer 15 may be formed. In this case, only under the source / drain region on the side where the capacitor is connected,
The low concentration N-type impurity diffusion layer 15 is formed.

The present invention can also be applied to the case where an epi substrate having a triple well structure and a high concentration P type CZ substrate and a low concentration P type epitaxial layer is used.

Embodiment 2 Embodiment 2 is a method of manufacturing a DRAM according to the present invention.
It is related to another embodiment.

Referring to FIG. 13, oxide film 2 and nitride film 3 are formed on P type silicon substrate 1. The oxide film 2 and the nitride film 3 in the portion where the trench isolation insulating film is to be formed are removed by photolithography, and the trench 4 is formed by etching the silicon.

Referring to FIG. 14, a sacrificial oxide film 21 (which may be an oxide film or a nitride film formed by CVD or the like) for stress relaxation and cleaning of trench 4 is formed so as to cover the inner wall surface of trench 4. To form. Boron ions are vertically implanted near the silicon surface at the bottom of the trench 4 through the sacrificial oxide film 21 to form a channel cut implantation layer 7b. Referring to FIG. 15, sacrificial oxide film 21 is removed, oxide film 2 and nitride film 3 are removed, and the semiconductor device shown in FIG. 16 is obtained through the steps of FIGS. After that, FIG.
After the process shown in (1), the DRAM is completed. According to the second embodiment, referring to FIG. 16, the width of channel cut injection layer 7b can be made smaller than the width of trench 4, so that the interference action between channel cut injection layer 7b and low concentration N-type impurity diffusion layer 15 is caused. Can be made smaller.

Third Embodiment FIG. 17 is a diagram showing a method according to the third embodiment.
First, in the main surface of silicon substrate 1, trench 4 having a sidewall whose cross-sectional shape becomes smaller toward the bottom is formed. After forming the insulating film 21 having an appropriate thickness on the inner surface of the trench 4, the trench 4 is formed by ion implantation.
The channel cut injection layer 7b is formed only on the bottom of the. After that, insulating film 21 is removed and the same process as in the second embodiment is performed to complete the DRAM. The use of the trench having the inclined sidewall has an effect that the trench isolation insulating film is easily embedded in the trench 4.

In this case, when the inclination becomes nearly vertical, the insulating film 21 becomes substantially thicker for the implanted ions, so that the implantation into the inclined portion can be prevented.

[0057]

As described above, according to the first aspect of the present invention, since the second conductivity type channel cut layer is formed only directly below the trench isolation oxide film, the low-encapsulation layer that surrounds the punch-through stopper layer is formed. Even if the concentrated first conductivity type diffusion layer is formed, the low concentration N type diffusion layer does not come into contact with the channel cut layer, so that the PN junction is not formed in high concentration. As a result, the leak current can be reduced. Consequently, the charge stored in the capacitor can be held for a long time, and the refresh characteristic can be improved. Further, since the junction capacitance is reduced, the leak current is reduced and the element can be operated at high speed. Also,
The punch through stopper is located below the punch through stopper layer.
-In the vicinity of the stopper layer, the lower layer of the second conductivity type with a thin concentration is
Of the saw-through stopper layer and the saw
The first conductor, which has a lower concentration than the high-concentration portion of the gate / drain region
Conductivity type impurity diffusion layer is, the direction <br/> or earthenware pots direction from the surface of the semiconductor substrate to substrate, deeper than bread <br/> Chi-through stopper layer from the bottom of the source / drain regions further lower portion of the thin
Because there I spread to a concentration part, never PN junction punch-through stopper layer and the source / drain layer is formed at a high concentration. Furthermore, since the leak current can be reduced, the electric charge stored in the capacitor can be retained for a longer period of time, and the refresh characteristic can be improved.

[0058]

According to the semiconductor device of the second aspect , the depth of the trench is 0.15 μm from the main surface of the semiconductor substrate.
Since it is formed as shallow as 0.40 μm, the process time can be shortened. Further, there is an effect that it becomes easy to embed the insulating film in the trench.

[0060]

According to the semiconductor device of the third aspect , the PN junction between the channel cut layer and the low-concentration impurity diffusion layer has an impurity concentration of 2 × 10 ¹⁷ / cm 3 or less. The current can be reduced.

According to the semiconductor device of the fourth aspect , since the low-concentration impurity diffusion layer is provided only under one of the source / drain regions to which the capacitor is connected, a junction leakage current is generated in this portion. The effect that it can reduce is produced.

[0063]

[0064]

[Brief description of drawings]

FIG. 1 is a sectional view (a) of a memory cell portion according to a first embodiment and a sectional view (b) of a semiconductor device including a memory cell portion and a peripheral circuit portion.

FIG. 2 is a diagram showing a planar shape of a trench isolation insulating film.

FIG. 3 is an impurity concentration profile diagram in a cross section taken along line X′-Y ′ in FIG.

FIG. 4 is a partially enlarged view of a portion where a trench isolation insulating film, a channel cut layer, and a low-concentration impurity diffusion layer exist in FIG. 1.

5 is an impurity concentration profile diagram in a cross section taken along line VV in FIG.

FIG. 6 is a cross-sectional view of the semiconductor device in a first step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 7 is a cross-sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 8 is a sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 9 is a sectional view of the semiconductor device in a fourth step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 10 is a cross-sectional view of the semiconductor device in a fifth step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 11 is a cross-sectional view of the semiconductor device in a sixth step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 12 is a cross-sectional view of the semiconductor device in a seventh step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 13 is a cross-sectional view of the semiconductor device in a first step in the order of the method for manufacturing the semiconductor device according to the second embodiment.

FIG. 14 is a cross-sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device according to the second embodiment.

FIG. 15 is a cross-sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device according to the second embodiment.

FIG. 16 is a cross-sectional view of the semiconductor device in a fourth step of the order of the method for manufacturing the semiconductor device according to the second embodiment.

FIG. 17 is a sectional view of the semiconductor device showing the main steps of the method of manufacturing the semiconductor device according to the third embodiment.

FIG. 18 is a cross-sectional view of a conventional DRAM.

FIG. 19 is a cross-sectional view of the semiconductor device in a first step of the order of the conventional DRAM manufacturing method.

FIG. 20 is a cross-sectional view of the semiconductor device in a second step of the order of the conventional DRAM manufacturing method.

FIG. 21 is a cross-sectional view of the semiconductor device in a third step of the order of the conventional DRAM manufacturing method.

FIG. 22 is a cross-sectional view of the semiconductor device in a fourth step of the order of the conventional DRAM manufacturing method.

FIG. 23 is a cross-sectional view of the semiconductor device in a fifth step of the order of the conventional DRAM manufacturing method.

FIG. 24 is a cross-sectional view of the semiconductor device in a sixth step of the order of the conventional DRAM manufacturing method.

25 is a diagram showing a concentration profile in a cross section taken along line XY in FIG.

[Explanation of symbols]

1 P-type silicon substrate, 5 trench isolation insulating film, 7a
Channel cut layer, 9 Punch through stopper layer, 1
2 N type source / drain regions, 15 low concentration N type diffusion layers, 17 bit lines, 20 capacitors, 42 gate electrodes.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8242 H01L 21/8234 H01L 27/088 H01L 27/108

Claims (4)

(57) [Claims] 1. A semiconductor substrate, a trench isolation oxide film provided in a main surface of the semiconductor substrate for isolating one element region from another element region, and provided on the one element region. And a pair of first-conductivity-type sources of LDD structure provided on both sides of the gate electrode in the main surface of the first element region and having a high-concentration portion and a low-concentration portion. / Drain region, a second conductivity type punch-through stopper layer extending from the main surface of the semiconductor substrate toward the inside of the substrate, and a layer below and in contact with the punch-through stopper layer.
Therefore, in the vicinity of the punch-through stopper layer,
Two-conductivity-type lower layer portion, a capacitor provided on the semiconductor substrate and connected to one source / drain region, and a bit provided on the semiconductor substrate and connected to the other source / drain region and line, even during the semiconductor substrate, said trench isolation oxide second conductivity type channel cut layer provided only immediately below the film, in a direction that would unsuitable from the surface of the semiconductor substrate in a substrate, wherein
From the bottom of the source / drain region to a depth deeper than the punch-through stopper layer , and further to a low concentration portion of the lower layer portion , and the high concentration of the source / drain region.
Concentration than the portion is formed thinly, an impurity diffusion layer of a first conductivity type, a semiconductor device comprising. 2. The depth of the trench for forming the trench isolation oxide film is 0 .. from the main surface of the semiconductor substrate.
The semiconductor device according to claim 1, having a thickness of 15 μm to 0.40 μm. 3. A PN junction between the second conductivity type channel cut layer and the first conductivity type impurity diffusion layer,
The semiconductor device according to claim 1 , wherein each impurity concentration is set to 2 × 10 ¹⁷ / cm ³ or less. 4. The semiconductor device according to claim 1, wherein the first conductivity type impurity diffusion layer is provided only under the one source / drain region to which the capacitor is connected.