JP3450214B2 - Data processing device and data processing method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and a data processing method for transferring data between a master circuit and a slave circuit, and more particularly to a master circuit and a slave by an address data bus sharing the address bus. The present invention relates to a data processing device and a data processing method for transferring data to and from a circuit.

[0002]

2. Description of the Related Art Conventionally, a data transfer system using an address data bus sharing an address bus and a data bus has a configuration shown in FIG. 12 and operates as shown in FIG. That is, the master circuit 1 and the slave circuits X and Y are configured such that the address data bus 100, the address strobe 102, the data strobe 105, and the signal lines for the read / write signal 107 are connected to each other. Is the address data bus 100
The address <A1> corresponding to each slave circuit is output to. Also, the address output on the address data bus <
The address strobe 102 is output to cause each slave circuit to determine A1>, and the master circuit 1 outputs the read / write signal 107 to determine whether the output address is a read request or a write request.
Each slave circuit determines that its own slave circuit has been accessed by the address data bus 100 and the address strobe 102, prepares output data if the own slave circuit is accessed by a read request, and the master circuit 1 outputs the data strobe. After confirming that 105 is output, data <D1 is transferred onto the address data bus 100.
> Is output. The master circuit 1 operates based on the clock 200 output from the oscillator 10, and the slave circuit X and the slave circuit Y further include the oscillators 11 and 1 respectively.
It operates based on the clocks 201 and 202 which are the output signals from 2.

[0003]

However, the prior art has the following problems. In the prior art, as shown in FIG. 13, the master circuit 1 must wait for the next address <A before the data <D1> is output from the slave circuit.
2> could not be output, and there was a delay from the output of the address of the read request to the output of the data. Therefore, even when the master circuit continuously makes a read request to the slave circuit, the address <A1> is written on the address data bus.
If the data <D1> is not output from the slave circuit after outputting, the next address <A2> cannot be output, and there is a problem that it takes time to continuously read a plurality of data from the slave circuit. .

The present invention has been made in view of the above problems, and an object of the present invention is to reduce wasteful time when a master circuit continuously reads a plurality of data from a slave circuit. Another object is to provide a data processing device and a data processing method capable of reading a large number of data in a short time.

[0005]

The present invention has the following constitution in order to solve the above problems. According to a first aspect of the present invention, an address data bus for handling an address signal for reading and writing data and the data on the same bus, a master circuit connected to the address data bus, and the address data bus A slave circuit connected to, and a data processing device for writing the data to the slave circuit and reading the data from the slave circuit based on the address signal from the master circuit, The master circuit stabilizes the address signal output means for continuously outputting the address signal for reading the data from the slave circuit to the address data bus, and the continuously output address signal. Address confirmation signal for outputting an address confirmation signal for notifying the slave circuit of And a read final signal output means for outputting a read final signal for notifying the slave circuit of the last address signal of the continuously output address signals, and the slave circuit outputs the data. A memory that stores the address signal in association with the address signal, an address signal determination unit that determines whether the address signal output from the master circuit is the address signal addressed to its own slave circuit, and an address signal determination unit that determines the address signal. A memory output means for sequentially outputting, from the memory, the data corresponding to the address signal continuously output from the master circuit to the address data bus by the address confirmation signal when the address signal is addressed to the slave circuit. When,
Output data storage means for temporarily storing the data sequentially output from the memory by the memory output means, and the data stored in the output data storage means after the end of the read final signal are sequentially transferred to the address data bus. And a data output means for outputting. According to a second aspect of the present invention, the address signal output means writes the data between the address signals for reading the data continuously output from the slave circuit to the address data bus. For outputting the address signal and the data to the slave circuit, and the memory output means outputs the address signal and the data for writing the data addressed to its own slave circuit. The data processing apparatus according to claim 1, wherein the output from the memory is stopped. According to a third aspect of the present invention, a plurality of the slave circuits are connected to the address data bus, and the plurality of slave circuits count the address confirmation signal and output the slaves that are continuously output. The data output means includes an order storage means for storing the order of the address signal addressed to the slave circuit of the address signals for reading the data from the circuit, and the data output means stores the order stored in the order storage means. The data processing apparatus according to claim 1 or 2, wherein the data is output in accordance with the above.
A fourth aspect of the present invention is directed to an address data bus for handling an address signal for reading and writing data and the data on the same bus, a master circuit connected to the address data bus, and the address data. A data processing method comprising: a slave circuit connected to a bus, for writing the data to the slave circuit and reading the data from the slave circuit based on the address signal from the master circuit. The address signal for reading the data from the master circuit from the slave circuit is continuously output to the address data bus, and the address signal continuously output from the master circuit is stable. Address confirmation signal for notifying the slave circuit of A final read signal for notifying the slave circuit of the address signal at the end of the address signal, the slave circuit storing the data in association with the address signal, and the master circuit in the slave circuit. When the slave circuit determines whether the address signal output from the circuit is the address signal addressed to its own slave circuit, and when the slave circuit determines that the address signal is addressed to its own slave circuit, the master circuit outputs the address determination signal from the master circuit. The stored data corresponding to the continuously output address signals is sequentially output, the sequentially output data is temporarily stored, and the temporarily stored data is stored after the end of the read final signal. A data processing method is characterized in that the data is sequentially output to the address data bus. A fifth aspect of the present invention is to write the data between the address signals for reading the data from the slave circuit continuously outputting from the master circuit to the address data bus. Outputting the address signal and the data to the slave circuit, and stopping the output of the data while the address signal and the data for writing the data to the slave circuit are being output. A data processing method according to claim 4 is characterized. A sixth aspect of the invention is to connect a plurality of the slave circuits to the address data bus, count the address confirmation signal, and read the data from the continuously output slave circuits. 6. The order of the address signal addressed to each slave circuit among the address signals for storing the address signal is stored, and the data is output from each slave circuit according to the stored order. Data processing method.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment according to the present invention, FIG. 2 is a block diagram showing a master circuit shown in FIG. 1, and FIG. 3 shows a slave circuit shown in FIG. It is a block.

According to the embodiment of the present invention, the master circuit 1 for managing data transmission / reception and the slave circuits X, Y, Z for data transmission / reception in accordance with an instruction from the master circuit 1 have address data buses 100 and 6 respectively. The control signals of six types are connected by signal lines, and the six types of control signals include an address strobe 102, an output data confirmation signal 103, a read final signal 104, a data strobe 105, and input data. An address strobe 102, which is composed of a confirmation signal 106 and a read / write signal 107, makes each slave circuit judge the address signal output to the address data bus 100, and output data notifying that the output address signal or data is stable. The confirmation signal 103 and the output address signal are the final address signals. Read final signal 104 to inform the
A data strobe 105 for notifying each slave circuit of the data output to the address data bus 100 and notifying the slave that the data waiting state is written, and a read for determining whether it is a read request or a write request. The / write signal 107 is output from the master circuit 1, and the input data confirmation signal 106 indicating that the output data from each slave circuit is stable is output from each slave circuit.

The master circuit 1 is an oscillator 10 that outputs a clock 200 for controlling the timing of the master circuit 1.
And an address data transmitting / receiving unit 2 for transmitting an address signal to the address data bus 100 and transmitting / receiving data.
Control signal management unit 21 that manages 0 and 6 types of control signals
And a control unit 22 that controls the master circuit.

The oscillator 10 outputs a clock 200 which serves as a reference for control timing in the master circuit 1.

The address data transmitter / receiver 20 outputs the data to be stored in the slave circuit, receives the data output to the slave circuit, identifies the slave circuit and the location of the data stored in the slave circuit. The output of the address signal and the output of all the slave circuits are performed.

The control signal management unit 21 includes an address strobe 102, an output data confirmation signal 103, a read final signal 104, a data strobe 105, an input data confirmation signal 106, and a read / write signal 10.
7 and the input data confirmation signal 106 are monitored.

The control unit 22 controls the timing of the address data transmission / reception unit 20 and the control signal management unit 21 with reference to the clock 200 from the oscillator 10.

When a read request is issued to the slave circuit, the read / write signal 107 is maintained in the read request state, the address strobe 102 is output simultaneously with the transmission of the address signal, and the address output on the address data bus 100 is output. When the signal is stable, the output data confirmation signal 103 is output. When the address signal output for the read request is the final address signal, the final read signal 10 is output at the same time when the address signal is output.
4 is output and the final address signal and the final read signal 1
After outputting 04, the data strobe 105 is output. Then, by inputting the input data confirmation signal 106,
The data output to the slave circuit is taken in, and the output of the data strobe 105 is stopped when the input data confirmation signal 106 ends.

When a write request is issued to the slave circuit, the read / write signal 107 is set to the write request state, the address strobe 102 is output simultaneously with the transmission of the address signal, and the address signal output on the address data bus 100 is output. Is stabilized, the output data confirmation signal 103 is output. Next, the data strobe 105 is output at the same time as the data transmission, and the address data bus 1
When the data output on 00 is stable, the output data confirmation signal 103 is output.

The slave circuit X is an oscillator 1 that outputs a clock 201 for controlling the timing of the slave circuit X.
1, a first latch circuit 30 that temporarily holds an address signal from the address data bus 100, and a second latch circuit 3 that temporarily holds data from the address data bus 100.
1, an OR circuit 32 to which the data strobe 105 and the read / write signal 107 are input, and a first buffer 33 for outputting data to the address data bus 100.
A register 34 for storing the address information of its own slave circuit, a comparator 35 for comparing the address signal from the address data bus 100 with the address information stored in the register 34, and a data control for controlling the slave circuit. 36, a second buffer 37 for outputting an address signal from the address data bus 100 to the memory 38,
It comprises a memory 38 for storing data and a data buffer 39 for temporarily storing output data.

The oscillator 11 outputs a clock 201 which serves as a reference for control timing in the slave circuit X.

The first latch circuit 30 is connected to the address data bus 100, temporarily holds an address signal sent from the master circuit 1 via the address data bus 100, and holds the address strobe 102 and the output data decision signal 103. Accordingly, the latch address 300 is used as the comparator 35, the second buffer 37, and the data buffer 39.
Output to.

The second latch circuit 31 is connected to the address data bus 100, temporarily holds the data sent from the master circuit 1 through the address data bus 100, and outputs the latch signal 320 from the OR circuit 32. The data held by the data confirmation signal 103 is input data 3
Output as 11.

The OR circuit 32 has a data strobe 105.
And the read / write signal 107 are ORed, that is, when the data strobe 105 indicates the data and the read / write signal 107 indicates the data, the latch signal 320 is output to the second latch circuit 31. Output.

The first buffer 33 outputs the memory buffer output data 391 from the data buffer 39 to the address data bus 100 according to the first buffer control signal 367 from the data controller 36, and at the same time, the data controller 3
The data decision signal 361 from 6 outputs the input data decision signal 106 to the master circuit 1.

The register 34 stores in advance address information for recognizing whether or not the address signal output from the master circuit 1 onto the address data bus 100 is output to its own slave circuit. It outputs its own address signal 340 to 35.

The comparator 35 compares the latch address 300 from the first latch circuit 30 with the own address signal 340 from the register 34, and when it determines that the latch address 300 is to the own slave circuit, it outputs the data. Controller 3
The self-selection signal 350 is output to the No. 6 signal.

The data controller 36 controls the slave circuit X with the clock 201 from the oscillator 11 as a reference, and includes the output data confirmation signal 103 and the read final signal 1.
04, the data strobe 105, the input data confirmation signal 106, the read / write signal 107, and the comparator 35.
And a self-selection signal 350 from the master circuit 1 are input, and it is determined by these input signals whether the request of the master circuit 1 is a read request or a write request and various controls are performed.

When the request from the master circuit 1 is a read request, the address control signal 364 for the data buffer 39 causes the latch address 300 held by the first latch circuit 30 to be stored in the data buffer 39, and the prefetch signal for the data buffer 39 is stored. The latch address 300 stored by 360 is output to the memory 38 as the output memory address 371, and the data corresponding to the output memory address 371 is output as the memory output data 310 to the data buffer 39 by the memory control signal 363 for the memory 38 and the data buffer is output. The memory output data 310 is stored in 39. Then, by the data strobe 105 notifying that the read final signal 104 is input from the master circuit 1 which is constantly monitored and ready to receive the data, that is, the data strobe 105 after the input of the read final signal 104, the data buffer 39 To output the data control signal 368 for the first buffer 33 to the memory output data 310 stored in the data buffer as the memory buffer output data 391, and to output the first buffer control signal 3 to the first buffer 33.
67 causes the address data bus 100 to output the data requested by the master circuit 1. Then, in order to inform the master circuit 1 that the data has been output onto the address data bus 100, the first buffer 33 outputs the input data finalization signal 106 to the master circuit 1 by the data finalization signal 361 to the first buffer 33. . When the request from the master circuit 1 is a read request, the second
The second buffer control signal 365 for the buffer 37 inhibits the output of the latch address 300 to the memory 38, and the latch circuit control signal 366 for the second latch circuit 31 inhibits the output of the input data 311 to the memory 38. .

When the request from the master circuit 1 is a write request, the second buffer control signal 365 for the second buffer 37 permits the output of the latch address 300 to the memory 38 and the latch circuit for the second latch circuit 31. Input data 311 according to the control signal 366
Output to the memory 38, and the memory control signal 363 for the memory 38 stores the input memory address 370 from the buffer 37 and the input data 311 from the second latch circuit 31 in the memory 38.

The second buffer 37 includes a first latch circuit 30.
And outputs the latch address 300 from the input address to the memory 38 as an input memory address 370. The data controller 3 determines whether to output the input memory address 370.
It is controlled by the second buffer control signal 365 from No. 6.

The memory 38 outputs the output memory address 37 by the output memory address 371 from the data buffer 39 when the request of the master circuit 1 is a read request.
The data corresponding to 1 is output to the data buffer 39 as the memory output data 310, and when the request of the master circuit 1 is a write request, the input memory address 370 from the buffer 37 and the input data 311 from the second latch circuit 31 are output. Memorize

The data buffer 39 is configured to temporarily store a plurality of latch addresses 300 and data corresponding to the latch addresses 300, and a pre-read signal 360 from the data controller 36 causes the first latch circuit 30 to output data. The memory that outputs the latch address 300 to the memory 38 as the output memory address 371, temporarily stores the memory output data 310 corresponding to the output memory address 371 from the memory 38, and then stores it by the data control signal 368 from the data controller 36. The output data 310 is output to the first buffer 33 as the memory buffer output data 391.

In this embodiment, the slave circuit Y and the slave circuit Z have the same structure as the slave circuit X described above.

Next, the operation of the present embodiment will be described with reference to FIGS.
This will be described in detail with reference to FIG.

FIG. 4 is a diagram showing the timing when the master circuit 1 according to the present invention makes a read request to the slave circuit X once, and FIG. 5 is shown in FIG. 5 from the master circuit 1 to the slave circuit X according to the present invention. FIG. 6 is a diagram showing the timing when a write request is made once to the slave circuit X, and FIG. 6 is a diagram showing the timing when a read request is made three times in succession from the master circuit 1 to the slave circuit X according to the present invention. Yes, Figure 7
FIG. 8 is a diagram showing the timing when the master circuit 1 according to the present invention makes a write request to the slave circuit X three times in succession. FIG. 8 is a diagram showing the timing when the master circuit 1 according to the present invention reads the slave circuit X. FIG. 9 is a diagram showing a timing when a request, a write request, and a read request are sequentially made, and FIG.
FIG. 10 is a diagram showing the timing when the master circuit 1 according to the present invention sequentially makes a read request to the slave circuit X, a read request to the slave circuit Y, and a read request to the slave circuit Z. FIG. FIG. 11 is a diagram showing the timing when the master circuit 1 according to the first embodiment makes a write request to the slave circuit X, the write request to the slave circuit Y, and the write request to the slave circuit Z in order, and FIG. 11 shows the master circuit according to the present invention. FIG. 3 is a diagram showing the timing when a read request is made to slave circuit X, a write request is made to slave circuit Y, and a read request is made to slave circuit Z in order from 1;

First, the master circuit 1 is set to the slave circuit X 1
The operation when the read request is made once will be described with reference to FIG.

The master circuit 1 includes an address data bus 10
0, the address <A1> corresponding to the slave circuit X is output, and the address strobe 102 is output to notify the slave circuit X that the address <A1> is output on the address data bus 100, and a read request is issued. Since it is only once, the read final signal 104 is output to notify the slave circuit X that the read request is final.
Further, the read / write signal 107 is maintained in the read request state. Next, when the output address <A1> becomes stable, the output data confirmation signal 103 notifies the slave circuit X that the address has been confirmed.
Next, on the address data bus 100, the address signal <A
After the output of 1> is completed, the output of the address strobe 102 is stopped and the data strobe 105 is output to stand by.

The slave circuit X has an address strobe 1
02 and the output data determination signal 103, the address <A1> from the master circuit 1 is transferred to the first latch circuit 30.
It is held at and is output as the latch address 300. Address output as latch address 300 <A1>
Is compared with the self-address signal 340 output from the register 34 in the comparator 35, and the slave circuit X is selected. Therefore, the self-selection signal 350 for the data controller 36 is selected. Output. Data controller 3
6 recognizes from the read / write signal 107 that the request from the master circuit 1 is a read request, outputs an address control signal 364 to the data buffer 39, and the latch address 300 from the first latch circuit 30 at this time. The address <A1> output as
Store th. Next, the data controller 36 outputs the prefetch signal 360 to the data buffer 39, and outputs the first address <A1> stored in the data buffer 39 to the memory 38 as the output memory address 371. Further, the memory control signal 363 is output to the memory 38, the data <D1> corresponding to the address <A1> is output from the memory 38 to the data buffer 39 as the memory output data 310, and the first data buffer 39 is output. Store. Next, the data controller 36 detects the input of the read final signal 104 and the input of the data strobe 105, and the master circuit 1 outputs the data <
It recognizes that it is ready to receive D1>, outputs the data control signal 368 to the data buffer 39, and stores the first data <D1 stored in the data buffer 39.
> Is output as the memory buffer output data 391,
A first buffer control signal 367 is sent to the first buffer 33.
To output the data <D1> to the address data bus 100.
Is output. At this time, a data confirmation signal 361 is output to notify the master circuit 1 that the state of the data <D1> output onto the address data bus 100 has been determined, and the input data confirmation signal 10 is output via the first buffer 33.
Output as 6. During the above operation, the data controller 36 controls the latch circuit control signal 366 and the buffer control signal 365 so as not to perform input / output from the latch circuit 31 and the second buffer 37.

The master circuit 1 uses the input data confirmation signal 106
Of the slave circuit X, and recognizes that the data <D1> output from the slave circuit X to the address data bus 100 is confirmed, and the state of the address data bus 100 at that time, that is, the data from the slave circuit X < Take in D1>. When the input data confirmation signal 106 output from the slave circuit X ends, it is determined that the output of the data <D1> from the slave circuit X ends, and the output of the data strobe 105 is stopped.

Next, from the master circuit 1 to the slave circuit X, 1
The operation when the write request is made twice will be described with reference to FIG.

The master circuit 1 includes an address data bus 10
0, the address <A1> corresponding to the slave circuit X is output, and the address strobe 102 is output to notify the slave circuit X that the address <A1> is output on the address data bus 100, and a write request is issued. The slave circuit X is notified of the existence by the read / write signal 107, and when the output address <A1> becomes stable, the output data finalizing signal 103 informs the slave circuit X that the address signal <A1> is finalized. To notify you. Next, the output of the address strobe 102 is stopped, the data <D1> is output on the address data bus 100, and the data strobe 105 outputs the data <D1> on the address data bus 100. Data notified to X and output <D
1> becomes stable, the slave circuit X confirms that the data <D1> is confirmed by the output data confirmation signal 103.
Notify. Then, after the output of the data <D1> is completed, the output of the data strobe 105 is stopped.

The slave circuit X has an address strobe 1
02 and the output data determination signal 103, the address <A1> from the master circuit 1 is transferred to the first latch circuit 30.
It is held at and is output as the latch address 300. Address output as latch address 300 <A1>
Is compared with the self-address signal 340 output from the register 34 in the comparator 35, and the slave circuit X is selected. Therefore, the self-selection signal 350 for the data controller 36 is selected. Output. Data controller 3
6 recognizes that the request from the master circuit 1 is a write request by the read / write signal 107, and inputs the latch address 300 to the memory 38 via the second buffer 37 and the memory address 37 by the second buffer control signal 365.
0 is output and the address is set by the memory control signal 363.
A1> is stored in the memory 38. Further, the latch control signal 366 causes the data on the address data bus 100 <
D1> is temporarily held by the second latch circuit 31, the held data <D1> is output to the memory 38 as the input data 311, and the control signal 363 stores the data <D1> in the memory 38 together with the address <A1>.

Next, from the master circuit 1 to the slave circuit X 3
Operation when read requests are issued consecutively Figure 6
Will be described with reference to.

The master circuit 1 includes an address data bus 10
Address signal <A1> corresponding to slave circuit X on 0
And address strobe 102 to output address signal <A1 on address data bus 100.
> Is output to the slave circuit X, and read /
The write signal 107 is maintained in the read request state, and when the output address <A1> becomes stable, the output data confirmation signal 103 notifies the slave circuit X that the address has been confirmed. Next, the master circuit 1 maintains the output of the address strobe 102 for the second and third read requests to the slave circuit X, outputs the address <A2> and the address <A3>, and outputs the output address. When <A2> and the address <A3> are stable, the output data confirmation signal 103 is output. At the time of the third read request, the master circuit 1 outputs the read final signal 1 at the same time as the output of the address <A3> in order to inform that the third address <A3> is final.
04 is output. Next, after the output of the address signal <A3> corresponding to the slave circuit X on the address data bus 100 is completed, the output of the address strobe 102 is stopped and the data strobe 105 is output to stand by.

The slave circuit X first stores the address <A1> and the data <D1> relating to the first read request in the first place of the data buffer 39. That is, the address <A1> from the master circuit 1 is set to the first by the address strobe 102 and the output data confirmation signal 103.
It is held by the latch circuit 30 and output as the latch address 300. The address <A1> output as the latch address 300 is compared with the own address signal 340 output from the register 34 by the comparator 35, and the slave circuit X is selected. A self-selection signal 350 is output indicating that the circuit has been selected.
The data controller 36 recognizes from the read / write signal 107 that the request from the master circuit 1 is a read request, outputs the address control signal 364 to the data buffer 39, and the first latch circuit 30 at this time outputs the address control signal 364. The address <A1> output as the latch address 300 is stored first in the data buffer 39. Next, data controller 3
6 outputs the prefetch signal 360 to the data buffer 39, and outputs the address <A1> stored first in the data buffer 39 to the memory 38 as the output memory address 371. Further memory control signal 363
Is output to the memory 38, and the data <D1 corresponding to the address <A1> is output from the memory 38 to the data buffer 39.
> Is output as the memory output data 310 and is stored in the first of the data buffer 39. Next, since the read final signal 104 indicating the end of the read request is not input at the time of the first read request, the address <A2> and the data <D2> related to the second read request are stored in the data buffer 2 The read final signal 104 that stores the second signal and indicates the last read request at the time of the second read request.
Is not input, the address <A3> and the data <D3> required for the third read request are stored in the third position of the data buffer 39 by the same operation. Next, the data controller 36 detects the input of the read final signal 104 and the input of the data strobe 105, and the master circuit 1 is ready to receive the data <D1>, <D2>, and <D3> on the address data bus 100. That is, the data control signal 368 is output to the data buffer 39, and the data <D2> and the data <D3> stored in order from the first data <D1> stored in the data buffer 39 are output to the memory buffer. The data is output as data 391, the first buffer control signal 367 is output to the first buffer 33, and the data <D1>, <D2>, and <D3 are output to the address data bus 100.
> Are output in order. At this time, the address data bus 10
0 outputs the data confirmation signal 361 for notifying the master circuit 1 that the states of the data <D1>, <D2>, and <D3> output on 0 are determined.
The data is output as the input data confirmation signal 106 via 3 respectively.

The master circuit 1 receives the input data confirmation signal 106
Of the data <D1>, <D2 output from the slave circuit X to the address data bus 100.
>, <D3> is confirmed, the state of the address data bus 100 at that time, that is, the slave circuit X
The data <D1>, <D2>, and <D3> from each are fetched. When the third input data confirmation signal 106 output from the slave circuit X ends, it is determined that the output of the data <D3> from the slave circuit X has ended, and the output of the data strobe 105 is stopped.

Next, from the master circuit 1 to the slave circuit X 3
Operation when write requests are made consecutively Figure 7
Will be described with reference to.

The operation when the master circuit 1 makes three consecutive write requests to the slave circuit X is the same as when the master circuit 1 described with reference to FIG. 5 makes only one write request to the slave circuit X. The operation is repeated three times.

Next, the operation when the master circuit 1 issues a read request, a write request, and a read request in order to the slave circuit X will be described with reference to FIG.

The master circuit 1 includes an address data bus 10
Address signal <A0> corresponding to slave circuit X on 0
And address strobe 102 to output address signal <A0 on address data bus 100.
> Is output to the slave circuit X, and read /
The write signal 107 is maintained in the read request state, and when the output address <A0> becomes stable, the output data confirmation signal 103 notifies the slave circuit X that the address has been confirmed. Next, the master circuit 1
While the address strobe 102 is maintained, the address <A1> corresponding to the slave circuit X is output on the address data bus 100, and the slave circuit X is notified by the read / write signal 107 that it is a write request and is output. When the address <A1> becomes stable, the address signal <
The slave circuit X is notified that A1> has been established. Next, the output of the address strobe 102 is stopped, the data <D1> is output onto the address data bus 100, and the data strobe 105 is output to output the data <D1> onto the address data bus 100. X is notified, and when the output data <D1> becomes stable, the output data confirmation signal 103 causes
The slave circuit X is notified that the data <D1> has been determined. After the data <D1> has been output,
The output of the output data confirmation signal 103 and the data strobe 105 is stopped. Next, it is output to the slave circuit X that the address <A2> corresponding to the slave circuit X is output onto the address data bus 100 and the address strobe 102 is output to output the address <A2> onto the address data bus 100. Then, the read final signal 104 is output to notify the slave circuit X that the read request is final. Further, the read / write signal 107 is maintained in the read request state. When the output address <A2> becomes stable, the output data confirmation signal 103 causes
The slave circuit X is notified that the address has been determined, and the address signal <A2 is sent to the address data bus 100.
After the output of> is completed, the output of the address strobe 102 is stopped and the data strobe 105 is output to stand by.

The slave circuit X performs the first read request from the master circuit 1 in the same manner as the one read request from the master circuit 1 to the slave circuit X described with reference to FIG. However, since the write request is continuously issued from the master circuit 1, the data controller 36 that recognizes the write request stores the data <D0> corresponding to the address <A0> stored first in the data buffer 39 in the memory 38.
The operation of reading from the memory 38 is stopped halfway, and the same operation as the one-time write request from the master circuit 1 to the slave circuit X described with reference to FIG. D1> and are stored. After the storage of the address <A1> and the data <D1> in the memory 38 is completed, the operation when the master circuit 1 described with reference to FIG. The data <D0> and <D2> are output to the address data bus 100 by the same operation.

The master circuit 1 receives the input data confirmation signal 106
Of the data <D0>, <D2> output from the slave circuit X to the address data bus 100.
Is recognized and the state of the address data bus 100 at that time, that is, the data <D0> and <D2> from the slave circuit X are respectively fetched. The second input data confirmation signal 10 output from the slave circuit X
When 6 ends, data from slave circuit X <D3>
The output of the data strobe 105 is stopped when it is determined that the output of the data is finished.

Next, the operation when the master circuit 1 issues a read request to the slave circuit X, a read request to the slave circuit Y, and a read request to the slave circuit Z in order will be described with reference to FIG.
Will be described with reference to.

The master circuit 1 operates in the same manner as when the master circuit 1 described with reference to FIG. 6 makes a read request to the slave circuit X three times in succession.
Address <A1> for the slave circuit Y, address <A2> for the slave circuit Y, address <A for the slave circuit Z
3> is continuously output, the data strobe 105 is output, and the device stands by.

Each slave circuit has addresses <A1>, <A1>,
When A2> and <A3> are recognized as own addresses, the master circuit 1 described with reference to FIG.
The operation is basically the same as the operation when the read request is made once, but the following control is performed regarding the output of data to the address data bus 100.

The data controller 36 of each slave circuit counts the number of times the output data confirmation signal 103 is output, and stores the order in which the read request is issued to its own slave circuit.
It should be noted that the output frequency of the output data confirmation signal 103 is counted only when the read / write signal 107 is a read request. Each slave circuit is a master circuit 1
Data is output by the input of the final read signal 104 and the input of the data strobe 105 from the device. First, the slave circuit X requested to read first outputs the data <D1> to the address data bus 100. At the same time, when the output data <D1> is determined, the input data determination signal 106 is output to the master circuit 1. The slave circuits other than the slave circuit X (slave circuit Y, slave circuit Z) count the input data confirmation signal 106 output from the slave circuit X, and when their own slave circuits reach the order in which the read request is issued, the slave circuits themselves are slaves. The data stored in the data buffer 39 of the circuit is output onto the address data bus 100. That is, following the output of the data <D1> from the slave circuit X, the second slave-requested slave circuit Y outputs the data <D2>.
To the address data bus 100, and finally the slave circuit Z, which is thirdly requested to read, outputs the data <D3> to the address data bus 100.

Next, the operation when the master circuit 1 sequentially issues a write request to the slave circuit X, a write request to the slave circuit Y, and a write request to the slave circuit Z is shown in FIG.
This will be described with reference to 0.

The master circuit 1 operates in the same manner as the operation when the master circuit 1 makes a write request three times in succession to the slave circuit X described with reference to FIG.
Address <A1>, data <A1>, address <A2>, data <A2> for slave circuit Y, address <A3>, data <A3 for slave circuit Z.
> Is continuously output.

The operation in each slave circuit (slave circuit X, slave circuit Y, slave circuit Z) is the same as the operation when one write request is made from the master circuit 1 to the slave circuit X described with reference to FIG. It is the same.

Next, the operation when the master circuit 1 sequentially issues a read request to the slave circuit X, a write request to the slave circuit Y, and a read request to the slave circuit Z is shown in FIG.
This will be described with reference to FIG.

The master circuit 1 operates in the same manner as when the master circuit 1 makes a read request, a write request, and a read request to the slave circuit X in the order described with reference to FIG. <A1>, address <A2> for slave circuit Y, data <A2>,
The address <A3> for the slave circuit Z is continuously output, and the data strobe 105 is output to stand by.

The operation of the slave circuit X and the slave circuit Z is the same as the operation when the master circuit 1 makes a read request once to the slave circuit X described with reference to FIG. Is similar to the operation when one write request is made from the master circuit 1 to the slave circuit X described with reference to FIG. 5, except that the address data bus 1 for data from the slave circuit X and the slave circuit Z is used.
At the time of output to 00, the output data confirmation signal 103 is not counted when the read / write signal 107 is a write request, so the slave circuit X transfers the data <A1> to the address data bus 100. Following output, slave circuit Z outputs data <A3>
Is output to the address data bus 100.

As described above, according to the present embodiment, after the data read request to the slave circuit, the next request can be made in the delay time until the slave circuit outputs the data. It is possible to reduce the time required to continuously read data and read a large number of data in a short time.

Furthermore, even when there is a read request to a plurality of slave circuits, the next request can be made within the delay time until the data is output from each slave circuit.
This has the effect that a large amount of data can be read in a short time.

It should be noted that the present invention is not limited to the above embodiments, and it is apparent that the embodiments can be modified appropriately within the scope of the technical idea of the present invention. Further, the number, position, shape, etc. of the above-mentioned constituent members are not limited to those in the above-mentioned embodiment, and the number, position, shape, etc. suitable for carrying out the present invention can be adopted. In addition, in each figure, the same components are denoted by the same reference numerals.

[0063]

The data processing device and the data processing method according to the present invention are arranged such that after the data read request to the slave circuit is made,
The next request can be made in the delay time until the data is output from the slave circuit, the time when reading data continuously can be shortened, and a large amount of data can be read in a short time. It has the effect of being able to.

Furthermore, the data processing device and data processing method of the present invention make the next request in the delay time until the data is output from each slave circuit even when there are read requests to the plurality of slave circuits. This has the effect that it can be performed and a large amount of data can be read in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data processing device according to the present invention.

FIG. 2 is a detailed block diagram of a master circuit shown in FIG.

FIG. 3 is a detailed block diagram of a slave circuit shown in FIG.

FIG. 4 is a diagram showing the timing when the master circuit 1 according to the present invention makes a read request to the slave circuit X once.

FIG. 5 is a diagram showing the timing when the master circuit 1 according to the present invention makes a write request to the slave circuit X once.

FIG. 6 is a diagram showing the timing when the master circuit 1 according to the present invention makes a read request to the slave circuit X three times in succession.

FIG. 7 is a diagram showing a timing when the master circuit 1 according to the present invention issues a write request to the slave circuit X three times in succession.

FIG. 8 is a diagram showing a timing when a master circuit 1 according to the present invention sequentially issues a read request, a write request, and a read request to the slave circuit X.

FIG. 9 is a diagram showing the timing when the master circuit 1 according to the present invention sequentially issues a read request to the slave circuit X, a read request to the slave circuit Y, and a read request to the slave circuit Z.

FIG. 10 is a diagram showing the timing when the master circuit 1 according to the present invention sequentially makes a write request to the slave circuit X, a write request to the slave circuit Y, and a write request to the slave circuit Z.

FIG. 11 is a diagram showing timings when the master circuit 1 according to the present invention sequentially issues a read request to the slave circuit X, a write request to the slave circuit Y, and a read request to the slave circuit Z.

FIG. 12 is a block diagram showing a configuration of a data processing device according to a conventional technique.

FIG. 13 is a diagram showing timing when a read request is issued from a master circuit to a slave circuit according to a conventional technique.

[Explanation of symbols]

1 Master circuit 10, 11, 12, 13 oscillator 20 Address / data transceiver 21 Control signal management unit 22 Control unit 30 First Latch Circuit 31 second latch circuit 32 OR circuit 33 First buffer 34 registers 35 comparator 36 Data Controller 37 Second buffer 38 memory 39 data buffer 100 address data bus 102 address strobe 103 Output data confirmation signal 104 Read final signal 105 data strobe 106 Input data confirmation signal 107 read / write signal 200, 201, 202, 203 clocks 300 Latch address 310 Memory output data 311 input data 320 Latch signal 340 Own address signal 350 self-selection signal 360 look-ahead signal 361 Data confirmation signal 363 Memory control signal 364 address control signal 365 second buffer control signal 366 Latch circuit control signal 367 First buffer control signal 368 data control signal 370 Input memory address 371 Output memory address 391 Memory buffer output data X, Y, Z slave circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-332851 (JP, A) JP-A-11-15778 (JP, A) JP-A-8-212171 (JP, A) JP-A-5- 143533 (JP, A) JP 62-78639 (JP, A) Tokumei HEI 8-503800 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 12/00-12 / 06 G06F 13/16-13/18 G06F 13/36-13/38

Claims (6)

(57) [Claims] 1. An address data bus for handling an address signal for reading and writing data and the data on the same bus, a master circuit connected to the address data bus, and a slave connected to the address data bus. A data processing device having a circuit and performing writing of the data to the slave circuit and reading of the data from the slave circuit based on the address signal from the master circuit, wherein the master circuit comprises: Address signal output means for continuously outputting the address signal for reading the data from the slave circuit to the address data bus; and for the slave circuit that the continuously output address signal is stable. An address confirmation signal output means for outputting an address confirmation signal to be notified, And a read final signal output unit that outputs a read final signal that notifies the slave circuit of the last address signal of the address signals that are continuously output, and the slave circuit outputs the data as the address signal. A memory that stores the data in association with each other, an address signal determination unit that determines whether or not the address signal output from the master circuit is the address signal addressed to the own slave circuit, and an address signal determination unit that determines the address signal addressed to the own slave circuit. A memory output unit for sequentially outputting, from the memory, the data corresponding to the address signal continuously output from the master circuit to the address data bus by the address confirmation signal when the address signal is determined to be the address signal; The output means temporarily stores the data sequentially output from the memory. A data processing device comprising: force data storage means; and data output means for sequentially outputting the data stored in the output data storage means to the address data bus after the end of the read final signal. 2. The address signal output means for writing the data between the address signals for reading the data continuously output from the slave circuit to the address data bus. And the data are output to the slave circuit, and the memory output means outputs from the memory while the address signal for writing the data addressed to the slave circuit and the data are output. The data processing device according to claim 1, wherein the data processing device is stopped. 3. A plurality of the slave circuits are connected to the address data bus, and the plurality of slave circuits count the address confirmation signal and read the data from the continuously output slave circuits. In order to store the order of the address signal of the address signal addressed to its own slave circuit for storing, the data output means, the data output means stores the data according to the order stored in the order storage means. The data processing apparatus according to claim 1, wherein the data processing apparatus outputs the data. 4. An address data bus for handling an address signal for reading and writing data and the data on the same bus, a master circuit connected to the address data bus, and a slave connected to the address data bus. A data processing method for writing the data to the slave circuit and reading the data from the slave circuit based on the address signal from the master circuit. The slave circuit continuously outputs the address signal for reading the data from the slave circuit to the address data bus, and notifies the slave circuit that the continuously output address signals are stable. Address confirmation signal to be generated, and the continuously output address A read final signal for notifying the slave circuit of the address signal at the end of the signal, storing the data in the slave circuit in association with the address signal, and outputting to the slave circuit from the master circuit. The determined address signal is the address signal addressed to its own slave circuit, and when the slave circuit determines the address signal addressed to its own slave circuit, the address confirmation signal causes the address determination signal to continuously output from the master circuit. The stored data corresponding to the output address signal is sequentially output, the sequentially output data is temporarily stored, and the temporarily stored data is sequentially stored in the address after the end of the read final signal. A data processing method characterized by outputting to a data bus. 5. The address signal and the data for writing the data between the address signal for reading the data from the slave circuit continuously output from the master circuit to the address data bus. 5. The data is output to the slave circuit, and the output of the data is stopped while the address signal for writing the data to the slave circuit and the data are being output.
Described data processing method. 6. A plurality of the slave circuits are connected to the address data bus, the address confirmation signal is counted, and the address signals for reading the data from the continuously output slave circuits are provided. 6. The data processing method according to claim 4, wherein the order of the address signals addressed to each slave circuit in the inside is stored, and the data is output from each slave circuit according to the stored order.