JP3449945B2 - Bus control method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system such as a personal computer or a workstation,
In particular, the present invention relates to a bus control technology of an information processing system.

[0002]

2. Description of the Related Art In an information processing system, a control technique of a synchronous bus in which a plurality of modules connected on a bus transfer data in synchronization with a common clock is disclosed in, for example, Japanese Patent Laid-Open No. 61-11872. Techniques are known.

The control of such a conventional synchronous bus will be described.

FIG. 16 shows the timing of data transfer on the bus by the conventional synchronous bus control technique.

In the figure, CLK is a synchronous clock for data transfer which each module connected to the bus has in common, A
/ D is a multiplexed address and data, ADRV is an address valid signal indicating that the address on A / D is valid, WRITE is a write access designation signal, and the data on A / D is valid. Is also shown. WAIT is a wait signal that informs the master side that the slave side buffer is not ready to accept data.

When one module makes a write access to another module using a bus composed of such signals, first, the bus master indicates an address valid indicating that the address on the A / D is valid. Signal ADRV
And the address of the access destination is output on the A / D at the same time.

On the other hand, the slave module, which has detected the write access to its own module based on the decoding result of this address and the write access designation signal WRITE, waits at the timing of the synchronous clock CLK when it is ready to take in the data. Capture valid data on A / D. If the slave module is not ready to take in the data, it requests the extension of the data cycle by the wait signal WAIT which informs the master side that it is not ready to receive the data.

The master module extends the data cycle during this time, if the wait signal is asserted. When the slave module is ready to take in data, it takes in valid data on the A / D at the timing of the synchronous clock CLK and negates the wait signal.
When the wait signal is negated, the master module terminates the data cycle and ends the access.

As described above, according to the conventional synchronous bus control technique, the data transfer is performed while the wait signal informs whether or not the data transfer is possible by the handshake method.

[0010]

However, according to the conventional technique, when data transfer is performed, since a wait cycle is inserted prior to the data transfer, an overhead occurs corresponding to the wait cycle and the data is transferred. There has been a problem that the transfer rate decreases, the bus occupation time increases, and the bus usage efficiency decreases.

Therefore, an object of the present invention is to provide a bus control method capable of improving the bus usage efficiency by reducing the overhead of data transfer.

[0012]

[Means for Solving the Problems] To achieve the above object,
According to the present invention, in an information processing system having a bus and a plurality of modules connected to the bus, a module (master) that has acquired the right to use the bus controls the bus to transfer the module (thread). A) a bus control method for transferring addresses and data in synchronism with a clock common to each module, wherein the master transfers the address or data to the slave when the bus usage right is acquired. The module that has executed the transfer cycle to relinquish the right to use the bus and, as a slave, receives the transferred address or data. An acknowledgment report, which reports the receipt, is sent to all other modules in the cycle after the specified number of transfer cycles, and the acknowledgment is acknowledged. The bus control method characterized in that the module that has executed the transfer as a master in the cycle a predetermined number before the cycle in which the report is sent confirms the success or failure of the transfer cycle executed from the sent acknowledge report. provide.

Further, the present invention has the following objects to attain the above objects.
When the master acquires the right to use the bus, it executes the transfer cycle to transfer the address or data to the slave to abandon the right to use the bus, and accepts the transferred address or data even though it is the slave. The module that could not do so sends a retry request for requesting re-execution of the transfer to all other modules in a cycle after a predetermined number of transfer cycles that could not be accepted,
The module that executed the transfer as the master in the cycle a predetermined number before the cycle in which the retry request was sent is:
A bus control method is characterized in that the transfer executed in the cycle a predetermined number of times before is executed again.

Further, according to the present invention, the master, after acquiring the right to use the bus, transmits the address or the data.
When the module that has received the transferred address or data as a slave has a transfer error, it executes the transfer cycle of transferring to the slave An error report for reporting the occurrence of a transfer error is sent to all other modules in a cycle a predetermined number after the cycle in which the transfer error occurred, and the predetermined cycle is sent from the cycle in which the error report is sent. A module that has executed a transfer as a master in a few cycles ago provides a bus control method characterized by confirming the contents of a transfer in which a transfer error has occurred from the error report sent.

[0015]

According to the bus control method of the present invention, for example, the master transfers the address or data to the slave without confirming the status of the slave when it acquires the right to use the bus. And release the right to use the bus without confirming the success or failure of the transfer. On the other hand, as a slave, the module that has received the transferred address or data, for each of the transfer cycles for the received address or data,
An acknowledgment report for reporting receipt is sent to all other modules in a cycle after a predetermined number of times from the corresponding transfer cycle, and transfer is executed as a master in the cycle a predetermined number before the cycle in which the acknowledge report is sent. The module confirms the success or failure of the transfer of the transfer cycle executed based on the transmitted acknowledgment report, and takes measures only when the transfer is not successful.

Therefore, the transfer to the slave that is ready to accept the transfer from the master can be realized only in the cycle of actually transferring the address and data, and the bus usage efficiency can be improved.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the information processing system according to the present invention will be described below.

First, FIG. 1 shows the configuration of an information processing system according to this embodiment.

As shown in the figure, the information processing system according to the present embodiment has a system bus 50 to 60, a plurality of modules 0 to 7 (100 to 107) connected thereto, and a bus between the modules 100 to 107. It has a bus arbiter 108 for arbitrating usage rights, an I / O bus 100 connected to each of the modules 100 to 107, and an I / O device connected to the I / O bus. In addition, each module 100-107
In some cases, only a single I / O device is connected to. Each module incorporates a system bus interface device, and mediates data transfer between the system buses 50 to 60 and an I / O bus or I / O device (not shown).

Further, in the figure, 61 is a bus right request signal (BREQ0) for requesting the bus right from the module 0 to the bus arbiter 108, and 62 is the bus arbiter 10.
8 is a bus use permission signal (BGRANT0) for giving permission to use the bus to the module 0 (100), and 63 is a last signal from the module 0 (100) to the bus arbiter 108 that the next cycle is the last cycle of the bus use. It is a cycle signal (LC0). Similarly, 64 is a bus right request signal (BREQ1) from the module 1 (101) to the bus arbiter 108, 65 is a bus use permission signal (BGRANT1) from the bus arbiter 108 to the module 1 (101), and 66 is a module 1 (10).
From 1), the next cycle is delayed for the bus arbiter 108.
The last cycle signal (LC1) that conveys that it is the last cycle of the bus use, 67 is a bus right request signal (BREQ) from the module 7 (107) to the bus arbiter 108.
7) and 68 from the bus arbiter 108 to the module 7 (1
07) bus use permission signal (BGRANT7),
69 is the module 7 (107) to the bus arbiter 108
Is a last cycle signal (LC7) that tells that the next cycle is the last cycle of bus usage .

In the system bus, 50 is an address and data bus (A / D), 51 is a command signal (CMD) for designating the type of access, and 52 is a valid address on the A / D. Address valid signal (ADRV), 53 is a data valid signal (DATAV) indicating that the data on the A / D is valid, and 54 is a transaction acknowledge signal that informs the master side that the slave side has surely received the address or data. (TACK), 55 is a retry request signal (RETRY) from the slave side to the master side, 56 is a synchronous error (SERR) which is an error report signal synchronized with a transaction from the slave side to the master side,
Reference numeral 57 is an asynchronous error (AERR) which is an error report signal not synchronized with the transaction, 58 is a freeze signal (FRZ) which is output at the same time as the synchronous error 56 and the asynchronous error 57 and freezes other than the diagnostic transaction, and 59 is a freeze signal. A bus reset signal (BRST) for releasing the freeze signal after the error recovery by the diagnostic transaction is completed, and 60 is a synchronization clock signal (CLK) commonly supplied to each module.

Next, FIG. 2 shows the internal structure of each module.

In the figure, reference numeral 1 is a system bus interface device which is responsible for bus control, and is a system bus 50-60.
Is connected to an I / O bus or I / O device (not shown), and mediates data transfer between the two.

Reference numeral 2 is a system bus control unit inside the system bus interface apparatus 1, and 3 is an I / O bus or I / O bus connected via the system bus interface apparatus 1.
It is a control unit that controls the O device. Further, 4 is a conversion unit for matching the interface between the system bus control unit 2 and the I / O bus or I / O control unit 3, 5 is a bus arbitration control unit, 6 is an error control unit, and 7 is a system bus control. Section, 8 is a retry control section, 9 is a received data buffer, 10 is an address conversion section, 11 is a data conversion section,
12 is a protocol conversion unit, 13 is an address input / output unit, 1
4 is a data input / output unit, 15 is an I / O (bus) control unit, 1
6 is an output last stage buffer, 17 is an input first stage buffer, 18 is an address output buffer, 19 to 22 are burst write data buffers, 23 is an input address buffer, 24 is an input address, a data check buffer,
Reference numeral 25 is an arbitration control signal, 26 is an address bus, 27 is a data bus, 28 is a control signal, and 29 is an error checker for detecting a transfer error from data parity or the like.

The data transfer operation in such an information processing system will be described below.

First, the read access operation will be described. In the present embodiment, the read access is realized by an activation sequence in which the read request side outputs an address to the system bus and a response sequence in which the requested side outputs data to the system bus in response to the received address. Further, in the present embodiment, the read access operation is realized by the split operation in which the activation sequence and the response sequence are independent.

In this embodiment, when a certain module performs a read access operation, first, a bus right request signal (BREQ) is used to request the bus right to the bus arbiter 108. At the same time, the last cycle signal (LC) is output at the same time to notify the bus arbiter 108 that the bus right will be relinquished in one cycle.

Then, a bus use permission signal (BGRAN
When T) is asserted, the address and the like are output to the system bus, and the use of the bus ends.

FIG. 3 shows a case where the modules 0 (100) to 3 (103) simultaneously assert BREQ for read access.

As shown, module 0 (100)
To module 3 are asserting BREQ at the same time. However, module 0 (100), module 1
It is assumed that the bus use priority is higher in the order of (101), module 2 and module 3.

As shown, the third cycle, the fourth cycle, the fifth cycle, the sixth cycle, and the bus master is switched in the order of module 0 (100), module 1 (101), module 2 and module 3. . That is, even if the bus master switches every cycle, the idle cycle is not inserted.

FIG. 4 shows a sequence for activating read access.

As shown in the figure, in this sequence, the activation module that asserts BREQ and LC for read access receives the bus use permission signal (BGRANT) from the bus arbiter 108 and the address on the A / D becomes valid. The address valid signal (ADRV) 52 indicating that there is a valid signal
/ D) Outputs the access destination address to 50. Also,
At the same time, the fact that the type of access is read access is output to the command signal (CMD) 51, and the activation sequence ends. The read access activation cycle is the fourth cycle in the figure.

Next, the response sequence is shown in FIG.

The module receiving the read access command and address acquires the bus right when the data to be responded is ready, and then the data valid signal (DATAV) indicating that the data on the A / D is valid.
Enable 53, address and data bus (A / D)
The response data is output to 50. At the same time, it outputs to the command signal (CMD) 51 that the type of access is read response access. The response cycle is the seventh cycle in the figure.

The response sequence of the read access at the burst read is shown in FIG. In the figure, the response cycles are the fifth to eighth cycles.

As described above, in the present embodiment, it is assumed that the receiving data buffer (FIGS. 1 and 9) of each module can take in data at any time without using a wait signal as in the conventional case, After acquiring the bus right, be sure to transfer 1
Data or address is performed in one cycle to reduce bus occupation time and improve bus use efficiency.

Also in the write access sequence, as shown in FIG. 7, both the address transfer and the data transfer can be completed in one cycle. The activation cycle for transferring an address and the like and activating the write access is the fourth cycle, and the response cycle for transferring the data and the like is the fifth cycle.

Also in the burst write sequence, as shown in FIG. 8, the transfer cycle can be always performed in one cycle for each data or address. In FIG. 8, the activation cycle for transferring an address is the third cycle, and the response cycle for transferring four data in response to this is the fourth to seventh cycles.

As described above, assuming that the buffer for receiving data (FIGS. 1 and 9) of each module can take in data at any time, after acquiring the bus right, the transfer cycle must be 1 data or 1 per address. Although the cycle is performed, the capacity of the buffer is limited, and therefore, if continuous write access is performed, the buffer may overflow and cannot receive data.

Therefore, in the present embodiment, the transaction acknowledge signal (TAC) which informs the master side that the slave side has surely received the address or the data.
K) 54, a retry request signal (RETRY) 55 for the slave side to request the master side for retransmission, and a synchronous error (SERR) 56 for the slave side to report the occurrence of an error to the master side in synchronization with the transaction. Further, these signals are always output by the slave side two cycles after the transfer cycle from the master side so that the master side can recognize whether or not the transaction from the master side has succeeded.

Further, since each module can determine whether or not the buffer overflows by the transaction at the time when the transaction is activated, the retry request signal (RETRY) 55 of the slave side module is not asserted. Do only for the first cycle of a transaction. Note that at the time of burst write or burst read, since the information of the burst transfer amount is included in the CMD in the first cycle of the transaction, in this case as well, each module overflows the buffer at the time when the transaction is activated. It is possible to determine whether or not.

FIG. 9 shows an example of a retry sequence for read access.

In the illustrated example, the slave asserts RETRY in the sixth cycle in response to the first activation cycle (fourth cycle), while the master in the eleventh cycle.
In the cycle, the startup cycle is executed again and the retry is successful.

Next, FIG. 10 shows an example of a sequence when a transfer error occurs.

In the illustrated example, when a paridi error occurs in the second data transfer cycle (sixth cycle) of the burst write access, a synchronous report which is an error report signal synchronized with the transaction from the slave side to the master side. The error (SERR) 56 is output from the slave side two cycles after the cycle in which the paridi error has occurred (eighth cycle). Further, the slave side module freezes the bus by the freeze signal (FRZ) 58 at the same time as making an error report. On the other hand, when the synchronous error (SERR) 56 is asserted, the master side receives the synchronous error (SER).
R) 56 is asserted, and the error occurrence cycle, error address, etc. are obtained from the stored information about each cycle executed in the past and stored as logging information.

Also, a synchronous error (SERR) 5
When 6 is asserted, the error occurrence cycle held by the module on the master side by a predetermined device responsible for error recovery processing, such as a processor connected to any module,
After recovering the error based on the logging information such as the error address (somewhere between the ninth cycle and the eighteenth cycle), the bus reset signal (BRST) 59
The freeze is released by and the normal transaction is restarted (from the 24th cycle).

As described above, in this embodiment, since the master side receives the error report completely synchronized with the transaction, it is possible to log even the information indicating in which cycle the error occurred, and analyze the error thereafter. The error recovery process can be facilitated.

Next, a case will be described in which the system bus having such a protocol is used to perform broadcast, which is a broadcast type transaction for simultaneously writing to a plurality of modules.

In such a broadcast type transaction, it is indispensable to write to a plurality of modules at the same time. Therefore, only some modules cause buffer overflow and some modules can be written and some modules are not. There are cases.

Therefore, in this embodiment, at the time of broadcasting, the master always waits for two cycles after the transfer cycle while holding the bus right, and whether the retry request signal (RETRY) 55 is present or whether the synchronous error report (SERR) is present. ) Make sure you have 56.

Further, here, a transaction acknowledge signal (TACK) 54 and a retry request signal (RET
RY) 55, synchronous error report (SERR) 56
However, since it may be asserted simultaneously by a plurality of modules, it is prepared as a wired OR signal. Then, if there is a retry request, the master holds the bus right and executes the same access cycle again. On the other hand, each slave that received the transfer also
Be sure to wait until two cycles after the transfer cycle, without holding the processing of the transferred data, holding it, and waiting for another thread.
Check whether there is a retry request signal (RETRY) 55 from the network or whether there is a synchronous error report (SERR) 56, and whether there is a retry request signal (RETRY) 55 or there is a synchronous error report (SERR) 56. If received, the received data will be discarded.

A sequence example at the time of the broadcast access operation is shown in FIGS.

FIG. 11 shows an example in which one broadcast access succeeds, and FIG. 12 shows an example in which broadcast access succeeds.

In the example shown in FIG. 11, if the retry request signal (RETRY) 55 and the synchronous error report (SERR) 56 are not present even after waiting for the bus right until two cycles after the transfer cycle, the master becomes , LC is issued and the bus right is released. On the other hand, in the example shown in FIG. 12, RETRY is asserted in the fifth and ninth cycles for the broadcast access initiated by the master in the third cycle and the seventh cycle. Master is
Against the assertion of the R ETRY, seventh, multiplied by the activation of the retry eleventh cycle, for the third retry is not R ETRY is asserted at the 13th cycle, after two cycles of the last transfer cycle the After confirming that there was no error report by the 14th cycle, LC is issued, the bus right is released, and the transaction is ended.

Here, FIG. 13 shows the procedure executed by the master performing the broadcast access. As shown in the figure, after starting the processing at 150, the master executes broadcast type write access at 151 for all modules. Then, in 152, it is determined whether or not there is a retry request for 151, and if there is, a return is made to 151 and re-execution of broadcast type write access for all modules. If there is no retry request for 151 in 152, wait for 2 cycles in 153 to check whether all slaves have received data without error. If an error report is received in 154, transition to 155 and perform error processing, and there is no error report. It ends at 156.

If the module that receives continuous write access is a bus converter that performs protocol conversion between buses of different hierarchies, the module is stored in the buffer until the data of the last cycle. After confirming that it has been received, the transfer to the bus of a different layer is started.

By the way, as described above, since the cycle in which the retry request is returned is two cycles after the start cycle, as shown in FIG. 14, the same module continuously writes access to a specific module ( Third
And (started in the fifth cycle), the second write access continues to be sent from the master side even though the first write access was not accepted due to a buffer overflow or the like due to the bus interface device. Done. Then, only this second write access may be accepted. That is, there may be a case where the access order is not guaranteed.

Therefore, in the present embodiment, in the case where continuous write access is performed from the same module to a specific module, in the bus interface device for activating, in the case of continuous write, the write access is always performed after the write access is completed. After waiting for two cycles, after confirming that the retry request is not returned, the next write access is activated.

FIG. 15 shows a sequence example in the case where continuous write access is performed from the same module to a specific module.

In the illustrated example, the master confirms that the retry request is not asserted in the fifth cycle after finishing the first write access in the fourth cycle,
The second access is activated in the 7th cycle.

In this embodiment, a retry request,
The reason why the acknowledge and the error report are performed after two cycles is that the error checker (FIG. 1, FIG. 1, in order to reduce the load on the system bus as much as possible and to increase the frequency of the clock CLK that is the transfer synchronization clock). 29) and the like are not directly connected to the system bus.

As described above, according to the information processing system according to the present embodiment, the handshake such as the ready control for confirming whether the other module can accept the data is not performed, and the data transfer source is not used. Since the transfer cycle is completed without confirming the acknowledge signal of the slave which is the transfer destination, the bus usage efficiency can be improved and the access speed can be improved.

Regarding error processing, since error reporting is performed in synchronization with each cycle of a transaction, the master module that has received the error reporting can perform detailed logging up to the location of the cycle in which the error occurred. Recovery processing after an error occurs can be facilitated.

[0065]

As described above, according to the present invention, it is possible to provide a bus control method capable of improving bus utilization efficiency by reducing the overhead of data transfer.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a system bus interface device.

FIG. 3 is a time chart showing a sequence when bus right requests for read access conflict.

FIG. 4 is a time chart showing a read access startup sequence.

FIG. 5 is a time chart showing a response sequence of read access.

FIG. 6 is a time chart showing an activation sequence of read access by burst transfer.

FIG. 7 is a time chart showing a write access sequence.

FIG. 8 is a time chart showing a write access sequence by burst transfer.

FIG. 9 is a time chart showing a retry sequence of read access.

FIG. 10 is a time chart showing a sequence when a transfer error occurs.

FIG. 11 is a time chart showing a sequence at the time of broadcast access.

FIG. 12 is a time chart showing a retry sequence at the time of broadcast access.

FIG. 13 is a flowchart showing a procedure performed by a master during broadcast access.

FIG. 14 is a time chart showing a retry sequence when a continuous write access similar to a normal write access is performed.

FIG. 15 is a time chart showing a sequence of continuous write access.

FIG. 16 is a timing chart showing a write access sequence according to a conventional bus control technique.

[Explanation of symbols]

1 ... System bus interface device 2 ... System bus control unit 3 ... Control unit 4 ... Conversion unit 5 ... Bus arbitration control unit 6 ... Error control unit 7 ... System bus control Part 8 ... Retry control part 9 ... Received data buffer 10 ... Address conversion part 11 ... Data conversion part 12 ... Protocol conversion part 13 ... Address input / output part 14 ... Data Input / output unit 15 ... I / O (bus) control unit 16 ... Output last stage buffer 17 ... Input first stage buffer 18 ... Address output buffer 19, 20, 21, 22 ... Burst Write data buffer 23 ... Input address buffer 24 ... Input address, data check buffer 25 ... Arbitration control signal 26 ... Address bus 27 ... Data bus 28 ... Control signal 29 ... Error checker 50 ... Data bus (A / D) 51 ... Command signal (CMD) 52 ... Address valid signal (ADRV) 53 ... Data valid Signal (DATAV) 54 ... Transaction acknowledge signal (TAC
K) 55 ... Retry request signal (RETRY) 56 ... Synchronous error (SERR) 57 ... Asynchronous error (AERR) 58 ... Freeze signal (FRZ) 59 ... Bus reset signal (BRST) 60 ... Synchronization clock signal (CLK)

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideaki Genma Inventor Hideaki Genma 810 Shimoimaizumi, Ebina City, Kanagawa, Ltd. Hitachi Office Co., Ltd. Hitachi, Ltd. Central Research Laboratory (72) Inventor Kazuhiko Komori 810 Shimoimaizumi, Ebina City, Kanagawa Stock Company Hitachi Office System Design & Development Center (72) Inventor, Koichi Okazawa 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Microelectronics equipment development laboratory (56) Reference JP 61-32161 (JP, A) JP 2-159658 (JP, A) JP 63-66654 (JP, A) JP JP-A-2-56048 (JP, A) JP-A-1-321543 (JP, A) JP-A-6 3-89956 (JP, A) Japanese Patent Laid-Open No. 2-19954 (JP, A) Okada, 3 persons, characteristic evaluation of split transfer system bus, IEICE Technical Report, April 20, 1990, CPS Y90-4, p. 25-32 (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 13/36 510 G06F 13/362 520

Claims (6)

(57) [Claims] 1. A bus for transferring at least one of address and data, a bus use right request signal, and a next cycle
A signal line provided separately from the bus for transferring a last cycle signal and an acknowledge signal indicating that it is the last cycle of bus use, and a plurality of modules connected to the bus and the signal line. In the bus control method for an information processing device, the master module that has acquired the bus use right by outputting the bus use right request signal outputs the last cycle signal in the same cycle as the bus use right request signal, And releasing the bus use right acquired for transferring at least one of the data to the slave module which is the transfer destination in one cycle before receiving an acknowledge signal for the transfer from the slave module, It receives the address or data transferred from the master module. That when, in the cycle after a predetermined number of cycles to which the transfer is executed,
The master module outputs an acknowledge signal for the transfer, and the master module confirms the success or failure of the transfer by receiving an acknowledge signal in a cycle after a predetermined number of cycles from the cycle in which at least one of the address and the data is transferred to the slave module. A bus control method characterized by the above. 2. A bus for transferring at least one of address and data, a bus use right request signal, and a next cycle
A signal line provided separately from the bus for transferring a last cycle signal and a retry signal indicating that it is the last cycle of bus use; and a plurality of modules connected to the bus and the signal line. In the bus control method for an information processing device, the master module that has acquired the bus use right by outputting the bus use right request signal outputs the last cycle signal in the same cycle as the bus use right request signal, And releasing the bus use right acquired for transferring at least one of the data to the transfer destination slave module in one cycle before receiving a retry signal for the transfer from the slave module, the slave module To receive the address or data transferred from the master module If it is not possible, the master module outputs a retry signal for the transfer in a predetermined number of cycles after the transfer is executed, and the master module outputs the address and / or data to the slave module in a predetermined cycle. A bus control method, wherein when a retry signal is received in a few cycles, the transfer is performed again. 3. A bus for transferring at least one of address and data, a bus use right request signal, and a next cycle
A signal line provided separately from the bus for transferring a last cycle signal and an error signal indicating that it is the last cycle of bus use; and a plurality of modules connected to the bus and the signal line. In the bus control method for an information processing device, the master module that has acquired the bus use right by outputting the bus use right request signal outputs the last cycle signal in the same cycle as the bus use right request signal, And releasing the bus use right acquired for transferring at least one of the data to the transfer destination slave module in one cycle before receiving an error signal for the transfer from the slave module, If there is a transfer error in the address or data received from the master module, In a cycle after a predetermined number of cycles after the transfer of the address or data, an error signal for the transfer is output, and the master module outputs a predetermined cycle from the cycle in which at least one of the address and the data is transferred to the slave module. A bus control method characterized by confirming a transfer error occurring in the transfer by receiving an error signal in a cycle several times later. 4. An information processing apparatus, and a bus for transferring at least one of addresses and data, bus request signal, the final support of the next cycle bus use
A plurality of modules connected to the bus and the signal line, the signal line being provided separately from the bus for transferring a last cycle signal and an acknowledge signal that convey that it is an icle; The master module that has obtained the bus use right request signal by outputting the bus use right request signal outputs the last cycle signal in the same cycle as the bus use right request signal, and outputs at least one of the address and the data. The bus use right acquired for transferring to the slave module which is the transfer destination of the plurality of modules is released in one cycle before receiving an acknowledge signal for the transfer from the slave module, and the slave module is The address or data transferred from the master module Taking only, in the cycle after a predetermined number of cycles to which the transfer is executed,
The master module outputs an acknowledge signal for the transfer, and the master module confirms the success or failure of the transfer by receiving an acknowledge signal in a cycle after a predetermined number of cycles from the cycle in which at least one of the address and the data is transferred to the slave module. An information processing device characterized by the above. 5. An information processing apparatus, and a bus for transferring at least one of addresses and data, bus request signal, the final support of the next cycle bus use
A plurality of modules connected to the bus and the signal line, the signal line being provided separately from the bus for transferring a last cycle signal and a retry signal that convey that it is an icle; The master module that has obtained the bus use right request signal by outputting the bus use right request signal outputs the last cycle signal in the same cycle as the bus use right request signal, and outputs at least one of the address and the data. The bus use right acquired to transfer to the slave module which is the transfer destination of the plurality of modules is released in one cycle before the retry signal for the transfer is received from the slave module, and the slave module is Receives the address or data transferred from the master module If it cannot, the master module outputs a retry signal for the transfer in a cycle after a predetermined number of cycles after the transfer, and the master module transfers at least one of address and data to the slave module. The information processing apparatus, wherein when a retry signal is received in a cycle after a predetermined number of times from, the transfer is performed again. 6. An information processing apparatus, and a bus for transferring at least one of addresses and data, bus request signal, the final support of the next cycle bus use
A signal line provided separately from the bus to transfer the last cycle signal and the error signal saying that a cycle, a plurality of modules connected to the bus and the signal lines, a plurality The master module that has obtained the bus use right request signal by outputting the bus use right request signal outputs the last cycle signal in the same cycle as the bus use right request signal, and outputs at least one of the address and the data. The bus use right acquired for transferring to the slave module which is the transfer destination of the plurality of modules is released in one cycle before receiving an error signal for the transfer from the slave module, and the slave module is There is a transfer error in the address or data received from the master module. In this case, in a cycle after a predetermined number of cycles from which the address or data transfer was executed, the master module outputs an error signal for the transfer, and the master module transfers at least one of address and data to the slave module. An information processing apparatus, wherein a transfer error occurring in the transfer is confirmed by receiving an error signal in a cycle after a predetermined number of times.