JP2000035924A - Bus control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the control method of a bus capable of improving bus using efficiency by reducing the overheads of data transfer. SOLUTION: A module (master) 100 for performing read access to the module 101 to be a slave requests a bus using right to a bus arbiter by BREQ signals 61 and reports that the next cycle is the last cycle to be used by the master by LC signals 63. Then, when bus use is permitted by BGRANT signals 62, the read access is activated by transferring an address to the slave 101 by using the A/D 50 of a system bus in the next cycle and the bus using right is released. Only in the case of being incapable of receiving the transferred address, the slave 101 asserts RETRY signals 55 two cycles after the transfer cycle of the non-received address. The module 100 which executes transfer two cycles before the cycle in which the RETRY signals 55 are asserted executes the transfer executed two cycles before again.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system such as a personal computer and a workstation.
In particular, the present invention relates to a bus control technology of an information processing system.

[0002]

2. Description of the Related Art In an information processing system, a technique for controlling a synchronous bus in which a plurality of modules connected on a bus transfer data in synchronization with a common clock is disclosed in, for example, JP-A-61-11872. Techniques are known.

[0003] Control of such a conventional synchronous bus will be described.

FIG. 16 shows the timing of data transfer on the bus according to the conventional synchronous bus control technique.

[0005] In the figure, CLK is a data transfer synchronous clock commonly owned by each module connected to the bus, A
/ D is a multiplexed address and data, ADRV is an address valid signal indicating that the address on the A / D is valid, WRITE is a write access designation signal, and the data on the A / D is valid Are also shown. WAIT is a wait signal that informs the master that the slave buffer is not ready to accept data.

When one module performs write access to another module using a bus composed of such signals, first, the bus master issues an address validity signal indicating that an address on the A / D is valid. Signal ADRV
And outputs the address of the access destination on the A / D at the same time.

On the other hand, the slave module, which detects the write access to its own module based on the decoded result of the address and the write access designation signal WRITE, is ready to take in the data at the timing of the synchronous clock CLK if it is ready to take in the data. Import valid data on A / D. If the slave module is not ready to take in data, a data cycle extension is requested by a wait signal WAIT that informs the master side that it is not ready to accept data.

When the wait signal is asserted, the master module extends the data cycle during this time. When the slave module is ready to take in the data, it takes in valid data on the A / D at the timing of the synchronous clock CLK and negates the wait signal.
When the wait signal is negated, the master module terminates the data cycle and terminates the access.

As described above, according to the conventional synchronous bus control technique, data transfer is performed while communicating whether or not data transfer is possible in a handshake manner with a wait signal.

[0010]

However, according to the prior art, when performing data transfer, a wait cycle is inserted prior to the data transfer, so that an overhead is generated by the amount of the wait cycle and the data is transferred. There has been a problem that the transfer speed is reduced, the bus occupation time is increased, and the bus use efficiency is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bus control method capable of improving bus use efficiency by reducing data transfer overhead.

[0012]

To achieve the above object,
According to the present invention, in an information processing system having a bus and a plurality of modules connected to the bus, a module (master) that has acquired the right to use the bus controls the bus to control a transfer destination module (thread). A bus control method for transferring addresses and data in synchronization with a clock common to each module, wherein the master transfers the address or data to the slave after acquiring the right to use the bus. The module that has received the transferred address or data as a slave performs a transfer cycle to perform the transfer cycle, and releases the right to use the bus. An acknowledgment report for acknowledgment is sent to all other modules in a cycle after a predetermined number of times from the corresponding transfer cycle, and the acknowledgment report is sent. A bus control method, characterized in that the module which has executed the transfer as the master in the predetermined number of cycles before the cycle in which the report has been sent confirms the success or failure of the executed transfer cycle from the sent acknowledgment report. provide. Further, according to the present invention, in order to achieve the above object, when the master acquires the right to use the bus, the master executes a transfer cycle for transferring an address or data to the slave and relinquishes the right to use the bus. However, the module that cannot receive the transferred address or data receives a retry request for re-executing the transfer in another cycle after a predetermined number of transfer cycles from the transfer cycle that could not receive the retry request. All modules
A module that has performed a transfer as a master in the predetermined number of cycles before the cycle in which the retry request has been transmitted, and executes the transfer performed in the predetermined number of previous cycles again. A bus control method is provided.

Further, according to the present invention, when the master obtains the right to use the bus, the master scans the address or data.
The module that has received the transferred address or data as a slave executes a transfer cycle for transferring to the slave and relinquishes the right to use the bus. An error report for reporting the occurrence of a transfer error is sent to all other modules in a cycle after a predetermined number of cycles from the cycle in which the transfer error occurred, and the error report is sent from the cycle in which the error report was sent. A module which has performed a transfer as a master several cycles ago provides a bus control method characterized by confirming the contents of the transfer in which a transfer error has occurred from the transmitted error report.

[0014]

According to the bus control method of the present invention, for example, when the master acquires the right to use the bus, the transfer cycle for transferring the address or data to the slave without confirming the status of the slave. To relinquish the right to use the bus without confirming the success or failure of the transfer. On the other hand, as a slave, the module having received the transferred address or data, for each of the transfer cycles for the received address or data,
An acknowledgment report for reporting receipt is transmitted to all other modules in a cycle after a predetermined number of cycles from the corresponding transfer cycle, and transfer is performed as a master in the cycle before the predetermined number of cycles before the acknowledgment report is transmitted. The module confirms the success or failure of the transfer of the transfer cycle executed based on the transmitted acknowledgment report, and takes measures only if the transfer is not successful.

Therefore, the transfer to the slave ready to accept the transfer from the master can be realized only by the cycle of actually transferring the address and data, and the bus use efficiency can be improved.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the information processing system according to the present invention will be described below.

FIG. 1 shows the configuration of an information processing system according to the present embodiment.

As shown in the figure, the information processing system according to the present embodiment comprises a system bus 50 to 60, a plurality of modules 0 to 7 (100 to 107) connected thereto, and a bus between each of the modules 100 to 107. It has a bus arbiter 108 for arbitrating usage rights, an I / O bus 100 connected to each of the modules 100 to 107, and an I / O device connected to the I / O bus. Also, each module 100 to 107
In some cases, only a single I / O device is connected. Each module has a built-in system bus interface device and mediates data transfer between the system buses 50 to 60 and an I / O bus or I / O device (not shown).

In the figure, reference numeral 61 denotes a bus request signal (BREQ0) for requesting a bus use right from the module 0 to the bus arbiter 108;
A bus use permission signal (BGRANT0) for giving a bus use permission from module 8 to module 0 (100), 63 is a last signal from module 0 (100) to bus arbiter 108 indicating that the next cycle is the last cycle of bus use. This is a cycle signal (LC0). Similarly, 64 is a bus right request signal (BREQ1) from the module 1 (101) to the bus arbiter 108, 65 is a bus use permission signal (BGRANT1) from the bus arbiter 108 to the module 1 (101), and 66 is a module 1 (10
A last cycle signal (LC1) for transmitting the last cycle from 1) to the bus arbiter 108, a bus request signal (BREQ7) from the module 7 (107) to the bus arbiter 108, and a bus request signal (BREQ7) from the module 7 (107) to the module 7 (107). ), 69 is a module 7 (10
7) is a last cycle signal (LC7) for notifying the bus arbiter 108 of the last cycle.

In the system bus, reference numeral 50 denotes an address and data bus (A / D), reference numeral 51 denotes a command signal (CMD) for specifying an access type, and reference numeral 52 denotes that an address on the A / D is valid. An address valid signal (ADRV), 53 is a data valid signal (DATAV) indicating that data on the A / D is valid, and 54 is a transaction acknowledge signal for notifying the master that the slave has received the address or data. (TACK), 55 is a retry request signal (RETRY) for the master on the slave side, 56 is a synchronous error (SERR) which is an error report signal synchronized with a transaction from the slave to the master,
57 is an asynchronous error (AERR) which is an error report signal not synchronized with the transaction; 58 is a freeze signal (FRZ) which is output simultaneously with the synchronous error 56 and the asynchronous error 57 to freeze other than the diagnostic transaction; A bus reset signal (BRST) for releasing the freeze signal after the error recovery by the diagnostic transaction is completed, and 60 is a synchronization clock signal (CLK) commonly supplied to each module.

Next, FIG. 2 shows the internal configuration of each module.

In the figure, reference numeral 1 denotes a system bus interface device for controlling buses, and system buses 50 to 60.
And an I / O bus or I / O device (not shown) to mediate data transfer between them.

Reference numeral 2 denotes a system bus control unit inside the system bus interface device 1, and 3 denotes an I / O bus or I / O bus connected through the system bus interface device 1.
The control unit controls the O device. 4 is a converter for matching the interface between the system bus controller 2 and the I / O bus or I / O controller 3; 5 is a bus arbitration controller; 6 is an error controller; and 7 is a system bus controller. Unit, 8 a retry control unit, 9 a receiving data buffer, 10 an address conversion unit, 11 a data conversion unit,
12 is a protocol conversion unit, 13 is an address input / output unit, 1
4 is a data input / output unit, 15 is an I / O (bus) control unit, 1
6 is an output last stage buffer, 17 is an input first stage buffer, 18 is an address output buffer, 19 to 22 are burst write data buffers, 23 is an input address buffer, 24 is an input address, a data check buffer,
25 is an arbitration control signal, 26 is an address bus, 27 is a data bus, 28 is a control signal, and 29 is an error checker for detecting a transfer error from data parity or the like.

Hereinafter, a data transfer operation in such an information processing system will be described.

First, the read access operation will be described. In this embodiment, read access is realized by a start sequence in which the read request side outputs an address to the system bus and a response sequence in which the requested side outputs data to the system bus in response to the address received. Further, in this embodiment, the read access operation is realized by the split operation in which the activation sequence and the response sequence are independent.

In this embodiment, when a certain module performs a read access operation, first, a bus right is requested to the bus arbiter 108 by a bus right request signal (BREQ). At this time, a last cycle signal (LC) is simultaneously output to notify the bus arbiter 108 of relinquishing the bus right in one cycle.

Then, a bus use permission signal (BGRAN)
When T) is asserted, an address or the like is output to the system bus, and the use of the bus is terminated.

FIG. 3 shows a case where the module 0 (100) to the module 3 (103) simultaneously assert BREQ for read access.

As shown, module 0 (100)
To module 3 assert BREQ at the same time. However, module 0 (100), module 1
(101) It is assumed that the priority order of bus use is higher in the order of module 2 and module 3.

As shown, the bus masters are switched in the order of the third cycle, the fourth cycle, the fifth cycle, and the sixth cycle in the order of module 0 (100), module 1 (101), module 2, and module 3. . That is, even if the bus master switches every cycle, no idle cycle is inserted.

FIG. 3 shows a sequence for activating read access.

As shown, in this sequence, when the activation module asserting BREQ and LC for read access receives the bus use permission signal (BGRANT) from the bus arbiter 108, the address on the A / D becomes valid. The address valid signal (ADRV) 52 indicating that the address data bus is present is enabled, and the address data bus (A
/ D) The address of the access destination is output to 50. Also,
At the same time, the fact that the type of access is read access is output to the command signal (CMD) 51, and the activation sequence ends. The start cycle of the read access is the fourth cycle in the figure.

Next, a response sequence is shown in FIG.

The module that has received the read access command and address acquires the bus right when the data to be responded is ready, and then a data valid signal (DATAV) indicating that the data on the A / D is valid.
53, address and data bus (A / D)
The response data is output to 50. At the same time, it outputs to the command signal (CMD) 51 that the type of access is read response access. The response cycle is the seventh cycle in the figure.

FIG. 5 shows a response sequence of the read access at the time of the burst read. In the figure, the response cycle is the fifth to eighth cycles.

As described above, in the present embodiment, it is assumed that the receiving data buffer (FIGS. 1 and 9) of each module can always take in data without using a wait signal or the like as in the prior art. After acquiring the bus right, be sure to transfer 1
This is performed in one cycle per data or address, thereby reducing the bus occupation time and improving the bus use efficiency.

In the write access sequence, as shown in FIG. 7, both address transfer and data transfer can be completed in one cycle. A start cycle for transferring an address or the like and starting a write access is a fourth cycle, and a response cycle for transferring data or the like is a fifth cycle.

Also, in the sequence at the time of burst write, as shown in FIG. 8, the transfer cycle can always be performed in one cycle per data or address. In FIG. 8, a start cycle for transferring an address is a third cycle, and a response cycle for transferring four data in response thereto is a fourth to a seventh cycle.

As described above, it is assumed that the receiving data buffers (FIGS. 1 and 9) of each module can take in data at any time, and after acquiring the bus right, the transfer cycle must be one data or one address per address. Although the operation is performed in cycles, the capacity of the buffer is limited, so that if write access or the like is performed continuously, the buffer may overflow and become unable to receive data.

Therefore, in this embodiment, a transaction acknowledge signal (TAC) for notifying the master that the slave has received the address or data has been received.
K) 54, a retry request signal (RETRY) 55 in which the slave requests the master to retransmit, and a synchronous error (SERR) 56 in which the slave reports to the master the error occurrence in synchronization with the transaction. In addition, these signals are always output by the slave side two cycles after the transfer cycle from the master side, so that the master side can recognize whether or not the transaction from the master side has succeeded.

Each module can determine whether or not the buffer overflows due to the transaction when the transaction is started. Therefore, the assertion of the retry request signal (RETRY) 55 of the slave module is Perform only for the first cycle of the transaction. At the time of burst write or burst read, information on the amount of burst transfer is included in the CMD in the first cycle of the transaction. In this case as well, when each module is activated, the buffer overflows due to the transaction. Can be determined.

FIG. 9 shows an example of a retry sequence for read access.

In the illustrated example, the slave asserts RETRY in the sixth cycle with respect to the first activation cycle (fourth cycle), and the master asserts RETRY in the sixth cycle.
The start cycle is executed again in the cycle, and the retry succeeds.

Next, FIG. 10 shows a sequence example when a transfer error occurs.

The example shown is a case where a parity error has occurred in the second data transfer cycle (sixth cycle) of the burst write access, and is a synchronous error report signal synchronized with a transaction from the slave to the master. An error (SERR) 56 is output from the slave side two cycles (eighth cycle) after the cycle in which the parity error has occurred. At the same time as reporting the error, the slave-side module freezes the bus with the freeze signal (FRZ) 58. On the other hand, when the synchronous error (SERR) 56 is asserted, the master side transmits the synchronous error (SERR).
R) 56 is asserted, an error occurrence cycle, an error address, and the like are obtained from the timing of the assertion and the stored information on each previously executed cycle, and are stored as logging information.

Further, a synchronous error (SERR) 5
6 is asserted, a predetermined device responsible for error recovery processing, such as a processor connected to one of the modules, causes an error generation cycle held by the module on the master side;
After recovering the error based on the logging information such as the error address (any timing between the ninth cycle and the eighteenth cycle), the bus reset signal (BRST) 59
To release the freeze and restart the normal transaction (after the 24th cycle).

As described above, in the present embodiment, the master side receives the error report completely synchronized with the transaction, so that it is possible to log information on in which cycle the error occurred, and analyze the error thereafter. Thus, error recovery processing can be facilitated.

Next, a case will be described in which a broadcast, which is a broadcast type transaction for simultaneously writing to a plurality of modules, is performed using a system bus having such a protocol.

In such a broadcast-type transaction, since it is essential to write to a plurality of modules at the same time, only some of the modules cause an overflow of the buffer, and some of the modules have been written and some have not. There may be cases.

Therefore, in this embodiment, at the time of broadcasting, the master always waits while holding the bus right until two cycles of the transfer cycle, and waits for the retry request signal (RETRY) 55 or the synchronous error report (SERR). ) Check if there is 56.

Here, the transaction acknowledge signal (TACK) 54 and the retry request signal (RET)
RY) 55, Synchronous error report (SERR) 56
However, since it may be asserted by a plurality of modules at the same time, it is prepared as a wired OR signal. Then, if there is a retry request, the master executes the same access cycle again while maintaining the bus right. On the other hand, each slave that received the transfer also
Until two cycles after the transfer cycle, the processing of the transferred data is not started and waits while holding the data.
It is checked whether there is a retry request signal (RETRY) 55 from the receiver or a synchronous error report (SERR) 56, and there is no retry request signal (RETRY) 55 or a synchronous error report (SERR) 56. If received, discard the received data.

FIGS. 11 and 12 show sequence examples at the time of the broadcast access operation.

FIG. 11 shows an example of successful broadcast access, and FIG. 12 shows an example of successful broadcast access.

In the example shown in FIG. 11, if there is no retry request signal (RETRY) 55 and synchronous error report (SERR) 56 even if the bus right is held until two cycles after the transfer cycle, the master is , LC and release the bus. On the other hand, in the example shown in FIG. 12, RETRY is asserted in the fifth and ninth cycles with respect to the broadcast access activated by the master in the third and seventh cycles. The master
For each RRETRY assertion, a retry is activated in the seventh and eleventh cycles. For the third retry, RRETRY is not asserted in the thirteenth cycle.
After confirming that there was no error report by the 14th cycle two cycles after the final transfer cycle, the LC is issued and the bus right is released to end the transaction.

FIG. 13 shows a procedure executed by the master performing the broadcast access. As shown in the drawing, the master starts processing at 150, and then executes broadcast-type write access for all modules at 151. Then, at 152, it is determined whether or not there is a retry request for 151, and if there is, the process returns to 151 to re-execute the broadcast-type write access for all modules. If there is no retry request for 151 in 152, it waits for two cycles in 153 and confirms whether all slaves have received data without error. If an error report is received in 154, it transits to 155 and performs error processing, and there is no error report The process ends at step 156.

If the module that receives the continuous write access is a bus converter that performs protocol conversion between buses of different hierarchies, the module is stored in the buffer until the data of the last cycle. The transfer to the bus of a different hierarchy is started after confirming the reception.

As described above, the cycle in which the retry request is returned is two cycles after the start cycle. Therefore, as shown in FIG. Third
And start-up in the fifth cycle), the second write access continues from the master side even though the first write access was not accepted due to buffer overflow or the like due to the bus interface device. Done. Then, only the second write access may be accepted. That is, the order of access may not be guaranteed.

Therefore, in the present embodiment, in the case where continuous write access is performed from the same module to a specific module, the bus interface device that starts up is used. After waiting for two cycles and confirming that no retry request is returned, the next write access is started.

FIG. 15 shows a sequence example in the case where continuous write access is performed from the same module to a specific module.

In the illustrated example, after the master completes the first write access in the fourth cycle, after confirming that the retry request is not asserted in the fifth cycle,
The second access is activated in the seventh cycle.

In this embodiment, the retry request
The reason for performing the acknowledgment and the error report two cycles later is to reduce the load on the system bus as much as possible and to increase the frequency of CLK, which is a transfer synchronization clock, by using an error checker (FIG. 1). 29) are not directly connected to the system bus.

As described above, according to the information processing system according to the present embodiment, the handshake such as the ready control for confirming whether or not the partner module can accept data is not performed. Ends the transfer cycle without confirming the acknowledge signal of the slave that is the transfer destination, so that the bus use efficiency can be improved and the access speed can be improved.

As for error processing, an error report is issued in synchronization with each cycle of a transaction, so that the master module receiving the error report can perform detailed logging up to the point of the cycle in which the error occurred, Recovery processing after an error has occurred can be facilitated.

[0064]

As described above, according to the present invention, it is possible to provide a bus control method capable of improving the bus use efficiency by reducing the data transfer overhead.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a system bus interface device.

FIG. 3 is a time chart showing a sequence when a bus right request for read access competes;

FIG. 4 is a time chart showing a start sequence of read access.

FIG. 5 is a time chart showing a read access response sequence.

FIG. 6 is a time chart showing a start sequence of read access by burst transfer.

FIG. 7 is a time chart showing a write access sequence.

FIG. 8 is a time chart showing a write access sequence by burst transfer.

FIG. 9 is a time chart showing a read access retry sequence.

FIG. 10 is a time chart showing a sequence when a transfer error occurs.

FIG. 11 is a time chart showing a sequence at the time of broadcast access.

FIG. 12 is a time chart showing a retry sequence at the time of broadcast access.

FIG. 13 is a flowchart showing a procedure performed by a master at the time of broadcast access.

FIG. 14 is a time chart showing a retry sequence when a continuous write access similar to a normal write access is performed.

FIG. 15 is a time chart showing a sequence of a continuous write access.

FIG. 16 is a timing chart showing a write access sequence according to a conventional bus control technique.

[Description of Signs] 1 ・ ・ ・ System bus interface device 2 ・ ・ ・ System bus control unit 3 ・ ・ ・ Control unit 4 ・ ・ ・ Conversion unit 5 ・ ・ ・ Bus arbitration control unit 6 ・ ・ ・ Error control unit 7 ・..System bus control unit 8 Retry control unit 9 Received data buffer 10 Address conversion unit 11 Data conversion unit 12 Protocol conversion unit 13 Address input / output unit 14 Data input / output unit 15 I / O (bus) control unit 16 Last output buffer 17 First input buffer 18 Address output buffers 19, 20, 21, 22: Burst write data buffer 23: Input address buffer 24: Input address and data check buffer 25: Arbitration control signal 6 Address bus 27 Data bus 28 Control signal 29 Error checker 50 Data bus (A / D) 51 Command signal (CMD) 52 Address valid Signal (ADRV) 53: Data valid signal (DATAV) 54: Transaction acknowledge signal (TAC)
K) 55: Retry request signal (RETRY) 56: Synchronous error (SERR) 57: Asynchronous error (AERR) 58: Freeze signal (FRZ) 59: Bus reset signal (BRST) 60: Synchronization clock signal (CLK)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideaki Genma 810 Shimo-Imaizumi, Ebina-shi, Kanagawa Prefecture Inside the Office System Design and Development Center, Hitachi, Ltd. (72) Inventor Tetsuhiko Okada 1-280, Higashi Koikebo, Kokubunji-shi, Tokyo Address Central Research Laboratory, Hitachi, Ltd. (72) Inventor Kazuhiko Komori 810 Shimoimaizumi, Ebina-shi, Kanagawa Prefecture Office System Design and Development Center, Hitachi, Ltd. (72) Inventor Koichi Okazawa Yoshida, Totsuka-ku, Yokohama, Kanagawa Prefecture No. 292, Hitachi, Ltd. Microelectronics Equipment Development Laboratory

Claims (6)

[Claims] 1. An information processing apparatus, comprising: a bus; a plurality of modules connected to the bus; and an acknowledgment signal line connected to the plurality of modules and provided separately from the bus for transferring an acknowledgment report. The master module that has acquired the right to use the bus controls the order in which the master module executes a transfer cycle of transferring at least one of an address and data to a slave module that is a transfer destination, and the master module further includes: After the transfer cycle, before the transfer of an acknowledgment report from the slave module to the transfer cycle, the slave module relinquishes the bus usage right and receives the transferred address or data. After a predetermined number of cycles, Controls the order in which the modules send acknowledgment reports that report receipt of the address and data, and the master module that has performed the transfer executes the master module by receiving the acknowledgment report in a predetermined number of cycles after the corresponding transfer cycle. An information processing apparatus for confirming the success or failure of a transfer cycle. 2. An information processing apparatus, comprising: a bus; a plurality of modules connected to the bus; and a retry signal line connected to the plurality of modules and provided separately from the bus for transferring a retry report. The master module that has acquired the right to use the bus controls the order in which the master module executes a transfer cycle of transferring at least one of an address and data to a slave module that is a transfer destination, and the master module further includes: After the transfer cycle, before the transfer of a retry report for the transfer cycle from the slave module, the bus module relinquishes the right to use the bus and fails to accept the transferred address or data. In a cycle after a predetermined number of transfer cycles The master module that has performed the transfer by controlling the order of sending the retry request that requests the execution of the transfer, when the retry report is received in a cycle after a predetermined number of times from the corresponding transfer cycle, executes the transfer. An information processing apparatus for performing cycle transfer again. 3. An information processing apparatus, comprising: a bus; a plurality of modules connected to the bus; and an error connected to the plurality of modules and provided separately from the bus for transferring an error report. The master module having a report signal line, and having acquired the right to use the bus, controls the order in which the master module executes a transfer cycle of transferring at least one of an address and data to a slave module that is a transfer destination, and further includes: The master module relinquishes the right to use the bus after the transfer cycle and before there is a transfer of an error report from the slave module to the transfer cycle, and the slave module that has received the transferred address or data, , Transfer error occurs when received address or data has transfer error The module that controls the order in which the error report to be reported is sent in a predetermined number of cycles after the cycle in which the transfer error has occurred, and that executes the transfer in the cycle before the predetermined number of cycles before the cycle in which the error report was sent, An information processing apparatus for confirming the contents of a transfer in which a transfer error has occurred from the transmitted error report. 4. An information comprising a bus, a plurality of modules connected to the bus, and an acknowledge signal line connected to the plurality of modules and provided separately from the bus for transferring an acknowledgment report. In the bus control method for a processing device, the master module that has acquired the right to use the bus controls an order in which the master module executes a transfer cycle of transferring at least one of an address and data to a slave module that is a transfer destination. The master module may relinquish the right to use the bus after the transfer cycle but before there is a transfer of an acknowledgment report for the transfer cycle from the slave module, and the slave module receiving the transferred address or data, In a cycle after a predetermined number from the corresponding transfer cycle, The slave module controls the order in which the slave module sends an acknowledgment report for reporting receipt of the address and data, and the master module that has performed the transfer receives the acknowledgment report in a predetermined number of cycles after the corresponding transfer cycle. A bus control method for confirming the success or failure of the executed transfer cycle. 5. Information comprising a bus, a plurality of modules connected to the bus, and a retry signal line connected to the plurality of modules and provided separately from the bus for transferring a retry report. In the bus control method for a processing device, the master module that has acquired the right to use the bus controls an order in which the master module executes a transfer cycle of transferring at least one of an address and data to a slave module that is a transfer destination. The master module relinquishes the right to use the bus after the transfer cycle but before there is a transfer of a retry report for the transfer cycle from the slave module, and fails to accept the transferred address or data. The slave module performs a cycle after a predetermined number from the corresponding transfer cycle. The master module that performed the transfer controls the order in which the retry request for requesting the execution of the transfer is sent in the transfer module. A bus control method characterized by re-transferring the cycle in which the operation has been executed. 6. A bus, comprising: a plurality of modules connected to the bus; and an error report signal line connected to the plurality of modules and provided separately from the bus for transferring an error report. In the bus control method for an information processing device, the master module that has acquired the right to use the bus controls the order in which the master module executes a transfer cycle of transferring at least one of an address and data to a slave module that is a transfer destination, Further, the master module relinquishes the right to use the bus after the transfer cycle but before there is a transfer of an error report for the transfer cycle from the slave module, and the slave module receiving the transferred address or data is If there is a transfer error in the received address or data, An error report for reporting the occurrence of a transmission error is controlled by controlling the order in which the error report is sent in a cycle after a predetermined cycle from the cycle in which the transfer error occurred, and the transfer is performed in the predetermined number of cycles before the cycle in which the error report was sent. A bus control method, wherein the executed module confirms the content of the transfer in which the transfer error has occurred from the transmitted error report.