JP3442550B2 - Register file - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register file mounted on a microprocessor or the like, and more particularly to a register file added with a barrel shift function.

[0002]

2. Description of the Related Art Conventionally, a microprocessor has a register file and a barrel shifter as independent arithmetic macros, as shown in FIG.

FIG. 9 is a block diagram showing the structure of a conventional microprocessor. According to this microprocessor, the instruction read from the instruction memory 101 via the instruction cache 102 is decoded by the decoder 103, and necessary data is read from the register file 104 based on the decoding result, and the bypass unit 10 is read.
Each execution unit (branch unit 10
6. The arithmetic logic unit (ALU) 107, barrel shifter 108, and load / store unit 109) execute instructions. The result is stored in the register file 104 and directly passed from the bypass unit 105 to the next execution unit as needed. The load / store unit 109 is connected to the data memory 111 via the data cache 110.

For example, when the data stored in the register r3 of the register file 104 is shifted to the right by 3 bits and used as the first data, and is added to the second data stored in the register r2, first, The address r3 of the register file 104 is accessed to read the data. This data is sent to the barrel shifter 108 and shifted to the right by 3 bits to become the first data. In the same cycle as the execution of this shift, another second data is read from the register file 104 and sent to the ALU 107.
The first data is AL by the bypass unit 105.
It is sent to U107 and added with the second data read from the register file 104.

[0005]

However, the above conventional microprocessor has the following problems.

Originally, the barrel shifter requires a large number of wirings to realize its function, and the area occupied by the transistors is very small. Further, also in the register file, the proportion of the circuit area is more occupied by the wiring than the transistor due to the tendency of increasing the number of ports. In addition to this, in the microprocessor equipped with the barrel shifter and the register file, the area required for wiring is increasing with the expansion of the bit width. Due to these factors, the efficiency of the circuit area is deteriorated, which is an obstacle to speeding up. I was getting tired.

The present invention has been made in order to solve the above-mentioned conventional problems, and the purpose thereof is to add a barrel shift function and to make a circuit area of a microprocessor or the like efficient. It is to provide the file. Another object of the present invention is to provide a register file to which a barrel shift function is added and which enables high-speed output of shift data in a microprocessor or the like.

[0008]

In order to achieve the above object, a feature of the first invention is that a word line controlled by an address decoder for transmitting a selection signal of a memory cell and a read data or a write data are transmitted. In a register file including a memory cell array in which the memory cells are arranged in a matrix at intersections with bit lines, a shift bit line for transmitting shift data, the shift bit line and the memory cell or the read bit line. And a connection control circuit that controls the connection, and controls the connection control circuit to load the data in the memory cell column specified by the address of the source register on the shift bit line, and to use the address of the destination register. From each read bit line of the specified memory cell column,
The shift data read from the source register is read.

According to the first aspect of the present invention, data can be shifted to the left and right by the difference between the address of the source register and the address of the destination register, and a register file with a barrel shift function can be realized. It will be possible.

A feature of the second invention is that in the first invention, a bit line and its control circuit are provided for the most significant bit of the memory cell array, and sign expansion is performed by these.

According to the second aspect of the present invention, sign expansion during arithmetic shift can be performed easily and accurately.

A feature of the third invention is that in the first invention, a sign extension control circuit for the most significant bit of the memory cell array is provided inside the memory cell array, and the sign extension control circuit performs the sign extension. There is something to do.

According to the third aspect of the invention, like the second aspect of the invention, the sign extension during arithmetic shift can be performed easily and appropriately.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a register file according to the first embodiment of the present invention.

The register file of this embodiment is a register file with a barrel shift function, which is obtained by adding a barrel shift function to the original register file, and is provided outside the memory cell array unit 1, the address decoder 2, and the memory cell array unit 1. The sign extension / shift bit precharge unit 3 is provided.

Here, as will be described later, the memory cell array unit 1 stores a plurality of memory cells for storing "1" or "0" data and the stored data in the memory cells as they are or in a shifted state. It has a read circuit for reading (including a sense amplifier and a precharge circuit). The address decoder 2 decodes the source (shift source) address SAD and the destination (shift destination) address DAD to read out and shift the data in the memory cell (read precharge). Signal RP, read word signal RW, source word signal SW, and destination word signal DW)
And a sine extension control circuit 2A for generating a sine extension signal Ext for controlling sine (sign) extension at the time of arithmetic shift. Of course, in addition to this, a writing system circuit is also provided, but since it is not directly related to the present invention, the description and illustration are omitted here.

Further, a discriminating circuit (not shown) for discriminating between the source / destination of the input addresses SAD and DAD is provided in the address decoder 2, or there is control corresponding to the outside, and there is a sign. The extension control circuit 2A determines a bit that requires sign extension when decoding the input addresses SAD and DAD by using a method such as comparing the size of the source and destination addresses, and when performing the sign extension, for example, "1" is set. The sign extension signal Ext of "" is output to the sign extension / shift bit precharge unit 3. The sign extension control circuit 2A also outputs a shift precharge signal SP for activating the shift bit line in the memory cell array section 1 to the sign extension / shift bit precharge section 3.

The sign extension / shift bit precharge unit 3 receives the sign extension signal Ext and the shift precharge signal SP from the sign extension control circuit 2A and the MSB data received from the memory cell array unit 1 when performing the sign extension. (Sign bit to be extended (MS
Based on (B) data), the Sign data is output to the shift bit line of the memory cell array unit 1.

FIG. 2 is a circuit diagram showing a specific structure of the sign extension / shift bit precharge unit 3 in FIG.
In this sign extension / shift bit precharge unit 3,
For each bit, a shift channel precharge P-channel transistor 3a and N-channel transistors 3b, 3
c and c are provided respectively. That is, the P-channel transistor 3a is turned on by the shift precharge signal SP to precharge the shift bit line 13 with the power supply voltage VDD. N-channel transistors 3b and 3c
Are connected in series between the drain of the P-channel transistor 3a connected to the shift bit line 13 and the ground.

When performing the sign extension, the sign extension signal Ext of "1" is sent from the sign extension control circuit 2A, whereby the N-channel transistor 3b is turned on and the most significant bit data (MSB data) is output. If it is "1", the N-channel transistor 3c is turned on. As a result, the precharge charge of the shift bit line 13 corresponding to the bit to be sign-extended is pulled to "0" and "1" is output to perform sign-extension.

FIG. 3 is a block diagram showing an internal configuration (a part) of the memory cell array section 1 in FIG. The memory cell array unit 1 includes a plurality of sets each including a destination word line, a read word line, and a source word line that propagate the destination word signal DW, the read word signal RW, and the source word signal SW for each row. Group word lines 11, a plurality of (bit direction) read bit lines 12 for propagating read data, and a plurality of (bit direction) write bit lines (not shown) for propagating write data in a matrix. It is arranged. The read bit line 12 is precharged by the P-channel transistor 1a which is turned on by the read precharge signal RP.

Further, a plurality of shift bit lines 13 used at the time of arithmetic shift are diagonally arranged so as to intersect the set word line 11 and the read bit line 12 (in FIG. 2, for right shift). Only shift bit lines are shown).

A memory cell 14 and a connection control circuit 15 are respectively arranged at intersections of the set word line 11 of each row and the read bit line 12 and the write bit line of each column. The cells 14 are connected to the read bit lines 12 via the connection control circuit 15, respectively. Here, the connection control circuit 15 directly outputs the data of the memory cell 14 to the read bit line 12 when the read word signal RW is activated, and shifts the data of the memory cell 14 when the source word signal SW is activated. Output to the bit line 13, and when the destination word signal DW is activated, shift bit line 1
3 has a function of taking in the data on 3 and outputting it to the read bit 12 line.

The memory cell column of each row as described above constitutes a register for each row. A sense amplifier 16 is connected to the end side of each read bit line 12. The sense amplifier 16 inverts and amplifies the signal on the read bit line 12 and takes it out of the memory cell array unit 1.

Next, the basic operation of the above-mentioned register file with barrel shift function will be described. Note that right shift and left shift have the same basic operation, and they can be easily performed by reversing the magnitude relationship of the addresses or by providing shift bit lines for left and right shifts respectively. Only the operation, that is, the operation when the instruction for right shifting the data of the register [m + 3] by 3 bits is executed will be described with reference to FIG.

When the source register is designated as [m + 3] and the destination register is designated as [m] (see FIG. 4), when the address decoder decodes the address, the address is the source or the destination. Whether or not there is is determined by the determination circuit, and the source word line [m + 3] and the destination word line [m] are activated. The dashed arrow in FIG. 3 indicates the flow of data at this time.

As described above, the data read from the register [m + 3] is shifted to the shift bit line 1 by the connection control circuit 15 controlled by the source word line [m + 3].
3 is transferred to the read bit line 12 and read by the connection control circuit 15 controlled by the destination word line [m]. As a result, the read data is right-shifted by 3 bits. In this case, since there is no shift data for the upper 3 bits, the shift bit line is set so that the output from the shift bit line 13 has a value used by default. Here, by default, the value precharged by the shift precharge signal SP, that is, "1" is inverted by the sense amplifier 16 to output "0".

FIG. 4 is a diagram showing movement of all bits when arithmetic shift, that is, sine extension is performed. It is assumed that the register file shown in the figure has two read ports, and the read bit lines in each column are composed of first and second read bit lines 12a and 12b, respectively.

The data of the register [m + 1] read from the memory cell 14 passes through the shift bit line 13,
The data is read from the second read bit line 12b. The MSB data read from the most significant bit is the N-channel transistor 3 shown in FIG.
When c is turned on, the Sign data is output to the shift bit line 13 and read from the second read bit line 12b. SEB in the figure represents a sign-extended bit, and SB
FB represents the shifted bits.

As described above, in this embodiment, since the barrel shifter function is added to the register file, it is not necessary to separately provide the barrel shifter, and the area efficiency of the microprocessor is improved. Furthermore, by shifting simultaneously with the reading of the register, the contents of the register r1 are shifted by 3 bits and stored in the register r2, for example, in the instruction format of Shift r1 r2 3 Add r2 r3 r3. In the case of an instruction to add the contents and store it in the register r3, two cycles were required. For example, if an instruction ShiftAdd for simultaneously performing shift and addition is prepared and the register file with the barrel shifter function according to the present invention is used, ShiftAdd r1 r3 r4 ( ^* 1) ^* 1: At this time, the difference between the r4 and r1 addresses is 3, which can be performed in one cycle. As a result, shift data can be obtained at high speed, and the performance of the entire microprocessor is improved.

FIG. 5 is a block diagram showing a main configuration of the memory cell array unit 1 in the register file according to the second embodiment of the present invention. Elements common to those in FIG. 3 are designated by the same reference numerals. There is.

The second embodiment shows an example in which the sign extension function is provided in the most significant bit in the memory cell array 1.

As shown in FIG. 5, a first selector 31 and a second selector 32 are provided near the most significant bit memory cell 14 in the memory cell array portion 1 of this embodiment. The first selector 31 outputs the data on the shift bit line 13 when the destination word signal DW is active, and outputs the data in the memory cell 14 to the read bit line 12 via the transistor 33 when it is inactive. Further, the second selector 32 transfers the data on the read bit line 12 when the sign extension signal Ext is activated,
When it is inactive, the data in the memory cell 14 is output to the shift bit line 13 via the transistor 34.
The transistors 33 and 34 are on / off controlled by the read word signal RW and the source word signal SW, respectively.

In this embodiment, when the sign extension is performed, the selector 32 is operated by the sign extension signal Ext.
Is controlled to connect the read bit line 12 to the shift bit line 13 and transfer the data of the most significant bit (that is, the sign bit) to the shift bit line 13. On the other hand, when the sign extension is not performed, the shift bit line 13 holds the precharge potential and is extended by 0 by the potential.

FIG. 6 is a diagram showing a configuration other than the most significant bit in the memory cell array section 1 according to this embodiment. However, corresponding to the description in FIG. 4 described above, description will be made assuming a register file having two read ports.

The memory cells 14 other than the most significant bit provided in the memory cell array portion 1 of the present embodiment (for example, [m
+3, n + 3]) near the first selector 51 and the second selector 51.
And a selector 52. First selector 51
Is the first destination word signal DW1 [m +
3] is activated, the data on the shift bit line 13 is activated, and when it is inactivated, the data in the memory cell 14 is transferred via the transistor 53 to the first read bit line 12a [n + 3].
Output to. Further, the second selector 52 secondly reads the data on the shift bit line 13 when the second destination word signal DW2 [m + 3] is active and the data in the memory cell 14 through the transistor 54 when it is inactive. The data is output to the bit line 12b [n + 3]. The transistors 53 and 54 have the first and second transistors, respectively.
It is turned on when the read word signals RW1 and RW2 [m + 3] are active. Transistors 55 and 56 are connected to the output side of the memory cell 14 [m + 3, n + 3], and these transistors 55 and 56 turn on when the first and second source word signals SW1 and SW2 [m + 3] are active. , The data in the memory cell 14 [m + 3, n + 3] is output to the shift bit line 13. In addition, the memory cell 1 shown in FIG.
4 including [m, n] and corresponding to the other memory cells 14 has the same configuration as described above.

In this embodiment, the data in the source register [m + 3] is set to the right by 3 as in the case of the basic operation described above.
Consider bit-shifting. Source register [m +
3] is read by the first read bit line 12a, and the second read bit line 1 of the destination register [m] is read.
When reading with 2b, first, source address [m + 3]
When the first read word signal RW1 and the first source word SW1 are activated by the decoding of the
And 55 are turned on.

At this time, the destination word DW
1 is not activated, the memory cell 14 [m + 3, n
The data in +3] is the first read bit line 12a [n +
3] and the shift bit line 13. The data of the shift bit line 13 is output to the read bit line 12b [n] by the selector 52 controlled by the second destination word signal DW2 [m], which causes the data of the source register [m + 3] to be 3 bits right. The output shifted to is obtained.

As described above, even if the sign extension function is provided inside the memory cell array portion 1, the same effect as that of the first embodiment can be obtained.

FIG. 7 is a block diagram showing a main configuration of a memory cell array section of a register file according to the third embodiment of the present invention. Elements common to FIG. 3 are designated by the same reference numerals.

The third embodiment shows another example in which the sign extension function is provided in the most significant bit in the memory cell array section 1, and the configuration other than the most significant bit is shown in FIG.
It is the same as that shown in.

As shown in FIG. 7, a first selector 61 and a second selector 62 are provided near the most significant bit memory cell 14 in the memory cell array portion 1 of this embodiment. The first selector 61 outputs the data on the shift bit line 13 when the destination word signal DW is active, and outputs the data in the memory cell 14 to the read bit line 12 via the transistor 63 when it is inactive. Further, the second selector 62 is controlled by the source sign select signal SS. The source sign select signal SS is a signal that indicates whether to access the source register or perform sign extension.
It is generated by the address decoder 2 when the input addresses SAD and DAD are decoded. Then, the transistor 63 is on / off controlled by the read word signal RW.

In this embodiment, when sign extension is performed, the read bit line 12 is connected to the shift bit line 13 by the second selector 62 and the most significant bit data is transferred to the shift bit line 13. On the other hand, when the sign extension is not performed, the selector 62 or 61 causes the shift bit line 13 to be driven only by the precharge circuit (transistor 3a in FIG. 3) to perform 0 extension.

As described above, even if the sign extension function is provided in the memory cell array portion 1, the same effect as that of the first embodiment can be obtained.

In the above description of the first to third embodiments, only the case of right shift is explained, but it is assumed that the structure actually includes left shift.

FIG. 8 is a block diagram showing the configuration of a microprocessor to which the register file with barrel shift function of the present invention is applied. Elements common to FIG. 9 are designated by the same reference numerals.

Explaining the case of performing the operation of "shifting one data and adding it to another data" shown in FIG. 9 described above, first, the above-mentioned instruction "ShiftAdd" is prepared. The instruction read from the instruction memory 101 is decoded by the decoder 103, and depending on the result, the necessary data is accessed to access the register file 71 with the barrel shift function. The first data and the second data to be added are read in the same cycle and can be added in the next cycle. Further, in this example, a multiplier and a divider 72 are added to the space of the conventional barrel shifter which is vacant by using the register file with the barrel shift function of the present invention.

[0048]

As described in detail above, according to the first invention, a shift bit line for transmitting shift data,
A connection control circuit for controlling the connection between the shift bit line and the memory cell or the read bit line is provided, and the connection control circuit is controlled to shift the data in the memory cell column designated by the address of the source register to each shift bit. Since the shift data read from the source register is read out from each read bit line of the memory cell column specified by the address of the destination register by placing it on the line, the address of the source register and the destination register can be changed. The data can be shifted left and right by the difference and output at high speed, and a register file with a barrel shift function can be realized. As a result, by installing the register file of the present invention in a microprocessor or the like, it is not necessary to separately provide a barrel shifter, so that the circuit area of the microprocessor can be made efficient and its performance can be improved. Becomes

According to a second aspect of the present invention, in the first aspect, a bit line and its control circuit are provided for the most significant bit and the least significant bit of the memory cell array, and sign expansion is performed by these. Therefore, in addition to the effect of the first aspect of the present invention, it becomes possible to easily and accurately perform the sign extension during the arithmetic shift.

According to a third invention, in the first invention, a sign extension control circuit for the most significant bit and the least significant bit of the memory cell array is provided inside the memory cell array, and the sign extension control circuit is provided. Since the sign extension is performed by the above, in addition to the effect of the first invention, it is possible to easily and accurately perform the sign extension during the arithmetic shift, as in the second invention.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a register file according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a sign extension / shift bit precharge unit 3 in FIG.

FIG. 3 is a block diagram showing an internal configuration (a part) of a memory cell array unit 1 in FIG.

FIG. 4 is a diagram showing movements of all bits when sign extension is performed.

FIG. 5 is a block diagram showing a main configuration of a memory cell array section 1 in a register file according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a configuration other than the most significant bit in the memory cell array unit 1 according to the second embodiment.

FIG. 7 is a block diagram showing a main configuration of a memory cell array unit of a register file according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing functions of a microprocessor to which the register file of the present invention is applied.

FIG. 9 is a block diagram showing a configuration of a conventional microprocessor.

[Explanation of symbols]

1 Memory cell array section 2 address decoder 2A sign extension control circuit 3 sign extension / shift bit precharge section 12 read bit line 13 shift bit lines 14 memory cells 15 Connection control circuit 16 sense amplifier 31, 32, 61, 62 selector SP shift precharge signal DW destination word signal RW Read word signal SW source word signal RP Read precharge signal SAD, DAD input address

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 11/40-11/419 G16F 7/00 G06F 5/01

Claims (3)

(57) [Claims] 1. A memory cell array in which the memory cells are arranged in a matrix at intersections of word lines which are controlled by an address decoder and which transmit a selection signal of memory cells and bit lines which transmit read data or write data. In the provided register file, a shift bit line for transmitting shift data, a connection control circuit for controlling connection between the shift bit line and the memory cell or the read bit line are provided, and the connection control circuit is controlled, The data in the memory cell string specified by the address of the source register is placed on the shift bit lines, and read from the source register from each read bit line of the memory cell string specified by the address of the destination register. Register that reads out the shifted shift data File. 2. The register file according to claim 1, wherein a bit line and a control circuit for the bit line are provided for the most significant bit of the memory cell array, and sign extension is performed by these. 3. The register file according to claim 1, wherein a sign extension control circuit for the uppermost bit of the memory cell array is provided inside the memory cell array, and the sign extension is performed by the sign extension control circuit.