JPH04298884A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable high speed operation and to reduce area by arranging plural memories while alternatively interleaving them for each corresponding bit and directly connecting all address to a corresponding bit string. CONSTITUTION:A bar bit line 11, bit lines 12 and 21, bar bit line 22 and a node 36 are precharged by a precharge 15 and an MOS transistor Tr 33 of all the adders. MOSTr 31 and 32 are turned off. Then the word line for a selected line is activated, and the data of any of memory cells 13 and 23 are read out to the respective lines 11 and 12 and the lines 21 and 22. Accordingly, the node 36 is kept at a precharged level H. Then a proper gate signal is set to '1'. When '1' is stored in the cells 13 and 23, the lines 12 and 21 maintains the precharged level H. Thus, since the Tr 31 is turned on, the Tr 32 is turned off, the node 36 is changed into a L level and the proper gate signal is converted into '0'.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit that performs arithmetic operations in digital signal processing and the like at high speed.

0002

2. Description of the Related Art An example of a conventional semiconductor integrated circuit is shown in FIG. 3 and will be described. In FIG. 3, 31 and 32 are memory devices, and 33 is an arithmetic operation circuit that performs addition and the like. Then, the data to be operated on is read out from the memory devices 31 and 32 and inputted to the arithmetic operation circuit 33. etc. are output as the calculation output.

0003

[Problems to be Solved by the Invention] In the conventional semiconductor integrated circuit as described above, data bus lines and the like are required to input data from the memory devices 31 and 32 to the arithmetic operation circuit 33, resulting in a large area. There was an issue. Another problem is that it is difficult to increase the speed due to the parasitic capacitance of the data bus line.

The present invention has been made to solve the above problems, and its object is to provide a semiconductor integrated circuit that performs high-speed arithmetic processing and has a small area.

[0005]

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention includes a plurality of memories having an m-bit x n-bit (m, n: arbitrary natural number) configuration and performs operations between output data of the plurality of memories. an arithmetic circuit that configures the plurality of memories as one memory cell array, and arranges memory cell columns of corresponding bits in an alternately interleaved manner, and connects a bit line of each memory cell column to the arithmetic circuit. It is directly connected.

[0006]

[Operation] In the present invention, two M
By turning off both OS FETs, the propagation signal generation operation is performed stably and at high speed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit according to the present invention. In FIG. 1, 1 is a memory cell column [Ak, Bk (k=0 to n)], and this memory cell column 1 has a plurality of memories configured with m bits x n bits (m, n: arbitrary natural numbers). It is accommodated. 2 is a write circuit for this memory cell column 1 [WAk, WBk (k=0
-n)], 3 is a full adder (F), and this full adder 3 constitutes an arithmetic circuit that executes arithmetic operations between the output data of the plurality of memories. The plurality of memories are constituted by one memory cell array, memory cell columns of corresponding bits are arranged in an alternately interleaved manner, and the bit line of each memory cell column is directly connected to the arithmetic circuit. ing. 4 indicates a memory A decoder, and 5 indicates a memory B decoder.

Next, the operation of the embodiment shown in FIG. 1 will be explained. First, Ak, Bk (k=
0 to n) are memory cell columns. Two pieces of data (n bits/word) required for the operation are stored in interleaved memory areas A and B, respectively. That is, one data is in the memory cell row A0 to An, and the other data is in the memory cell row B0 to Bn.
, B0 stores the least significant digit (bit) [LSB], and the memory cell columns An, Bn store the most significant digit (bit) [M
SB] is stored. Next, WAk and WBk (k=0 to n) in the write circuit 2 are each memory cell column A
This is a circuit for writing to k and Bk. In addition, each memory cell belonging to the memory cell row Ak (k=0 to n) is a memory A
It is connected to a word line that conveys a selection signal from decoder 4. On the other hand, memory cells belonging to memory cell column Bk (k=0 to n) are each connected to a word line that transmits a selection signal from memory B decoder 5. And memory cell column Ak
and Bk are both input to full adder Fk.

Next, in order to more specifically explain the configuration shown in FIG. 1, the configuration shown in FIG. 1 will be explained using FIG. 2, which is a more detailed explanatory diagram of FIG. FIG. 2 shows the circuit configurations of WAk and WBk of the k-th bit write circuit 2, Ak and Bk of the memory cell column 1, and Fk of the full adder 3, and their connection states. In the memory cell column Ak, 11
is a bar bit line, 13-1...13-n are memory cells, 14 is a sense amplifier, 15a and 15b are precharge transistors for the bar bit line 11 and bit line 12, and memory cells 13-1 to 13- n is connected to a word line output from memory A decoder 4 shown in FIG. In addition, in the memory cell column Bk, 21 is a bit line;
22 is a bar bit line, 23-1...23-n are memory cells, 24 is a sense amplifier, 25a and 25b are precharge transistors for the bit line 21 and bar bit line 22, and memory cells 23-1 to 23 -n is connected to the word line output from memory B decoder 5 shown in FIG.

In the write circuit WAk, 16, 17
is a tri-state driver and is controlled by a write enable signal WE. The tri-state driver 16 is connected to the bar bit line 11, and the tri-state driver 17 is connected to the bit line 12. Further, in the write circuit WBk, 26 and 27 are tri-state drivers, and the write enable signal WE
controlled by This tri-state driver 26 connects the tri-state driver 27 to the bit line 21.
are connected to the bar bit line 22, respectively.

In the full adder Fk, 31 and 32 are N-channel type MOS transistors, each having a source electrode (or drain electrode) connected to the bar bit line 11 and a bit line 12, respectively, and each drain electrode (or The source electrodes) are short-circuited to form a node 36, which is connected to the drain of the P-channel MOS transistor 33. The gate electrode of the N-channel MOS transistor 31 is connected to the bit line 21, and the gate electrode of the N-channel MOS transistor 32 is connected to the bar bit line 22.

The drain electrodes of N-channel type MOS transistors 31 and 32 and the carry input Ck-1 are connected to the input of the EX-OR gate 34.
R gate 34 outputs sum Sk. Further, the bit line 12 and the carry input Ck-1 are connected to the input of the selector 35, and the control terminal of the selector 35 is connected to the node 3.
6 are connected, and the selector 35 outputs a carry output Ck. This carry output Ck becomes the carry input of the (k+1)th bit full adder Fk+1. In addition, N-channel type MOS transistors 31 and 32 and P-channel type MO
The S transistor 33 forms a propagation signal generation circuit of the full adder, and a propagation signal is outputted to a node 36.

Next, the operation of the present invention will be explained. First, data is written to the memory cells 13-1 to 13-n (MCA) and 23-1 to 23-n (MCB). When data DAk and DBk are respectively input to the write circuits WAk and WBk and the write enable signal WE is in the active state, the tri-state drivers 16, 17 and 26, 27 control the corresponding bar bit line 11 and bit line 12, respectively. and drives the bit line 21 and bar bit line 22. At this time, the word line of the row selected by the memory A decoder 4 and the memory B decoder 5 is activated, and the memory cells 13-1 to 13-n (MCA) and 23-1 connected to the word line are activated. ~23-
Data is written to n (MCB).

Next, read and add operations will be explained. First, the bar bit line 11, the bit line 12,
The bit line 21, the bar bit line 22 and the node 36 are connected to the precharge 15 and the P channel type MOS transistor 33.
is precharged to "H". Further, N-channel type MOS transistors 31 and 32 are turned off. Then, the word line of the selected row is activated by the memory A decoder 4 and the memory B decoder 5, and the data of any memory cell 13 in the memory cell column Ak is transferred to any one of the memory cells 13 in the memory cell column Bk. The data of the memory cell 23 is read out to the corresponding bar bit line 11, bit line 12 and bit line 21, bar bit line 22, respectively. For example, if "1" is stored in the memory cell 13 and "0" is stored in the memory cell 23, the bar bit line 11 and the bit line 21 shift to the "L" level. The bit line 12 and the bar bit line 22 maintain the precharged "H" level. As a result, N-channel MOS transistors 31 and 32 remain off, and therefore node 36 maintains the precharge level "H". Therefore, in this case, the propagation signal becomes "1". Also, "1" is stored in the memory cell 13, and "1" is stored in the memory cell 23.
is stored, bar bit lines 11 and 22 shift to "L" level, and bit lines 12, 21 maintain the precharged "H" level.

As a result, the N-channel type MOS transistor 31 is turned on, and the N-channel type MOS transistor 31 is turned on.
Since transistor 32 remains off, node 36
is discharged to “L” level, and the propagation signal becomes “0”.
becomes.

By the above-described operation, adjacent memory cell columns can be directly coupled to generate a propagation signal. Here, the difference from the propagate generation circuit of conventional configuration is the presence of a P-channel type MOS transistor 33. This is important in an adder circuit that receives the bit line of a memory array as an input, as in the present invention. In other words, by turning off both the N-channel MOS transistors 31 and 32 in the precharge state before the start of the write/read operation, the propagation signal generation operation can be performed stably and at high speed. . Carry generation and sum generation using the propagation signal are performed by using the selector 35 and EX-OR, respectively.
This is implemented by gate 34, which is generally well known as it is the principle of a normal Manchester full adder, and will not be discussed here. In the manner described above, the addition of the two data read from memory column A and memory column B is completed.

Note that in the above embodiment, the sum of the full adder,
Although the EX-OR gate circuit 34 and the selector 35 are used as the carry generation circuit, any structure may be used as long as it has the same function. Further, the memory cell may be a static type, either a full CMOS type or a resistive load type, or a dynamic type. Alternatively, a normal data reading circuit may be added and a switch may be used to selectively use the addition mode and the normal mode. Further, in the above embodiment, a RAM was also described, but a ROM may also be used if a differential type configuration is adopted. Alternatively, a multi-port RAM may be used. In addition, although PMOS was used as the precharge transistor, NMOS
may be used, in which case the input to the gate electrode of the NMOS becomes the PC signal.

Further, in the above embodiment, an operation using two memories has been described, but the present invention is not limited to this. Similarly, when there are n memories (n≧2), the corresponding bits are It is also possible to interleave and arrange each. In that case, a plurality of adders may be arranged. Furthermore, the arithmetic circuit is not limited to an addition circuit, but may be a subtraction circuit, or may have all functions as an arithmetic operation circuit (ALU). Furthermore, in this embodiment, the memory cell column of the least significant digit (bit) [LSB] is placed closest to the decoder circuit, and the most significant digit (bit) [MSB]
] Since the memory cell row is placed furthest away, when carry propagation goes from LSB to MSB, such as in an addition operation, the word line delay is canceled out by the carry propagation delay, realizing a high-speed circuit. When carry propagation goes from the MSB to the LSB, such as in a magnitude comparison operation, the decoder circuit may be placed close to the MSB memory cell column.

[0019]

As explained above, in the semiconductor integrated circuit of the present invention, the memory A and the memory B are arranged in an alternately interleaved manner for each corresponding bit.
Full adders are configured to connect directly to columns, so the memory readout circuit and full adder propagation signal generation circuit can be merged, and unnecessary bus wiring can be removed, allowing high-speed calculations. In addition, there is an effect that a reduction in surface area can be achieved. Moreover, the insertion of the precharge transistor 33 has the effect that operations can be performed stably and at high speed.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a more detailed explanatory diagram of FIG. 1;

FIG. 3 is a configuration diagram showing an example of a conventional semiconductor integrated circuit that does not use the present invention.

[Explanation of symbols]

1 Memory cell column (Ak, Bk) 2 Write circuit (WAk, WBk) 3 Full adder (Fk) 4 Memory A decoder 5 Memory B decoder

Claims (1)

[Claims] 1. A computer comprising: a plurality of memories having a configuration of m bits by n bits (m, n: any natural number); and an arithmetic circuit that executes an operation between output data of the plurality of memories; 1. A semiconductor integrated circuit comprising one memory cell array, memory cell columns of corresponding bits are arranged in an alternately interleaved manner, and a bit line of each memory cell column is directly connected to the arithmetic circuit.