JP3439161B2 - Nitride light emitting device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor laser device using a semiconductor layer of a nitride compound system, a nitride-based light emitting devices such as light emitting diodes.

[0002]

2. Description of the Related Art GaN, GaInN, AlGaN, Al
A semiconductor element using a nitride-based semiconductor such as GaInN is
For example, application as a light emitting element that emits light in the visible to ultraviolet region is expected.

Among these applications, active development is being carried out for practical use of a semiconductor laser device using a double hetero structure having GaInN as an active layer and AlGaInN as a cladding layer. Such a semiconductor laser device is
It is formed by growing the above-mentioned active layer and cladding on a substrate made of a material such as sapphire or silicon carbide by using a metal organic chemical vapor deposition (MOVPE) method or a molecular beam epitaxial growth (MBE) method.

Conventionally, in this type of semiconductor laser device, after a buffer layer made of AlN is grown on a sapphire substrate, an n-type contact layer made of n-type GaN and an n-type A layer are formed.
nGaInN n-type cladding layer, A as active layer
A light emitting layer made of 1GaInN, a p-type clad layer made of p-type AlGaInN, and a cap layer made of p-type GaN are sequentially grown. Furthermore, a current confinement layer made of undoped GaN and a p-type contact layer made of p-type GaN formed so as to fill the current passage on the cap layer and the current confinement layer are formed thereon. Further, a p-type electrode joined to the p-type contact layer and an n-type electrode joined to the n-type contact layer are formed.

In such a conventional method for manufacturing a semiconductor laser device, first, each layer from a buffer layer to a cap layer is sequentially formed on a sapphire substrate by, for example, the MOVPE method, and then an undoped GaN layer to be a current confinement layer is formed. To form. After that, a portion of the GaN layer corresponding to the current passage is removed by etching to form a current confinement layer, and further a p-type contact layer is formed on the cap layer and the current confinement layer so as to fill the current passage. Also,
The portion forming the n-electrode is removed by etching until the n-type contact layer is exposed. Then, finally, a p-type electrode joined to the p-type contact layer and an n-type electrode joined to the n-type contact layer are formed. A conventional semiconductor laser device is manufactured by the above steps.

However, in the conventional semiconductor laser device as described above, undoped Ga serving as the current confinement layer is formed.
A dry etching process is required to remove the portion of the N layer corresponding to the current path by etching. For this reason, after this dry etching step, contaminants such as fluorine adhere to the etching surface, that is, the portion that becomes the current path, and the adhered contaminants also after the regrowth step of forming the p-type contact layer thereafter. , Remains in the portion that will be the current path.

In the above conventional semiconductor laser device,
A dry etching step is required in order to remove the portion forming the n-type electrode by etching until the n-type contact layer is exposed. Therefore, after this dry etching step, contaminants adhere to the etching surface, that is, the portion of the n-type contact layer where the n-type electrode is formed, and the adhered contaminants are used to form the n-type electrode thereafter. Even after the growth, it remains at the interface between the n-type contact layer and the n-type electrode as it is.

In other conventional semiconductor laser devices,
In the process of forming the current constriction structure, SiNx, Si
Wet etching is required when removing the O ₂ film. When SiNx, SiO ₂ or the like is used as the insulating film, an etchant containing hydrofluoric acid is often used. Therefore, contaminants such as fluorine adhere to the surface of the nitride semiconductor after the step of forming the current confinement structure, and the contaminants remain at the regrowth interface even after the subsequent regrowth step.

In the case of a nitride semiconductor device, the lattice mismatch is large, the interface state density is originally relatively high, and
When the concentration of fluorine at the regrowth interface and the nitride semiconductor / electrode interface is high, the interface state density at these interfaces is further increased. Therefore, in the case of a light emitting device, a part of the injection current is captured by the interface state, the current component contributing to light emission is reduced, the operating current and the threshold current density are increased, and the reliability of the device life is reduced. There is a problem. Especially about 20m used for recording / reproducing / recording type optical disk drive
The above-mentioned problems are remarkable in the nitride-based semiconductor laser for applications requiring a high output of W or more.

[0010]

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and has a highly reliable nitride-based luminescent element in which the interface state which causes deterioration of performance is reduced.
The purpose is to provide children .

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

Means for Solving the Problems The nitride-based light emitting device of the present invention includes a first nitride semiconductor layer, is formed on the first nitride semiconductor layer, a first nitride semiconductor layer A nitride-based light emitting device having a second nitride semiconductor layer having a junction interface and a current confinement layer that limits a width of a current path of a current flowing through the junction interface to the light emitting layer. It is characterized in that the concentration is 2 × 10 ¹¹ cm ⁻² or less.

In such a nitride-based light emitting device, a current component that does not contribute to light emission at the junction interface which is a current path between the first nitride-based semiconductor layer and the second nitride-based semiconductor device is reduced, The operating current and the threshold current density are low.

In the above nitride-based light emitting device,
When the first nitride-based semiconductor layer has a ridge portion protruding in a region to be joined to the second nitride-based semiconductor layer and the current confinement layer is formed in a shape that sandwiches the ridge portion from the left and right, the operating current It becomes a good ridge waveguide type semiconductor laser device with reduced threshold current density.

The first nitride semiconductor layer is a first conductivity type semiconductor or a non-doped semiconductor, the current confinement layer is a second conductivity type semiconductor or a high resistance semiconductor, and the second nitride semiconductor layer is The first conductivity type semiconductor may be used.

Further, the current confinement layer may be an insulator such as SiO _x N _y .

Further, the step density of the junction interface between the first nitride semiconductor layer and the second nitride semiconductor layer is 5 × 10 5.
^When it is ⁵ cm ^-1 or less, the step of removing fluorine may or may not be included in the production.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a semiconductor laser device (hereinafter referred to as an LD chip) of a first embodiment which is the first embodiment of the present invention.
FIG.

This LD chip has a main surface that is inclined by 0.3 ° in the <11-20> direction from the (0001) surface of the sapphire substrate 1, and on this main surface AlGaN having a layer thickness of about 15 nm. A buffer layer 2 made of is formed. On the buffer layer 2, an undoped GaN layer 3 having a layer thickness of about 0.5 μm and an n-type GaN layer having a layer thickness of about 4 μm.
N-type contact layer 4 made of n-type GaInN, a crack prevention layer 5 made of n-type GaInN having a layer thickness of about 0.1 μm, and a layer thickness of 0.
An n-type second clad layer 6 made of n-type AlGaN having a thickness of about 45 μm, an n-type first clad layer 7 made of n-type GaN having a layer thickness of about 50 nm, and a GaInN multiple quantum well (MQ
The light emitting layer 8 made of W) is sequentially formed. This M
The QW structure light emitting layer 8 is configured by alternately stacking a barrier layer made of undoped GaN having a layer thickness of about 4 nm and a well layer made of undoped GaInN having a compression thickness of about 4 nm. For example, there are five GaN barrier layers and four GaInN well layers.

On the light emitting layer 8, a p-type first clad layer 9 made of p-type GaN having a layer thickness of about 40 nm and a layer thickness of 0.45.
A p-type second cladding layer 10 made of p-type AlGaN having a thickness of about μm and a p-type contact layer 12 made of p-type GaN having a layer thickness of 3 to 5 μm are formed in this order. The p-type first clad layer 9 and the p-type contact layer 12 are connected to each other via the p-type second clad layer 10 which becomes a stripe-shaped current path having a trapezoidal cross section with a width of about 2 μm.
Between the cladding layer 9 and the p-type contact layer 12, a current confinement layer 14 made of n-type GaN having a film thickness of about 0.2 μm is formed except for the upper surface of the p-type second cladding layer 10.

The layers from the middle of the n-type contact layer 4 to the p-type contact layer 12 have a width of about 10 by mesa etching.
A mesa-shaped portion of μm is formed. A p-type electrode 15 is formed on the p-type contact layer 12, and an n-type electrode 16 is formed on the surface of the n-type contact layer 4 exposed by mesa etching. An insulating film 17 made of Si ₃ N ₄ or the like is formed on both side surfaces of the mesa-shaped portion and a part of the exposed surface of the n-type contact layer 4.

Each layer made of the nitride semiconductor of the LD chip shown in FIG. 1 is formed by sapphire substrate 1 by MOVPE method.
Formed on. Examples of the source gas at this time include trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn),
NH ₃ , SiH ₄ , and cyclopentadienyl magnesium (Cp ₂ Mg) are used.

Next, a method of manufacturing the LD chip of the first embodiment will be described.

2 to 8 are vertical cross-sectional views for each step showing the method of manufacturing the LD chip of the first embodiment.

First, as shown in FIG. 2, the substrate temperature is set to 60.
The buffer layer 2 made of AlGaN is formed on the sapphire substrate 1 at a temperature of 0 ° C. to a thickness of about 15 nm. Next, the substrate temperature was kept at 1150 ° C. and the layer thickness of 0.
An undoped GaN layer 3 having a thickness of about 5 μm and an n-type contact layer 4 made of Si-doped GaN having a thickness of about 4 μm are sequentially formed. Furthermore, keep the substrate temperature at 880 ° C,
A crack prevention layer 5 made of Si-doped n-type Ga _0.95 In _0.05 N and having a thickness of about 0.1 μm is formed on the n-type contact layer 4. Next, the substrate temperature was kept at 1150 ° C., and the n-type second cladding layer 6 made of Si-doped Al _0.15 Ga _0.85 N having a layer thickness of about 0.45 μm was formed on the crack prevention layer 5.
And n made of Si-doped GaN with a layer thickness of about 50 nm
The mold first clad layer 7 is sequentially formed. Furthermore, the substrate temperature was kept at 880 ° C., and a barrier layer made of undoped GaN having a layer thickness of about 4 nm and a well layer made of undoped Ga _0.85 In _0.15 N having a layer thickness of about 4 nm were formed on the n-type first cladding layer 7. Are alternately laminated to form a light emitting layer 8 made of GaInN MQW. Finally, the substrate temperature is maintained at 1150 ° C., the p-type first clad layer 9 made of Mg-doped GaN having a layer thickness of about 40 nm is formed on the light emitting layer 8, and the substrate temperature will be described later. Thus, the p-type second cladding layer 10 made of Mg-doped AlGaN having a layer thickness of about 0.45 μm is formed. Each of the layers from the buffer layer 2 to the p-type second cladding layer 10 described above has a normal pressure M.
It is formed by the OVPE method.

Then, a stripe-shaped mask 11 made of SiO ₂ is provided at a predetermined position on the upper surface of the p-type second cladding layer 10.
To form. This mask 11 is used for the p-type second cladding layer 1
On the entire upper surface of 0, a Si oxide such as SiO _{2 having} a film thickness of about 0.2 μm is formed by, for example, ECR plasma CVD method, and then a stripe having a width of about 2 μm is formed by photolithography and wet etching with buffered hydrofluoric acid. Shaped Si oxide is left, and S in other parts
It is formed by removing the i-oxide and exposing the p-type second cladding layer 10.

Then, using, for example, CF ₄ as an etching gas, a reactive ion etching method (R
By removing the p-type second clad layer other than below the mask 11 until the p-type first clad layer 9 is exposed by the IE method), the p-type second clad layer 10 is trapezoidal as shown in FIG. To process.

Next, as shown in FIG. 4, for example, 76To
The current confinement layer 14 made of Si-doped GaN and having a layer thickness of about 0.2 μm is formed by the rr low-pressure MOVPE method.
The formation of the current confinement layer 14 is performed by appropriately adjusting the growth conditions so that n-type GaN selectively grows on the exposed portion of the nitride semiconductor. For example, the substrate temperature is about 100 ℃
It is sufficient to increase the flow rate of NH ₃ to about 3 times.

After that, a Si is added by a hydrofluoric acid type etchant.
Remove O ₂ .

After this step, a step of removing fluorine remaining on the surface after the wet etching step is performed. Annealing was performed for 3 hours at 800 ° C. in an atmosphere of a group 0 element gas such as Ar or an inert gas such as nitrogen or in vacuum.

The step of removing fluorine may be performed by another method and is not limited to the above method.
As another method, for example, a method of performing temperature rising annealing at 1000 ° C. for 2 hours or 1100 ° C. for 1 hour in an H ₂ or NH ₃ atmosphere of 76 Torr may be used.

Next, as shown in FIG. 5, atmospheric pressure MOVPE
By the method, the p-type contact layer 12 made of Mg-doped GaN having a layer thickness of 3 to 5 μm is formed.

Next, as shown in FIG. 6, a metal mask and E
Using the B vapor deposition method, a stripe shape having a width of, for example, about 10 μm and a thickness of 3 is formed in a region including the p-type contact layer 12.
A mask 18 made of Ni of about 5 μm is deposited. Then, using CF ₄ as an etching gas, for example, by RIE, as shown in FIG. 7, parts other than below the mask 18 are removed until the n-type contact layer 4 is exposed,
Form a mesa-shaped portion. After that, the mask 18 is removed using hydrochloric acid or the like.

Next, as shown in FIG. 8, an insulating film 1 such as Si ₃ N ₄ is formed.
7 is formed on the side surface of the mesa-shaped portion and a part of the etched surface of the n-type contact layer 4 by ECR plasma CVD method, photolithography and etching. After that, an n-type electrode 16 of, for example, Au / Ti is formed on the mesa-etched surface of the n-type contact layer 4, and the p-type electrode 1 of Au / Pd is formed on the p-type contact layer 12.
5 is formed.

Finally, for example, by cleavage, a resonator structure having a resonator length of 300 μm is formed in the stripe extending direction, and the LD chip of the first embodiment shown in FIG. 1 is completed.

On the resonator surface of the LD chip, Si ₃ N ₄ ,
It is also possible to form an end face high reflection film or a low reflection film such as a dielectric multilayer film in which SiO ₂ , Al ₂ O ₃ , TiO ₂ , ZrO _{2 and the} like are laminated.

By the manufacturing method of the first embodiment described above, the growth temperature of the p-type second cladding layer 10 was changed and L of Samples 1 to 5 was changed.
A D chip was produced. In addition, for comparison, even when the step of removing the fluorine remaining on the surface was not performed after the wet etching step using buffered hydrofluoric acid, the growth temperature of the p-type second cladding layer 10 was changed and samples 6 to 6 were used. Ten LD chips were produced.

With respect to these LD chips, the step density and the fluorine concentration at the upper surface of the p-type second cladding layer 10, that is, the bonding surface with the p-type contact layer 12 which becomes the current passage 13 of the p-type second cladding layer 10 were measured. It was measured. The results are shown in Table 1. The step density is a cross-sectional transmission electron microscope (XTEM) image of a cross section (AA cross section in FIG. 1) parallel to the extending direction of the stripes of the p-type second cladding layer 10 and perpendicular to the substrate. It was measured by observation, and the fluorine concentration was measured by secondary ion mass spectrometry (SIMS). Further, the step density on the upper surface of the p-type second cladding layer 10 can be controlled by changing the growth temperature of the p-type second cladding layer 10. Specifically, the growth temperature of the p-type second cladding layer 10 is 1150 ° C. in Samples 1 and 6, 1130 ° C. in Samples 2 and 7, 1110 ° C. in Samples 3 and 8, and in Samples 4 and 9 1
090 ° C., and in Samples 5 and 10, it is 1070 ° C.
In this example, the step density on the upper surface of the p-type second cladding layer 10 was controlled by changing the growth temperature of the p-type second cladding layer 10, but other methods, for example, the sapphire substrate 1 It is also possible to control the inclination angle of the upper surface.

[0045]

[Table 1]

As can be seen from Table 1, in all the LD chips of Samples 1 to 5 in which the step of removing fluorine after the wet etching with buffered hydrofluoric acid was performed, the fluorine concentration on the upper surface of the p-type second cladding layer 10 was It is 2 × 10 ¹¹ cm ⁻² or less.

On the other hand, the step of removing fluorine was not performed.
Samples 6 to 10 also had a p-type second cladding layer 10
Step density on the top is 5 × 10^Fivecm^-1Sample 6 below,
The LD chips 7 and 8 are the upper surface of the p-type second cladding layer 10.
Fluorine concentration is 2 × 10¹¹cm^-2It is the following. P-type
The step density of the upper surface of the second cladding layer 10 is 5 × 10. ^Five
cm^-1The samples 9 and 10 above are the p-type second cladding layer 10
Fluorine concentration on the upper surface of 2 x 10¹¹cm^-2That is all.

Next, with respect to the LD chips of these samples 1 to 10, the operating current at an operating light output of 30 mW was measured. The results are shown in Table 2.

[0049]

[Table 2]

As can be seen from Table 2, the p-type second cladding layer
The fluorine concentration on the upper surface of 10 is 2 × 10 ¹¹cm^-2The following samples
The LD chips of 1 to 8 are compared with the LD chips of samples 9 and 10.
In addition, the operating current is low and the life is greatly extended.

That is, in the LD chips of Samples 1 to 8 of the first embodiment, the fluorine concentration at the junction interface between the p-type second cladding layer 10 and the p-type contact layer 12 serving as a current path is 2 × 1.
It is as low as 0 ¹¹ cm ^-2 or less, and the interface state density of these interfaces is small. Therefore, the current component that does not contribute to light emission is reduced, and the operating current and the threshold current density are reduced. Therefore, heat generation of the element can be suppressed and reliability is improved.

Further, the lower limit of the fluorine concentration at the junction interface between the p-type second cladding layer 10 and the p-type contact layer 12, which serves as a current path, was examined, and when the concentration was 1 × 10 ¹⁰ cm ⁻² or more, the LD chip It was confirmed that the operating current was low and the life was long. Furthermore, when the lower limit of the step density on the upper surface of the p-type second cladding layer 10 is examined, it is 3
It was confirmed that the fluorine concentration was 2 × 10 ¹¹ cm ^-2 or less without a fluorine removing step at × 10 ⁴ cm ^-1 or more, the operating current of the LD chip was low, and the life was long.

In the first embodiment, the current confinement layer 14 sandwiching the p-type second cladding layer 10 is formed of the n-type nitride semiconductor layer, but an undoped nitride semiconductor such as i-GaN or i-AlGaN is used. It may be formed of a high resistance semiconductor layer.

FIG. 9 is a perspective view of an LD chip of the second embodiment, which is the second embodiment of the semiconductor device of the present invention.

This LD chip has a layer thickness of about 15 nm on the (0001) plane of the sapphire substrate 21 of AlGaN.
A buffer layer 22 made of is formed. On the buffer layer 22, undoped G having a layer thickness of about 0.5 μm is formed.
An aN layer 23 and an n-type GaN layer having a thickness of about 4 μm
-Type contact layer 24 and n-type Ga having a layer thickness of about 0.1 μm
Crack prevention layer 25 made of InN and layer thickness 0.45μ
n-type second cladding layer 2 made of n-type AlGaN of about m
6 and an n-type first made of n-type GaN with a layer thickness of about 50 nm
A cladding layer 27 and a light emitting layer 28 made of GaInN MQW are formed. The light emitting layer 28 having the MQW structure includes an undoped GaN barrier layer having a layer thickness of about 4 nm and a layer thickness of 4 n.
It is configured by alternately stacking undoped GaInN well layers having a compressive strain of about m, for example, Ga
There are 5 N barrier layers and 4 GaInN well layers.

On the light emitting layer 8, a p-type first clad layer 29 made of p-type GaN having a layer thickness of about 40 nm and a p-type second clad layer 30 made of p-type AlGaN having a layer thickness of about 0.45 μm. A cap layer 31 made of p-type GaN having a layer thickness of about 50 nm and a p-type contact layer 32 made of p-type GaN having a layer thickness of 3 to 5 μm are formed in this order. The width of the cap layer 31 and the p-type contact layer 32 is 2 μm.
m-striped current paths 33 connected between the cap layer 31 and the p-type contact layer 32, except for the current path 33, a current of about 0.2 μm thick made of Si nitride. The constriction layer 34 is formed.

In the layers from the middle of the n-type contact layer 24 to the p-type contact layer 32, a mesa-shaped portion having a width of about 10 μm is formed by mesa etching. Also, p
A p-type electrode 35 is formed on the type contact layer 32, and an n-type electrode 36 is formed on the surface of the n-type contact layer 34 exposed by mesa etching. An insulating film 37 made of Si ₃ N ₄ or the like is formed on both side surfaces of the mesa-shaped portion and a part of the exposed surface of the n-type contact layer 24.

Each layer made of the nitride semiconductor of the LD chip shown in FIG. 9 is formed by sapphire substrate 2 by MOVPE method.
1 is formed on.

Next, a method of manufacturing the LD chip of the second embodiment will be described.

10 to 14 are vertical cross-sectional views for each step showing the method of manufacturing the LD chip of the second embodiment.

First, as shown in FIG. 10, the substrate temperature is first kept at 600 ° C., and the buffer layer 22 made of AlGaN is formed on the substrate 1 to have a layer thickness of about 15 nm. Next, with the substrate temperature kept at 1150 ° C., the undoped GaN layer 23 having a layer thickness of about 0.5 μm and the Si-doped G having a layer thickness of about 4 μm.
An n-type contact layer 24 made of aN is formed. Further, the substrate temperature is kept to 880 ° C., to form a crack preventing layer 25 consisting of Si-doped thickness of about 0.1 [mu] m n-type Ga _{0. 95} In _0.05 N. Next, the substrate temperature was kept at 1150 ° C., and the layer thickness was about 0.45 μm. Si-doped Al _0.15 G
a _0.85 N n-type second cladding layer 26 and a layer thickness of 50
The n-type first clad layer 27 made of Si-doped GaN having a thickness of about nm is formed. Further, the substrate temperature is kept at 880 ° C., a barrier layer made of undoped GaN having a layer thickness of about 4 nm and undoped Ga _0.85 In _0.15 N having a layer thickness of about 4 nm.
MQW of GaInN by alternately stacking well layers of
The light emitting layer 28 is formed. Finally, set the substrate temperature to 1
Mg-doped GaN with a layer thickness of about 40 nm kept at 150 ° C.
P-type first clad layer 29 composed of, and a layer thickness of 0.45 μm
P-type second cladding layer 30 made of Mg-doped AlGaN and Mg-doped p-type Ga having a layer thickness of about 50 nm
A cap layer 31 made of N is formed. The buffer layer 22 to the cap layer 31 are MOVs at normal pressure.
It is formed by the PE method.

After that, Si nitride such as Si ₃ N ₄ having a film thickness of about 0.2 μm to be the current confinement layer 34 is formed on the entire surface of the cap layer 31 by, for example, the ECR plasma CVD method. Next, by photolithography and wet etching using buffered hydrofluoric acid, as shown in FIG. 11, a stripe-shaped current passage 3 having a width of about 2 μm is formed.
The Si nitride corresponding to the portion 3 is removed until the cap layer 31 is exposed to form the current confinement layer 34 made of Si nitride.

After this step, a step of removing fluorine remaining on the surface of the cap layer 31 is performed after the above-mentioned wet etching step. In addition, the step of removing fluorine is
The same procedure as in the above-described first embodiment may be performed.

Next, as shown in FIG. 12, for example, 76T.
Or, under the reduced pressure MOVPE method, the layer thickness of M is 3 to 5 μm.
Form a p-type contact layer 32 made of g-doped GaN
It At this time, selectively expose the exposed portion of the cap layer 31.
Adjust growth conditions appropriately so that p-type GaN grows
It For example, increase the substrate temperature by about 100 ° C. ₃of
The flow rate may be increased about 3 times. Under such conditions
When the length is increased, first the p-type is formed on the exposed portion of the cap layer 31.
GaN grows to form a portion corresponding to the current path 33.
It On the other hand, crystal growth of p-type GaN occurs on the current confinement layer 34.
do not do. When the crystal growth is continued, the current passage 33
P-type G grown on the current path 33 while growing above
Crystal growth starts laterally from the side surface of the aN, and the current confinement layer
P-type contact layer 32 made of p-type GaN is formed on
Is made. For example, in the second embodiment, the current path 33 is
A p-type contact layer with a width of about 8 μm centered around the barrel
32 is formed. As a result, the cap layer 31 and the p-type
The contact layer 32 is a stripe-shaped current with a width of about 2 μm.
Connected by passage 33, p-type contact with cap layer 31
Between the layers 32, except for the current passage 33, the film thickness
A current confinement layer 34 of about 0.2 μm is formed.

Next, using a metal mask and an EB vapor deposition method, for example, a width of 10 is formed in a region including the p-type contact layer 12.
A mask made of Ni having a stripe shape of about μm and a thickness of 3 to 5 μm is deposited. Then, using, for example, CF ₄ as an etching gas, for example, by the RIE method,
As shown in FIG. 3, a portion other than the lower portion of the mask is removed until the n-type contact layer 24 is exposed to form a mesa-shaped portion. Then, the mask is removed using hydrochloric acid or the like.

After this step, after the above-mentioned reactive ion etching step with CF ₄ , the n-type contact layer 24
The step of removing the fluorine remaining on the exposed surface of is performed. The step of removing fluorine may be the same as in the first embodiment described above.

Next, as shown in FIG. 14, an insulating film 37 of Si ₃ N ₄ or the like is formed on the side surface of the mesa-shaped portion and n by an ECR plasma CVD method, photolithography and etching.
It is formed on a part of the etched surface of the mold contact layer 24. Then, for example, an Au / Ti n-type electrode 36 is formed on the mesa-etched surface of the n-type contact layer 24, and an Au / Pd p-type electrode 35 is formed on the p-type contact layer 32.

Finally, for example, by cleavage, a resonator structure having a resonator length of 300 μm is formed in the stripe extending direction, and the LD chip of the second embodiment shown in FIG. 9 is completed.

On the resonator surface of the LD chip, Si ₃ N ₄ ,
It is also possible to form an end face high reflection film or a low reflection film such as a dielectric multilayer film in which SiO ₂ , Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO _{2 and the} like are laminated.

In this embodiment, Si nitride is formed as the current confinement layer, but Si oxide represented by SiO ₂ is used.
Alternatively, an insulator represented by the general formula SiOxNy may be used, and further, Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO ₂ may be used.
You may use insulators, such as. In particular, Si oxide, SiO
The effect of the present invention is high when an insulator which is easily etched by a hydrofluoric acid-based etchant such as xNy, TiO ₂ , ZrO ₂ , or HfO ₂ is used.

Also in this second embodiment, the fluorine concentration at the junction interface between the cap layer 31 and the p-type contact layer 32, which serves as a current path, is as low as 2 × 10 ¹¹ cm ^-2 or less, and the interface level of these interfaces is low. When the unit density is small, the current component that does not contribute to light emission is small, and the operating current and the threshold current density are low. Therefore, heat generation of the element can be suppressed and reliability is improved.

Further, even if the fluorine removing step is not performed, the fluorine concentration at the bonding interface can be reduced by reducing the step density on the upper surface of the cap layer 11. The step density on the upper surface of the cap layer 11 is
For example, it can be controlled by changing the growth temperature of the cap layer 11 as in the first embodiment.

FIG. 15 is a perspective view of an LD chip of a third example which is the third embodiment of the present invention.

In this LD chip, on the (0001) plane of the sapphire substrate 41, AlGaN having a layer thickness of about 15 nm is used.
A buffer layer 42 of is formed. On the buffer layer 42, undoped G having a layer thickness of about 0.5 μm is formed.
n made of aN layer 43 and n-type GaN having a layer thickness of about 4 μm
-Type contact layer 44 and n-type Ga having a layer thickness of about 0.1 μm
InN crack prevention layer 45 and layer thickness 0.45μ
n-type second cladding layer 4 made of about n-type AlGaN
6 and an n-type first made of n-type GaN with a layer thickness of about 50 nm
A clad layer 47 and a light emitting layer 48 made of GaInN MQW are formed. The light emitting layer 48 of the MQW structure is a barrier layer made of undoped GaN having a layer thickness of about 4 nm,
It is configured by alternately stacking well layers made of undoped GaInN having a compressive strain and having a layer thickness of about 4 nm. For example, the GaN barrier layer has five layers and the GaInN well layer has four layers.

On the light emitting layer 48, a p-type first clad layer 49 of p-type GaN having a layer thickness of about 40 nm and a p-type second clad layer 50 of p-type AlGaN having a layer thickness of about 0.45 μm are provided. A cap layer 51 made of p-type GaN having a layer thickness of about 50 nm and a p-type contact layer 52 made of p-type GaN having a layer thickness of 3 to 5 μm are formed in this order. p-type first clad layer 49 and p-type second clad layer 50
Are connected to each other by a stripe-shaped current passage 53 having a width of about 2 μm, and between the p-type first clad layer 49 and the p-type second clad layer 50, a film thickness of 0. A current confinement layer 54 of about 2 μm made of n-type GaN is formed.

In the layers from the middle of the n-type contact layer 44 to the p-type contact layer 52, a mesa-shaped portion having a width of about 10 μm is formed by mesa etching. Also, p
A p-type electrode 55 is formed on the type contact layer 52, and an n-type electrode 56 is formed on the surface of the n-type contact layer 54 exposed by mesa etching. An insulating film 57 made of Si ₃ N ₄ or the like is formed on both side surfaces of the mesa-shaped portion and a part of the exposed surface of the n-type contact layer 44.

Each layer made of the nitride semiconductor of the LD chip shown in FIG. 15 is formed on the sapphire substrate 21 by the MOVPE method. Examples of the source gas at this time include trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMI).
n), NH ₃ , SiH ₄ , and cyclopentadienyl magnesium (Cp ₂ Mg) are used.

16 to 18 are vertical cross-sectional views for each step showing the method of manufacturing the LD chip of the third embodiment.

First, as shown in FIG. 16, the substrate temperature is set to 6
Keeping the temperature at 00 ° C., from AlGaN on the sapphire substrate 41
The buffer layer 42 is formed to have a layer thickness of about 15 nm. Next
In addition, the substrate temperature is kept at 1150 ° C and the layer thickness is about 0.5 μm.
Undoped GaN layer 43 and Si having a layer thickness of about 4 μm
The n-type contact layer 44 made of doped GaN is formed in order.
Form. Furthermore, keep the substrate temperature at 880 ° C and
Si-doped n-type Ga of about 0.1 μm_0.95In_0.05N
A crack prevention layer 45 made of is formed. Next, the substrate temperature
Temperature of 1150 ° C and a layer thickness of 0.45 μm
Of Al_0.15Ga _0.85N-type second cladding layer made of N
46 and Si-doped GaN with a layer thickness of about 50 nm
The n-type first cladding layer 47 is formed. In addition, the substrate temperature
Is maintained at 880 ° C., and the layer thickness is formed on the n-type first cladding layer 47.
Barrier layer composed of undoped GaN of about 4 nm and layer thickness
Undoped Ga of about 4 nm_0.85In_0.15Consists of N
It is composed of GaInN MQW by alternately stacking well layers.
The light emitting layer 48 is formed. Finally, set the substrate temperature to 1150 ° C
Of Mg-doped GaN with a layer thickness of about 40 nm.
P-type first clad layer 49 and S having a layer thickness of about 0.2 μm
A current confinement layer 54 made of i-doped GaN is formed.

Then, at a predetermined position on the current confinement layer 54,
For example, SiO having a film thickness of about 0.2 μm ₂Si oxide such as
A mask 51 is formed.

Next, using CF ₄ as an etching gas, for example, the current confinement layer 54 other than below the mask 51 is removed by, eg, RIE until the first p-type cladding layer 49 is exposed. Like p-type 1
A current path 53 is formed on the upper surface of the clad layer 49.

After this step, after the RIE step, a step of removing fluorine remaining on the exposed upper surface of the p-type first cladding layer 49 is performed. The step of removing fluorine may be the same as the step of the first embodiment described above.

Next, as shown in FIG. 18, the layer thickness 0.4
A p-type second layer made of Mg-doped AlGaN having a thickness of about 5 μm
Clad layer 50, Mg-doped GaN with a layer thickness of 3 to 5 μm
Then, the p-type contact layer 52 of is formed.

After that, the LD chip of the third embodiment shown in FIG. 15 is completed by the same steps as the steps described in FIGS. 13 and 14 of the second embodiment.

Even if the fluorine removing step is not performed, the step density of the exposed upper surface of the p-type first cladding layer 49 is reduced to reduce the p-type first cladding layer 49 and the p-type second cladding layer 49.
The fluorine concentration at the bonding interface with the cladding layer 50 can be reduced. The step density of the exposed upper surface of the p-type first cladding layer 49 is controlled by the etching rate when removing the current confinement layer 54 by RIE, as described in detail in a fourth embodiment described later. You can do it.

Also in this third embodiment, the fluorine concentration at the junction interface between the p-type first clad layer 9 and the p-type second clad layer 10 serving as a current path is as low as 2 × 10 ¹¹ cm ^-2 or less, When the interface state density of these interfaces is small, the current component that does not contribute to light emission is small, and the operating current and the threshold current density are low. Therefore, heat generation of the element can be suppressed and reliability is improved.

In the third embodiment, the current confinement layer 54 is n
Type nitride semiconductor layer, i-GaN, i-GaN,
It may be formed of a high resistance semiconductor layer such as an undoped nitride semiconductor such as AlGaN.

FIG. 19 is a sectional view of a light emitting diode element (hereinafter referred to as an LED chip) of a fourth example which is the fourth embodiment of the present invention.

This LED chip has a sapphire substrate 61.
On the (0001) plane of AlGa with a layer thickness of about 15 nm.
A buffer layer 62 made of N is formed. On the buffer layer 62, an undoped GaN layer 63 having a layer thickness of about 0.5 μm, an n-type contact layer 64 made of n-type GaN having a layer thickness of about 4 μm, and n-type AlGaN having a layer thickness of about 0.45 μm. N-type clad layer 66 and GaInN
Of the MQW is formed. This M
The QW structure light emitting layer 68 is configured by alternately stacking a barrier layer made of undoped GaN having a layer thickness of about 4 nm and a well layer made of undoped GaInN having a layer thickness of about 4 nm, for example. , GaN barrier layers are 5 layers, and GaInN well layers are 4 layers.

On the light emitting layer 68, a p-type clad layer 70 made of p-type AlGaN having a layer thickness of about 0.45 μm and a p-type contact layer 72 made of p-type GaN having a layer thickness of 3 to 5 μm.
Are formed in this order. A p-type electrode 75 is formed on the p-type contact layer 72, and an n-type electrode 76 is formed on the surface of the n-type contact layer 64 exposed by mesa etching.

Next, a method of manufacturing the LED chip of the fourth embodiment will be described.

20 and 21 are longitudinal sectional views showing a method of manufacturing an LED chip according to the fourth embodiment.

First, as shown in FIG. 20, the substrate temperature is first maintained at 600 ° C., and AlGaN is formed on the sapphire substrate 61.
A buffer layer 62 made of is formed with a layer thickness of about 15 nm.
Next, the substrate temperature is maintained at 1150 ° C., the undoped GaN layer 63 having a layer thickness of about 0.5 μm, and the S layer having a layer thickness of about 4 μm.
An n-type contact layer 64 made of i-doped GaN and Si-doped Al _0.15 Ga _0.85 N having a layer thickness of about 0.45 μm
An n-type clad layer 66 made of is formed. Further, the substrate temperature is kept to 880 ° C., and a well layer made of undoped Ga _0.75 In _{0. 25} N barrier layer and the thickness of approximately 4nm of undoped GaN of thickness of about 4nm are alternately stacked,
A light emitting layer 68 made of GaInN MQW is formed. Finally, the substrate temperature was kept at 1150 ° C and the layer thickness was 0.45 μm.
P-type cladding layer 7 made of approximately Mg-doped AlGaN
0, a p-type contact layer 72 made of Mg-doped GaN having a layer thickness of 3 to 5 μm is formed.

Next, using a metal mask and an EB vapor deposition method, a thickness of 3 to 5 μm is formed in a predetermined region of the p-type contact layer 72.
A mask 78 made of Ni of m is deposited.

Next, by using, for example, CF ₄ as an etching gas, by reactive ion etching, for example, as shown in FIG. 22, a portion other than below the mask 78 is removed until the n-type contact layer 64 is exposed. , Forming a mesa-shaped portion. After that, the mask 78 is removed using hydrochloric acid or the like.

After this step, a step of removing fluorine remaining on the surface is performed after the reactive ion etching step with CF ₄ . The step of removing fluorine may be the same as the step of the first embodiment described above.

After that, an n-type electrode 76 of, for example, Au / Ti is formed on the mesa-etched surface of the n-type contact layer 64, and Au / P is formed on the p-type contact layer 72.
A p-type electrode 75 of d is formed.

Through the above steps, the LED chip of the fourth embodiment is manufactured.

In the manufacturing method of the fourth embodiment described above, the LED chips of Samples 11 to 15 were manufactured by changing the etching rate of RIE when forming the mesa-shaped portion. For comparison, even when the step of removing the fluorine remaining on the surface was not performed after forming the mesa-shaped portion, the etching rate of RIE when forming the mesa-shaped portion was changed and the sample was changed. 16 to 20 LED chips were produced.

The step densities of the etched upper surfaces of the n-type contact layer 64 before forming the n-type electrodes 76 of these LED chips were measured using an atomic force microscope (AFM), and the secondary ion mass spectrometry was performed. Law (S
The fluorine concentration was measured using IMS). The results are shown in Table 3. The step density on the upper surface of the n-type contact layer 64 can be controlled by changing the etching rate of RIE when forming the mesa-shaped portion. Specifically, the etching rate of RIE was 0.1 μm / hour for sample 11 and sample 16, and sample 12 and sample 1
7 is 0.2 μm / hour, Samples 13 and 18 are 0.5 μm / hour, and Samples 14 and 19 are 1 μm / hour.
μm / hour, 2 μm / h for sample 15 and sample 20
It is our. In the present embodiment, the n-type contact layer 6
Although the step density of the upper surface of No. 4 was controlled by changing the etching rate of the reactive ion etching, it is also possible to control it by another method, for example, the inclination angle of the upper surface of the sapphire substrate 61.

[0101]

[Table 3]

As can be seen from Table 3, in all the LED chips of Samples 11 to 15 which have been subjected to the step of removing fluorine, the fluorine concentration on the upper surface of the n-type contact layer 64 is 2 × 10 ¹¹ c.
It is less than m ^-2 .

On the other hand, also in Samples 16 to 20 in which the step of removing fluorine was not performed, Sample 1 whose step density on the upper surface of the n-type contact layer 64 was 5 × 10 ⁵ cm ^-1 or less.
In the LED chips 6 and 17, the fluorine concentration on the upper surface of the n-type contact layer 64 is 2 × 10 ¹¹ cm ⁻² or less. Note that n
The step density of the upper surface of the mold contact layer 64 is 5 × 10 ⁵
In Samples 18, 19 and 20 having a cm ⁻¹ or more, the fluorine concentration on the upper surface of the n-type contact layer 64 is 2 × 10 ¹¹ cm ⁻² or more.

Next, the operating current at a luminous intensity of 20 cd was measured for the LED chips of these samples 11 to 20.
The results are shown in Table 4.

[0105]

[Table 4]

As can be seen from Table 4, the n-type contact layer 6
Fluorine concentration on the upper surface of 4 is 2 × 10 ¹¹ cm ^-2 or less Sample 1
The LED chips 1 to 17 have a lower operating current and a significantly longer life than the LED chips of the samples 18 to 20.

That is, LE of the fourth embodiment of samples 11 to 17
In the D chip, the n-type contact layer 64 which becomes a current path and
The fluorine concentration at the junction interface with the n-type electrode 76 is 2 × 10.¹¹
cm ^-2It is as low as or less, and the interface state density of these interfaces is small.
Become Therefore, in the case of a light emitting element, it does not contribute to light emission.
Low current component, low operating current and low threshold current density
it can. Therefore, heat generation of the element can be suppressed, and reliability is improved.
The property is improved.

Further, the n-type contact layer 6 serving as a current path
As a result of examining the lower limit of the fluorine concentration at the bonding interface between the No. 4 and the n-type electrode 76, at a concentration of 1 × 10 ¹⁰ cm ^-2 or more,
It was confirmed that the operating current of the LED chip was low and the life was long. Furthermore, when the lower limit of the step density on the upper surface of the n-type contact layer 64 was examined, it was 3 × 10 ⁴ c
It was confirmed that at m ⁻¹ or more, the fluorine concentration was 2 × 10 ¹¹ cm ⁻² or less even without the fluorine removal step, the operating current of the LD chip was low, and the life was long.

Further, in the fourth embodiment, the case where the n-type electrode is formed on the etching surface of the n-type semiconductor layer has been described, but the same applies to the case where the p-type electrode is formed on the etching surface of the p-type semiconductor layer. The effect is obtained.

The above-mentioned second embodiment having the step of removing the fluorine after forming the mesa-shaped portion by RIE, or the above-mentioned second embodiment having the step of forming the mesa-shaped portion by RIE and then removing the fluorine. Also in the first and third embodiments, the fluorine concentration at the junction interface between the n-type electrode and the n-type contact layer serving as a current path has a fluorine concentration of 2 × 10 ¹¹ c.
When it is as low as m ⁻² or less and the interface state density of these interfaces is small, the current component that does not contribute to light emission is small and the operating current and the threshold current density can be reduced, as in the fourth embodiment.
Therefore, heat generation of the element can be suppressed and reliability is improved.

FIG. 22 is a sectional view of the LED chip of the fifth embodiment, which is the fifth embodiment of the present invention.

This LED chip is an n-type Si substrate 10
On the (111) plane of 0, the longitudinal direction is Si [11-2]
The first selective growth film 101 made of SiO ₂ and having a layer thickness of about 0.5 μm and having a stripe-shaped opening having a period of 40 μm and a width of 5 μm, and a layer thickness of 0. A first buffer layer 102 made of n-type Al _0.09 Ga _0.91 N having a thickness of about 05 μm and a second buffer layer 103 made of n-type GaN having a layer thickness of about 0.5 μm are formed. On the second buffer layer 103, the longitudinal direction is S
Layer thickness 0.5 μm having stripe-shaped openings parallel to the [11-2] direction of i, having a period of 40 μm and a width of 5 μm
A second selective growth film 104 made of SiO ₂ is formed. Here, the stripe-shaped openings of the second selective growth film 104 are formed so as not to coincide with the stripe-shaped openings of the first selective growth film 101.

Then, on the second selective growth film 104,
Third buffer layer 8 made of n-type GaN having a layer thickness of about 4 μm
4, an n-type clad layer 86 made of n-type AlGaN having a layer thickness of about 0.45 μm, and a light-emitting layer 88 made of GaInN MQW. This MQW structure light emitting layer 8
Reference numeral 8 indicates a barrier layer made of undoped GaN having a layer thickness of about 4 nm and undoped GaIn having a compressive strain of about 4 nm.
It is configured by alternately stacking well layers made of N. For example, the GaN barrier layer has 5 layers and the GaInN well layer has 4 layers.

A p-type clad layer 90 made of p-type AlGaN having a layer thickness of about 0.45 μm and a layer thickness of 3 are formed on the light emitting layer 8.
A p-type contact layer 92 made of p-type GaN having a thickness of ˜5 μm is formed in this order. Then, the p-type contact layer 9
A p-type electrode 95 is formed on the second substrate 2, and an n-type electrode 96 is formed on the back surface of the Si substrate 100.

Next, a method of manufacturing the LED chip of the fifth embodiment will be described.

23 and 24 show the LED of the fifth embodiment.
It is sectional drawing which shows the manufacturing method of a chip.

First, as shown in FIG. 23, the substrate temperature is set to 1
The first selective growth film 101 was formed by keeping the temperature at 150 ° C.
On the i substrate 100, for example, a reduced pressure MOVP of 76 Torr
After the first buffer layer 102 made of Si-doped AlGaN is formed by the E method, the substrate temperature is changed as will be described later, and the second buffer layer 103 made of a Si-doped GaN layer having a layer thickness of about 0.5 μm. To form. On this occasion,
The growth conditions are appropriately adjusted so that the first buffer layer 102 is selectively grown on the exposed portion of the Si substrate 1.
When the crystal growth is continued, the first buffer layer 1
02, and crystal growth started in the lateral direction,
A second buffer layer 103 made of n-type GaN is formed on the first selective growth film 101.

After that, for example, SiO ₂ to be the second selective growth film 104 is formed. Next, SiO ₂ is removed by photolithography and wet etching using buffered hydrofluoric acid so as to form a predetermined stripe shape, and the second buffer layer 103 at this portion is exposed.

After this step, a step of removing the fluorine remaining on the surface after the wet etching step is performed. The step of removing fluorine may be the same as the step of the first embodiment described above.

Thereafter, as shown in FIG. 24, the substrate temperature was kept at 1150 ° C. and the Si-doped Ga having a layer thickness of about 4 μm was formed.
An n-type contact layer 84 made of N and an n-type clad layer 86 made of Si-doped Al _0.15 Ga _0.85 N having a layer thickness of about 0.45 μm are formed. Further, the substrate temperature is kept at 880 ° C., and an undoped GaN barrier layer having a layer thickness of about 4 nm and an undoped Ga _0.75 In _0.25 N well layer having a layer thickness of about 4 nm are alternately laminated to form a GaInN MQW. The light emitting layer 88 is formed. Finally, set the substrate temperature to 1150
Mg-doped AlGa with a layer thickness of about 0.45 μm
P-type clad layer 90 made of N, M having a layer thickness of 3 to 5 μm
A p-type contact layer 102 made of g-doped GaN is formed.

On the back surface of the Si substrate 100, Au /
An n-type electrode 96 of Ti is formed, and a p-type electrode 95 of Au / Pd is formed on the p-type contact layer 92.

Through the above steps, the LED chip of the fifth embodiment is manufactured.

In the manufacturing method of the fifth embodiment described above, the LED chips of Samples 21 to 25 were manufactured by changing the growth temperature when forming the second buffer layer 103. For comparison, a step of removing SiO ₂ by wet etching so as to form a predetermined stripe shape, exposing the second buffer layer 103 in this portion, and then removing fluorine remaining on the surface is performed. Even when the sample 26 was not formed, the growth temperature when forming the second buffer layer 103 was changed and the sample 26
~ 30 LED chips were produced. The growth temperature of the second buffer layer 103 is 11 in Samples 21 and 26.
00 ° C, Sample 22 and Sample 27: 1080 ° C, Sample 2
1060 ° C. for Sample 3 and Sample 28, Sample 24 and Sample 29
1040 ° C. for sample 25 and sample 1020 ° C.
Is.

For these LED chips, the step density and the fluorine concentration of the etched surface of the second buffer layer 103 before the formation of the second selective growth film 104 was measured using an atomic force microscope (AFM). did.
The results are shown in Table 5. The step density is measured by observing a cross section of the second buffer layer 103 perpendicular to the substrate by observing a cross section transmission electron microscope (XTEM) image, and the fluorine concentration is measured by secondary ion mass spectrometry (SIMS). It was measured using. In this embodiment, the step density on the upper surface of the second buffer layer is controlled by changing the growth temperature of the second buffer layer 103, but it can be controlled by other methods.

[0125]

[Table 5]

As can be seen from Table 5, a process for removing fluorine
The LED chips of Samples 21 to 25 which were subjected to
The fluorine concentration on the upper surface of the buffer layer 103 of 2 × 10¹¹
cm ^-2It is the following.

On the other hand, the step of removing fluorine was not performed.
Samples 26 to 30 also have the second buffer layer 103.
The step density on the top surface of the^Fivecm^-1Sample 2 below
The LED chips 6 and 27 are formed on the second buffer layer 103.
Fluorine concentration on the upper surface is 2 × 10 ¹¹cm^-2It is the following. still,
The step density on the upper surface of the second buffer layer 103 is 5 × 1.
0^Fivecm^-1The samples 28, 29, and 30 described above are the second bag.
The fluorine concentration on the upper surface of the phosphor layer 103 is 2 × 10¹¹cm^-2Since
Above.

Next, the operating current at a luminous intensity of 20 cd was measured for the LED chips of these samples 21 to 30.
The results are shown in Table 6.

[0129]

[Table 6]

As can be seen from Table 6, the second buffer layer 1
The top surface of 03 has a fluorine concentration of 2 × 10 ¹¹cm^-2The following samples
21-27 LED chips are samples 28-30 LEDs
Low operating current and significantly longer life than chips
It

That is, LE of the fifth embodiment of samples 21 to 27
In the D chip, the second buffer layer 103 serving as a current path
The fluorine concentration at the junction interface between the n-type contact layer 84 and the n-type contact layer 84 is as low as 2 × 10 ¹¹ cm ⁻² or less, and the interface state density at these interfaces becomes small. Therefore, in the case of the light emitting element, the current component that does not contribute to light emission is reduced, and the operating current and the threshold current density can be reduced. Therefore, heat generation of the element can be suppressed and reliability is improved.

The second buffer layer 1 serving as a current path
When the lower limit of the fluorine concentration at the bonding interface between the No. 03 and the n-type contact layer 84 was examined, it was confirmed that the operating current of the LED chip was low and the life was long at 1 × 10 ¹⁰ cm ⁻² or more. Further, the second buffer layer 103
As for the lower limit of the step density on the upper surface of,
It was confirmed that at a concentration of 3 × 10 ⁴ cm ⁻¹ or more, the fluorine concentration was 2 × 10 ¹¹ cm ⁻² or less even without the fluorine removing step, the operating current of the LD chip was low, and the life was long.

Although the Si substrate is used in the fifth embodiment, the same effect can be obtained when a GaN substrate, a GaAs substrate or the like is used.

Further, in the above-mentioned first to fourth embodiments, the n-type semiconductor layer is first formed on the substrate, but the p-type semiconductor layer may be formed first.

In the first to fourth embodiments, the semiconductor layer is grown on the (0001) plane of the sapphire substrate. However, other semiconductor layers such as the (1-100) plane and (11-20) plane of the sapphire substrate are grown. The semiconductor layer may be grown on the plane of the plane orientation. Alternatively, the same effect can be obtained by using a Si substrate, a GaN substrate, a GaAs substrate, or the like.

Although the stripe type LD chips have been described in the first to third embodiments, the surface emitting type L chip is used.
The present invention can also be applied to the D chip.

[0137]

Further, in the first to fifth embodiments, the semiconductor element and the semiconductor laser element using the wurtzite type as the crystal structure of the nitride semiconductor have been described in detail. The crystal structure of the semiconductor is the zinc blende type. It may be a structure.

In each of the first to fifth embodiments, each semiconductor layer is formed by MOVPE method. However, for example, halide vapor phase epitaxy method, MBE method, TMAl, TMGa, TMI are used.
It can also be formed by a gas source MBE method using n, NH ₃ , SiH ₄ , Cp ₂ Mg or the like as a source gas.

[0140]

[0141]

According to the present invention, by reducing the current component which does not contribute to light emission, reduce the operation current and the threshold current density, suppressing heat generation of the element, to provide a light emitting device which is suitable for long life obtain.

[Brief description of drawings]

FIG. 1 is a perspective view showing a configuration of an LD chip according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the LD chip of the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the LD chip of the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the method of manufacturing the LD chip of the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the LD chip of the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing the LD chip of the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the method of manufacturing the LD chip of the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the method of manufacturing the LD chip of the first embodiment of the present invention.

FIG. 9 is a perspective view showing the structure of an LD chip according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the method of manufacturing the LD chip of the second embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the method of manufacturing the LD chip of the second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing the method of manufacturing the LD chip of the second embodiment of the present invention.

FIG. 13 is a cross-sectional view showing the method of manufacturing the LD chip of the second embodiment of the present invention.

FIG. 14 is a cross-sectional view showing the method of manufacturing the LD chip of the second embodiment of the present invention.

FIG. 15 is a perspective view showing the structure of an LD chip according to a third embodiment of the present invention.

FIG. 16 is a cross-sectional view showing the method of manufacturing the LD chip of the third embodiment of the present invention.

FIG. 17 is a cross-sectional view showing the method of manufacturing the LD chip of the third embodiment of the present invention.

FIG. 18 is a cross-sectional view showing the method of manufacturing the LD chip of the third embodiment of the present invention.

FIG. 19 is a perspective view showing the structure of an LED chip according to a fourth embodiment of the present invention.

FIG. 20 is a cross-sectional view showing the method of manufacturing the LED chip of the fourth embodiment of the present invention.

FIG. 21 is a cross-sectional view showing the method of manufacturing the LED chip of the fourth embodiment of the present invention.

FIG. 22 is a perspective view showing the structure of an LED chip according to a fifth embodiment of the present invention.

FIG. 23 is a cross-sectional view showing the method of manufacturing the LED chip of the fifth embodiment of the present invention.

FIG. 24 is a cross-sectional view showing the method of manufacturing the LED chip of the fifth embodiment of the present invention.

[Explanation of sign]

8 Light emitting layer 10 p-type second cladding layer (first nitride semiconductor layer) 12 p-type contact layer (second nitride semiconductor layer) 13 Current passage 14 Current constriction layer 24 n-type contact layer (first nitride semiconductor layer) 28 Light-emitting layer 31 Cap layer (first nitride semiconductor layer) 32 p-type contact layer (second nitride semiconductor layer) 33 Current path 34 Current constriction layer 36 n-type electrode 44 n-type contact layer (first nitride semiconductor layer) 48 light emitting layer 49 p-type first cladding layer (first nitride-based semiconductor layer) 50 p-type second cladding layer (second nitride-based semiconductor layer) 53 Current path 54 Current constriction layer 56 n-type electrode 64 n-type contact layer (first nitride semiconductor layer) 68 Light-emitting layer 76 n-type electrode 84 n-type contact layer (second nitride semiconductor layer) 88 Light-emitting layer 31 Cap layer (first nitride semiconductor layer) 103 Second buffer layer (second nitride-based semiconductor layer)

Continuation of the front page (56) Reference JP-A-8-274081 (JP, A) JP-A-10-294529 (JP, A) JP-A-11-204889 (JP, A) JP-A-9-251977 (JP , A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01S 5/00-5/50 H01L 33/00 H01L 21/304

Claims (6)

(57) [Claims] 1. A first nitride-based semiconductor layer and the first nitride-based semiconductor layer.
And a first nitride semiconductor layer formed on the nitride semiconductor layer.
A second nitride semiconductor layer having a bonding interface with
Controls the width of the current path for the current flowing through the interface to the light-emitting layer.
In a nitride-based light emitting device having a current confinement layer
At the joint interface, the fluorine concentration is 1 × 10 ¹⁰ cm
^-2 or more and 2 × 10 ¹¹ cm ^-2 or less, and the step density is
3 × 10 ⁴ cm ^-1 or more and 5 × 10 ⁵ cm ^-1 or less
And a nitride-based light emitting device. 2. The first nitride-based semiconductor layer is the first nitride-based semiconductor layer.
2. A ridge protruding in a region to be joined to the nitride semiconductor layer 2
And the current confinement layer sandwiches the ridge from the left and right.
It is formed in a hollow shape.
Nitride-based light emitting device. 3. The first nitride semiconductor layer is a first conductive layer.
Type semiconductor or non-doped semiconductor, and the current confinement
The layer is a second conductivity type semiconductor or a high resistance semiconductor,
The second nitride-based semiconductor layer is a first conductivity type semiconductor
The nitride-based light emitting device according to claim 1 or 2. 4. The current confinement layer is an insulator.
The nitride-based light emitting device according to claim 1, 2 or 3, which is a characteristic of the present invention. 5. Japanese said insulator is SiO _x N _y
The nitride-based light emitting device according to claim 4, which is a characteristic. 6. The second layer of the first nitride-based semiconductor layer
Has a step density of 5 × at the junction interface with the nitride-based semiconductor layer.
10. It is 10 ⁵ cm ^-1 or less, claim 1,
2. The nitride-based light emitting device according to 2, 3, 4 or 5.