JP3439114B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device on which an improved TEG is mounted.

[0002]

2. Description of the Related Art In standardizing and optimizing processes,
An important method is evaluation by test patterns, so-called T
This is an evaluation by EG (Test Element Group). TEG
Has two purposes, one is a pattern for process / device check, and the second is a pattern for establishing and confirming new technology.

In any case, the optimum values of the process parameters, device parameters, and design rules are obtained by analyzing the pattern. The TEG includes a process TEG, a device TEG, and a circuit TEG.
There is. These contents are described in, for example, “Latest LSI Process Technology” (published on April 25, 1984, 2nd edition) by the Industrial Research Council.

The present invention is a test pattern for evaluating, in particular, a multilayer wiring, an electrode structure and the like, and examines a pinhole between wirings, a disconnection check, a step of an interlayer insulating film, and a coverage state of a wiring electrode material. On the other hand, in recent semiconductor processes, line rules and contact rules have become strict, and as shown in FIG. 11, the roughness of the film has also become strict. In other words, the wiring increases in two layers, three layers, etc., and as the layers are stacked, the unevenness becomes severe, and in a very thick interlayer insulating film, a contact hole having a high aspect ratio is formed, and a good step coverage is formed here. An important theme is how to create electrode materials. In addition, a material that has not been used in the past, such as W, is also used as the electrode material.

In the semiconductor device shown in FIG. 11, the BPSG film 1 is employed for the purpose of planarizing the film. However, as shown in the figure, irregularities, thick portions, and thin portions are inevitably generated. For example, a LOCOS film 3 is provided on the semiconductor substrate 2, on which electrodes, wirings, and the like are formed. For example,
Reference numeral 4 denotes a poly-Si gate, and reference numeral 5 denotes a wiring mainly made of Al. Of course, these conductive materials are insulated.

On these, various interlayer insulating films are provided to further provide wirings.
And the BPSG film 1 is formed thereon. Further, a barrier metal 8 in which Ti and TiN are laminated is formed in the contact hole 7 and on the surface of the BPSG film 1 via the contact hole 7, and a W plug 9 is formed in the contact hole 7. The wiring 10 is formed.

As described above, the electrodes 45 are stacked, and the BPSG film 1 or the like, for example, is formed thick to fill the irregularities, and the size is reduced in various portions where the interlayer insulating film is thick or thinner. When a contact hole having a high aspect ratio is formed (for example, 0.5 μm or less), the shape of the contact hole, the state of coverage of the barrier metal, the state of burying W, and the case where W is not adopted, of the electrode contacting the contact hole are naturally The step coverage state and the formation state of the wiring of the interlayer insulating film having irregularities are problems, and the TEG is used.

[0008]

However, almost 0.
In order to examine the state of W embedded in a contact hole of 5 μm or less by TEG, it is necessary to split this part and observe it with an electron microscope or the like. However, since W is harder than other materials, there is a problem that the W plug is attached to one of the two without being cracked as shown in FIG. For example, if a rice ball with dried plums is divided into two, the plum dried rice will not break into two pieces and will stick to either side.

Some W and other wirings are floating due to the TEG pattern. When the wiring is broken, the wiring becomes floating. As a result, the wiring is charged up and cannot be seen with an electron microscope.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been achieved by providing means for fixing a TEG pattern of a wiring to a ground of a semiconductor substrate. This problem can be solved by forming a plurality of TEG patterns of wirings collectively in one area and providing a means fixed to the ground of the semiconductor substrate in this one area.

When the TEG is viewed with an electron microscope, since the conductive material of the test element is grounded to GND, no charge-up occurs and good observation is possible. Since the floating gate is surrounded by the control gate and the source electrode, the charge of the floating gate is absorbed, and good observation is possible without being grounded to GND.

The problem is solved by electrically connecting the ground region of the semiconductor substrate with the W plug. Furthermore, if the TEG pattern of the wiring is fixed to the ground of the semiconductor substrate at both ends of this element, when the TEG is divided into two, both wirings are fixed to GND. Therefore, even if seen in the throat Chilla it can be observed without charge up.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the semiconductor device according to the present invention will be described below with reference to the drawings. First, TEG analyzes the characteristics as explained in the conventional example,
The observation of the state of the interlayer insulating film and the electrode material is performed.
It is arranged in a C chip or a scribe line.

In FIG. 10, TEGs 2 and 3 are formed on the scribe line 1. The area on the rectangle surrounded by the scribe line 1 is an IC
This is a portion that becomes the chip 4 and is a region where a semiconductor element forming an IC circuit is formed. The TEG has a large number of patterns prepared according to various materials and patterns formed in the IC chip, and it is better to form the TEG in the scribe line 1 in consideration of the efficient arrangement of the chips. Although they may be arranged in the IC formation region, there is a problem that the chip size becomes large.

When exposing with a stepper, a reticle is used. In this reticle, TE for checking an element in one IC with respect to one IC is used.
G may be arranged on the scribe line 1. However, as shown in FIG. 10, a TE that can collectively check a plurality of (four) ICs for a plurality of IC chips S, T, U, and V.
G may be arranged. In other words, in the former, a group of TEGs is formed for one IC, but in the latter, a group of TEGs is formed for a plurality of ICs. Has the merit that another TEG, alignment mark, alignment mark of scribe line and the like can be arranged.

The surrounding IC adjacent to the TEG is:
It is considered that the formation conditions are substantially the same as those of the TEG. Therefore, when one reticle is formed by four ICs (S, T, U, V), if it is formed on a central cross-shaped scribe line,
Ample room can be provided, many TEGs can be formed, and deep analysis is possible. FIG. 1 shows TEGs A to H, which are formed in a scribe line 1. However, if the increase in the chip area is ignored, it may be formed in the IC formation region. Here, the size from left B to right H is about 150 μm in width and about 1.5 m in height.
m or more.

Next, the TEG will be described.
A TEG in which the structure shown in FIG. 3 is formed and arranged is used to analyze the coverage of a jacket formed in an upper layer in which a wiring having a minimum line width and a minimum space is formed in an insulating film. . The TEGs of B and C are for examining the shape of the minimum contact hole 6 exposing the diffusion region 5 as shown in FIG. 4, where B is the N + diffusion region exposed from the contact hole and C is the P + diffusion region. It is exposed.

As shown in FIG. 5, the TEG of D is located at the valley of the interlayer insulating film 7 and has the shape of the second-layer contact 8 exposing the first-layer M and the metal wiring M contacting it. This is to check the coverage. Hereinafter, the expression of peaks and valleys will be used. In this case, the wiring also has a swell in the interlayer insulating film. Although it should have actually been shown in the drawing, it was flattened for the convenience of the drawing.

The TEG of E is, as shown in FIG. 6, the contact hole 9 having the minimum shape exposing the poly-Si gate GP, the coverage of the second-layer metal wiring SM, and the valley of the second-layer metal wiring SM. This is for observing the shape of the contact hole where the place is exposed. As shown in FIG. 7, the TEG of F examines the coverage of the minimum shape of the contact hole 11 exposing the first-layer metal wiring M arranged in the mountain portion and the coverage of the third-layer metal wiring TM. Things.

As shown in FIG. 8, the TEG of G is for observing the contact hole 12 having the minimum shape exposing the metal wiring SM of the second layer located at the peak. Finally, the TEG of H is a contact hole of the largest groove as shown in FIG. 9, and in particular, the diffusion region 13, the poly-Si gate GP, the first
The contact holes 14 to 17 exposing the metal wiring M of the layer and the metal wiring SM of the second layer are observed and examined.

These TEGs are arranged as shown in FIG. 1 as described above, and all the conductive materials GP, M, SM, TM, wirings, gate electrodes, W A plug or the like is provided on the GND of the semiconductor substrate. In this case, depending on the pattern shape, a floating conductive material is provided and charged up.
Therefore, even if it is divided for analysis, no charge is released, and it cannot be observed with an electron microscope. Therefore, all of the electric charges fall to GND at the ground regions 20 and 21.

When only one grounding region 20 is grounded and the other grounding region 21 is omitted, and divided by the arrow Z to the left and right with respect to the paper, the TEG located above the arrow Z is dropped to ground. Although it can be seen with an electron microscope, the TEG located below becomes floating and charges up,
I can't peep. Therefore, it is preferable to form the ground regions on both sides.

The upper part of FIG. 2 is an enlarged view of the grounding region 20, and the middle part is an enlarged view of a portion surrounded by an ellipse. The lower diagram is a cross-sectional view taken along line AA of the middle diagram.
Here, they are shown together in FIG. 2 for understanding. Details will be described later. The TEG shown in FIG. 3A is such that the P + diffusion region 22 surrounded by the LOCOS film has a poly-Si gate GP having a minimum line width (0.4 μm as an example here) and a minimum interval (0.5 μm as an example) of about 2500 °. It is formed with a film thickness. Here, GP is made of poly-Si in the lower layer and WSi in the upper layer.
Are laminated one body. And on top of this, BPS
The G film is covered by about 6000 °, and a first-layer metal wiring M is disposed thereon with a line width of about 0.6 μm and an interval of about 0.6 μm. The wiring M is a laminate of Ti, TiN, and Al as main materials, and is formed at about 8000 °. To cover these, a second interlayer insulating film 24 is laminated at about 10,000 °. The insulating film 24 is formed by laminating a TEOS film and a glass film several times. Furthermore, there is a second-layer metal wiring SM on this, which is a laminate of Ti, TiN, and Al as main materials and is formed at about 8000 °. The third interlayer insulating film 25 is formed by laminating a TEOS film and a glass film several times as described above. After all 10,000 yen
It is about. Further, as the third-layer metal wiring TM,
A laminate of Ti, TiN and Al as main materials, formed at about 8000 °, and a fourth insulating film 26
As a jacket, SiO2 film and Si3N4 film are about 100
It is covered by about 00 °. GP ~ TM shown here
Extends in a direction perpendicular to the paper surface, and extends about 1.5 mm from the top to the bottom of the solid-line rectangular area as shown in FIG.

Accordingly, if the wiring is divided right and left somewhere in FIG. 1, it is possible to analyze the coverage formation state of the wiring, the interlayer insulating film, the jacket formed on the upper layer and the like. Next, FIG. 4 will be described. Hereinafter, the same material as in FIG. FIG.
The difference is that the long hole is not analyzed, but the contact hole 6 is analyzed, and the W plug 27 is embedded from the valley of the BPSG film 23 to the diffusion region via the barrier metal of Ti and TiN. That is.

Here, as can be said for the entire embodiment, the W plug is embedded in the contact hole of the portion painted black in the drawing via the barrier metal. The point of the present invention lies in the shape of the contact hole 6. That is, the contact rows 30, 31, 3 surrounded by dotted lines
2 are formed in the same pattern, for example, FIG.
It is formed in the TEG of FIG. The two contact holes 33 below each contact row are the smallest size contact holes actually formed in the IC chip.
As described in the conventional example, the W plug embedded in this contact hole does not easily break into two,
Its size was elongated to make it easy to break. For example, the size of the contact hole 33 is 0.5 × 0.5 μm
Then, the width of the contact hole 34 is set to be the same, and the height is set to be twice or more, here, about 1.5 μm. as a result,
If the breaking point comes to the center of the contact hole 34,
It can be broken and observation is possible. However, actually, since the size is small, for example, two or more
They are arranged at intervals.

If there is only one contact row, the contact holes 34 may be divided between the contact holes 34, so that W cannot be divided. It is shifted at a pitch of 0.6 μm. The shift amount X is X> (contact hole 34 + shift pitch) / contact hole 3
It is considered to be about four. That is, the contact hole 34 in FIG. 4 is broken somewhere between the arrows K and L because of the shift amount.

In the figure, there are only two contact holes 34, but actually, many contact holes 34 are formed over a length of 1.5 mm in FIG. For example, if the contact hole 34 is 1000
The contact holes 33 are formed above and below this group, respectively. The contact hole 33 here is a monitor of the actual planar shape of the contact hole, and the number may be small.

On the other hand, what is actually desired to be examined is the contact hole 33, but the condition formed at least along the lateral side of the contact hole 34 is substantially the same as that formed along the lateral side of the contact hole 33. It is considered the same. On the other hand, the formation state of the contact hole 33 along the vertical side direction is different in the contact hole 34 in size, and it cannot be said that the formation state is the same.

Therefore, this pattern is formed by rotating it by 90 degrees. Here, it is formed on TEG3 in FIG. In other words, since the TEG 3 is broken in the vertical direction with respect to the plane of the paper, the situation is the same as that in FIG. That is, when observing the state of the contact hole 33 in the contact hole 34 of FIG. 4, if the TEG rotated 90 degrees is formed on each of the vertical scribe line and the horizontal scribe line as shown in FIG. The shape of the entire contact hole 33, the shape of the electrode therein, and the like can be estimated.

Next, FIG. 5 will be described. The analysis of the contact hole 8 is performed in the same manner as in FIG.
And a W plug 27 is embedded via a barrier metal such as Ti or TiN. Then, the shape of the contact 8 of the second layer and the coverage of the metal wiring M contacting it are examined. In the contact rows 40, 41, and 42, a contact hole 43 having the same shape as the shape that actually enters the IC and a contact hole 44 having a longer vertical length are formed, and are arranged so as to deviate from each row as in FIG. The shift pitch is calculated by the above-described formula, and is 0.6 μm here.

Since the method of forming the contact row is the same as that of FIGS. 4 and 5, only the sectional structure of FIGS. 6 to 8 is shown. FIG. 6 shows a contact hole 9 having a minimum shape exposing the gate GP.
Coverage of the second-layer metal wiring SM, contact hole 1 exposing the valley of the second-layer metal wiring SM
Observe the shape of 0. FIG. 7 shows the shape of the contact hole 11 having the minimum shape exposing the first-layer metal wiring M disposed in the mountain portion, and the third-layer metal wiring TM.
This is to check the coverage. FIG. 8 is an observation of the contact hole 12 having the minimum shape exposing the metal wiring SM of the second layer located at the mountain portion.

Finally, the TEG of H is a contact hole of the largest groove as shown in FIG.
The contact holes 14 to 17 exposing the i-gate GP, the first-layer metal wiring M, and the second-layer metal wiring SM are observed and examined. These contact holes 14
No. to No. 17 have a contact size of 1 μm × 1 μm,
On the contrary, the W plug may not be embedded well due to the large size. In other words, the formation state of W is examined because the plug is formed or the plug surface becomes concave instead of being substantially flat.

Here, since the size is large, the contact size does not need to be changed vertically and horizontally, and may be changed.
Subsequently, in the upper diagram of FIG. 2, FIG. 3 (TE in FIG.
G) to FIG. 9 (TEG of H in FIG. 1) are formed in the range of the arrow P, and TEGA to H are arranged just like comb teeth from the ground region 20, and TE
The G metal extends from the metal in the ground region 20 like a comb.

The portion surrounded by the ellipse in the upper diagram is the TEG of FIG. 1B, and an enlarged view thereof is shown in the middle diagram. That is, a gate GP hatched at a point is formed in the ground region 20, the GP is exposed in a horizontally long contact hole 60, and is electrically connected to the first-layer metal wiring M by a W plug. . This one-layer metal wiring M is provided over the entire ground region, and each TEG
And is electrically connected to the second-layer metal interconnection SM via a contact hole 62.
The point of the present invention is that the contact hole 61
Is in contact with the diffusion region (GND) of P +. This SM is also arranged in the entire region of the ground region 20 and extends in the longitudinal direction of the TEG as necessary, and
3 and is electrically connected to the third metal wiring TM. This TM is also provided in the entire ground region 20 and extends in the longitudinal direction of the TEG as necessary.

A feature of the present invention is that all the metal formed on the TEG is electrically connected to the GND region of the semiconductor substrate, here the P + diffusion region, for observation with an electron microscope. . Some wirings are connected to GND even in regions other than the ground region. For example, FIG.
However, some of them are not connected to GND and are floating.
D dropped.

Next, an application in an electrically programmable and erasable nonvolatile semiconductor memory device used for a cellular phone, a digital still camera and the like will be described. Here, a split gate type flash EEPROM is used as an example, and FIG. 13 shows a cell formed on a scribe line as a TEG. First, the upper diagram is a schematic cross section, and the lower diagram is a plan view of a memory cell requiring analysis.
On the p-type single crystal semiconductor substrate 101, LOCOSs (not shown) are arranged in a plurality of rows in the vertical direction across the left and right of the lower diagram, and between the LOCOS and the LOCOS, the end portions partially overlap the LOCOS. A floating gate 102 is formed, and a mini-LOCOS 103 is formed on the floating gate 102 to sharpen an end. On top of this, a control gate 10 is interposed via an interlayer insulating film.
4 are formed above and below. The floating gate 102 and the control gate 104 are formed on both sides around the contact 105 marked with “x”. Then, a drain electrode 108 that contacts the drain region 107 via an interlayer insulating film 106 that covers them is formed.
Further, the source electrode 11 that contacts the source region 109
0 is formed. A contact hole exposing the drain electrode 108 is covered with, for example, a laminate 111 of a TEOS film and a glass film as an interlayer insulating film covering them.
105 is formed, and a W plug 112 is formed via the contact hole 105 and a barrier metal formed of Ti and TiN formed around the contact hole 105. And this W
Metal wirings 113 contacting with the plugs 112 are formed on the left and right sides, and a stacked layer 114 of a TEOS film and a glass film is further coated thereon.
Is formed, and finally the jacket 116 is formed.

Here, the control gate 104, the drain electrode 108 , and the source electrode 110 are made of poly-Si and WSi.
Of a laminate. The metal wirings 113 and 115 are
It has the same configuration as M and TM described above. The control gate and the source electrode shown in the plan view are also formed to be long in the vertical direction as shown in FIG. 1, and a plurality of cells shown here are formed up and down (actually, about 1000), Rows are formed, and a plurality of contact rows are formed as shown in FIG. 4, and the respective pitches are shifted from each other.

The contact hole 105 here has a thickness of about 0.5 mm.
With a size of 5 × 2.0 μm, actual contacts are formed above and below the group of contact holes 105 as shown in the lower part of FIG. As described in the previous embodiment, the contact hole 105 is formed to be longer than the actual contact hole, and is formed with a shifted pitch. Is not broken.

The control gate 104, the drain electrode 108, the source electrode 110, the W plug 112, the metal wiring 113 and the metal wiring 115 are connected to GND as shown in FIG. Here, the floating gate 102 is surrounded by a control gate and a source electrode, and since these are grounded to GND, accumulated charges are discharged from this electrode and it is difficult to charge up. Absent.

Alternatively, the drain electrode 108 may be omitted, and a contact hole extending directly from the interlayer insulating film 111 to the drain region may be formed, and W may be embedded therein. The same applies to the source electrode.

[0041]

According to the present invention, when means for fixing the TEG pattern of the wiring to the ground of the semiconductor substrate is provided, the charge up of the TEG pattern can be prevented, and the electron microscope can be used. Is better observed. Efficient arrangement is possible by forming a plurality of TEG patterns of wirings collectively in one area and providing means fixed to the ground of the semiconductor substrate in this area. In particular, since the diffusion regions serving as the GND can be formed as one, the arrangement can be efficiently performed in the IC or in the scribe line.

If the ground region of the semiconductor substrate is electrically connected with the W plug, the TEG pattern can be fixed to GND without providing any additional means. Furthermore, if the TEG pattern of the wiring is fixed to the ground of the semiconductor substrate at both ends of this element, when the TEG is divided into two, both wirings are fixed to GND, and neither of them is charged up. Observable.

[Brief description of the drawings]

FIG. 1 is a view for explaining an embodiment of the present invention and is a view for explaining an arrangement of TEGs formed on scribe lines.

FIG. 2 is a diagram illustrating a part, enlargement, and section of FIG. 1;

FIG. 3 is a diagram illustrating TEG (A) in FIG. 1;

FIG. 4 is a diagram illustrating TEGs (B, C) in FIG. 1;

FIG. 5 is a diagram illustrating TEG (D) in FIG. 1;

FIG. 6 is a diagram illustrating TEG (E) in FIG. 1;

FIG. 7 is a diagram illustrating TEG (F) in FIG. 1;

FIG. 8 is a diagram illustrating TEG (G) in FIG. 1;

FIG. 9 is a diagram illustrating TEG (H) in FIG. 1;

FIG. 10 is a diagram for explaining a TEG arrangement on a scribe line.

FIG. 11 is a diagram illustrating a semiconductor element formed in an IC formation region of a wafer.

FIG. 12 is a diagram illustrating a problem that occurs due to a conventional TEG.

FIG. 13 is an explanatory diagram in the case where the nonvolatile semiconductor memory device is a TEG.

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/66

Claims (3)

(57) [Claims] A plurality of IC forming regions; and a plurality of ICs.
A scribe line provided between the formation areas ,
A semiconductor wafer having a TEG pattern on a part of the scribe line or the IC forming region, in the semiconductor device in which is divided into individual IC chips through the scribing line forming region is divided into the IC chip Before the IC formation area
Are a gate electrode, a first-layer wiring, a second
The wiring of the layer and the wiring of the third layer are provided, and the TEG pattern before being divided into the IC chips is
In the formation region, the gate electrode, the first layer wiring,
Corresponding to the second layer wiring and the third layer wiring
The TEG pattern made of the same material
Are, and the semiconductor substrate positioned at both ends of the TEG pattern
Is provided with a ground area , and at least the ground is provided at both ends of the TEG pattern.
The tungsten plug in contact with the region is electrically
It is fixed to the land and constitutes the TEG pattern.
The gate electrode, the first layer wiring, and the second layer
Wiring and the third layer wiring are tungsten plugs.
When the TEG pattern is observed, the TEG pattern is electrically fixed to the ground through the TEG pattern.
That a mechanism to prevent charge-up of
Characteristic semiconductor device. 2. The method according to claim 1, wherein both ends of the TEG pattern are
Between the gate electrode and the wiring of the first layer,
Between the wiring and the wiring of the second layer, and between the wiring
Between the third wiring and the third wiring,
A tungsten plug for electrical connection is provided, and the first-layer wiring pattern and the ground region are
Be fixed to ground via a tungsten plug
The semiconductor device according to claim 1, wherein: 3. A plurality of IC formation areas and said plurality of ICs
A scribe line provided between the formation areas ,
A semiconductor wafer having a TEG pattern on a part of the scribe line or the IC forming region, in the semiconductor device in which is divided into individual IC chips through the scribing line forming region is divided into the IC chip Before the IC formation area
Is the floating gate, the floating gate
The control gate, which is arranged to overlap on the above,
The floating gate and the control gate
A source electrode and a drain electrode provided so as to sandwich the
Disposed above the source electrode and the drain electrode
A first wiring, and a first wiring provided on the first wiring.
Nonvolatile semiconductor memory device having at least two wirings
Of the TEG pattern before being divided into the IC chips.
In the formation area, the floating gate and the controller
A roll gate, the source electrode, the drain electrode,
In a layer corresponding to the first wiring and the second wiring
The TEG pattern made of the same material is provided , and at least the ground is provided at both ends of the TEG pattern.
The tungsten plug in electrical contact with the region
TEG pattern fixed to the ground
The control gate and the source electrode.
Pole, the drain electrode, the first wiring, and the
2 wiring is electrically grounded through a tungsten plug
When the TEG pattern is observed, the TEG pattern is fixed.
That a mechanism to prevent charge-up of
Characteristic semiconductor device.