CN111354699B - Semiconductor device with a plurality of semiconductor chips - Google Patents
Semiconductor device with a plurality of semiconductor chips Download PDFInfo
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- CN111354699B CN111354699B CN201811580640.9A CN201811580640A CN111354699B CN 111354699 B CN111354699 B CN 111354699B CN 201811580640 A CN201811580640 A CN 201811580640A CN 111354699 B CN111354699 B CN 111354699B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
An embodiment of the invention provides a semiconductor device, which includes a first pad and a second pad, a first conductive connector and a second conductive connector, a first conductive structure and a second conductive structure. The first conductive connecting piece and the second conductive connecting piece are positioned above the first connecting pad and the second connecting pad. The first conductive structure is electrically connected with the first pad and the first conductive connecting piece, and comprises a first conductive part, a second conductive part positioned on the first conductive part and a connecting part for connecting the first conductive part and the second conductive part, wherein the first conductive part and the second conductive part are staggered in the horizontal direction, and the first conductive part, the connecting part and the second conductive part are integrally formed. The second conductive structure is electrically connected to the second pad and the second conductive connecting member, wherein in the vertical direction, a portion of the second conductive structure overlaps the first conductive structure below the second conductive structure.
Description
Technical Field
The present invention relates to a semiconductor device.
Background
Although the number of solder balls that can be placed on a Chip can be increased by Wafer Level Chip Scale Package (WLCSP) technology, it involves complicated manufacturing, resulting in an increase in the manufacturing cost of semiconductor devices.
Disclosure of Invention
The invention provides a semiconductor element, which can maximize the number of conductive connecting pieces which can be placed on the surface of the semiconductor element.
The semiconductor element comprises a first connecting pad, a second connecting pad, a first conductive connecting piece, a second conductive connecting piece, a first conductive structure and a second conductive structure. The first conductive connecting piece and the second conductive connecting piece are positioned above the first connecting pad and the second connecting pad. The first conductive structure is electrically connected with the first pad and the first conductive connecting piece, and comprises a first conductive part, a second conductive part positioned on the first conductive part and a connecting part for connecting the first conductive part and the second conductive part, wherein the first conductive part and the second conductive part are staggered in the horizontal direction, and the first conductive part, the connecting part and the second conductive part are integrally formed. The second conductive structure is electrically connected to the second pad and the second conductive connecting member, wherein in the vertical direction, a portion of the second conductive structure overlaps the first conductive structure below the second conductive structure.
In some embodiments of the invention, the first conductive connecting element and the first pad are staggered in a horizontal direction.
In some embodiments of the present invention, the first conductive structure directly contacts the first pad and the first conductive connecting element.
In some embodiments of the present invention, the semiconductor device further includes a first dielectric layer including a first block, a second block having a top surface higher than the first block, and a slope block connecting the first block and the second block, wherein the first conductive portion, the connecting portion, and the second conductive portion are respectively disposed on the first block, the slope block, and the second block.
In some embodiments of the present invention, the semiconductor device further comprises a second dielectric layer covering the first conductive structure, the second conductive structure being formed on the second dielectric layer, wherein the second dielectric layer is substantially coplanar with a top surface of the first dielectric layer.
In some embodiments of the invention, the first dielectric layer further includes an opening exposing the first pad, and the first conductive structure is electrically connected to the first pad through the opening.
In some embodiments of the present invention, the electronic device further includes a second dielectric layer disposed between the first conductive structure and the second conductive structure, wherein the second dielectric layer includes an opening exposing the first conductive structure, and the first conductive structure is electrically connected to the first conductive connecting element through the opening.
In some embodiments of the invention, the portion of the second conductive structure is located between the first conductive portion and the second conductive portion in the vertical direction.
In some embodiments of the present invention, the second conductive structure further comprises a via located on a portion of the second conductive structure, the via being in direct contact with the portion of the second conductive structure.
In some embodiments of the present invention, a third conductive structure is further included, wherein a portion of the second conductive structure is located between the top surface and the bottom surface of the third conductive structure, and the third conductive structure overlaps, in the vertical direction, a portion of the second conductive structure below the third conductive structure.
In view of the above, the semiconductor device of the embodiment of the invention includes a conductive structure, which is buried in a dielectric layer between the pad and a conductive connecting element such as a solder ball, so as to electrically connect the pad and the conductive connecting element. That is, the conductive structure does not occupy the surface area of the wafer, so that the number of conductive connectors that can be arranged on the surface of the wafer can be maximized.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to 1J are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to some embodiments of the invention.
Fig. 2 is a schematic top view of a semiconductor device according to some embodiments of the invention.
[ notation ] to show
100: wafer with a plurality of chips
102: dielectric layer
102a, 122a, 140a, 160a, 180 a: opening of the container
110': connecting pad
110A: first pad
110B: second pad
110C: third connecting pad
120: a first dielectric layer
122: first block
124: second block
126: slope block
130: first conductive structure
132: first conductive part
134: second conductive part
136: connecting part
140: a second dielectric layer
142. 162, 164: block
150: second conductive structure
152: conductive part
154: through hole
160: a third dielectric layer
170: third conductive structure
180: a fourth dielectric layer
180 b: contact window opening
182: contact window
190': conductive connecting piece
190A: first conductive connecting piece
190B: second conductive connecting piece
190C: third conductive connecting member
Detailed Description
Fig. 1A to 1J are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to some embodiments of the invention. It is particularly noted that fig. 1A to 1J only show a portion of the upper surface of the wafer for convenience of illustration, and the sizes and numbers of the components shown in the drawings are only for illustrative purposes, and are not actual sizes or intended to limit the present invention.
Referring to fig. 1A, first, a chip 100 is provided, wherein the chip 100 has first to third pads 110A, 110B and 110C on a surface thereof. In the present embodiment, the surface of the chip 100 is further provided with pads 110'. Specifically, in the embodiment, two types of pads are disposed on the chip 100, the first type of pad is horizontally offset from the conductive connection member connected thereto, so that the conductive structure designed in the present invention is required to connect the two types of pads, which include the first to third pads 110A, 110B, and 110C, for example. The second type of pad is electrically connected to the conductive connecting element above the second type of pad through a common contact window, so that the second type of pad overlaps the conductive connecting element connected to the second type of pad in a vertical direction, and the second type of pad includes a pad 110', for example. In the present embodiment, the chip 100 includes, for example, a substrate (not shown) and a circuit structure (not shown) on the substrate, the circuit structure includes, for example, a plurality of dielectric layers and a plurality of conductive layers overlapped with each other, wherein the circuit structure is, for example, electrically connected to the first to third pads 110A, 110B, 110C and the pad 110'. In addition, in an embodiment, the wafer 100 may further include a component disposed in or on the substrate, where the component may be a transistor, a diode, a capacitor, a resistor, or the like. In the embodiment, the first to third pads 110A, 110B, 110C and the pad 110' are disposed in the dielectric layer 102 on the chip 100, for example. That is, the dielectric layer 102 is formed on the first to third pads 110A, 110B, 110C and the pad 110 ', and the dielectric layer 102 includes an opening 102a exposing the first to third pads 110A, 110B, 110C and the pad 110', respectively. In the present embodiment, the top surfaces of the first to third pads 110A, 110B, 110C and the pad 110' are substantially coplanar. In the embodiment, the distances between the first to third pads 110A, 110B, 110C and the pad 110' are the same, but the invention is not limited thereto. That is, in other embodiments, the distances between the first to third pads 110A, 110B, 110C and the pad 110' may be different. Particularly, although 3 first-type pads (i.e., the first to third pads 110A, 110B, and 110C) and 1 second-type pad (i.e., the pad 110') are disposed on the chip 100 in the embodiment, the invention is not limited thereto, and in other embodiments, 2 or more than 3 first-type pads and no more than 1 second-type pad may be disposed on the chip 100. In addition, although the present embodiment is described by taking an example in which the conductive member is formed on the wafer, the present invention is not limited thereto, and in other embodiments, the conductive member may be applied to other semiconductor elements than the wafer such as a chip.
Referring to fig. 1B, a first dielectric layer 120 is formed on the wafer 100. In the present embodiment, the first dielectric layer 120 is formed on the dielectric layer 102, for example. The first dielectric layer 120 includes, for example, a first block 122, a second block 124 having a top surface higher than the first block 122, and a slope block 126 connecting the first block 122 and the second block 124. The first block 122 and the second block 124 have flat top surfaces, respectively, and the top surface of the slope block 126 gradually decreases from the height of the second block 124 to the height of the first block 122. In the present embodiment, the height of the first block 122 is equal to or greater than 4 μm, for example, and the height of the second block 124 is equal to or greater than 12 μm, for example. The ratio of the height of the second block 124 to the height of the first block 122 is, for example, 3: 1. The angle between the top surface of the ramp block 126 and the top surface of the first block 122 is, for example, less than or equal to 90 degrees. In the present embodiment, the width of the first block 122 is similar to the width of a conductive connection to be formed later, for example. The first block 122 includes an opening 122a exposing the first pad 110A, for example. In the present embodiment, the edge of the opening 122a is aligned with the edge of the opening 102a, for example, but the invention is not limited thereto. In other embodiments, the first dielectric layer 120 may fill a portion of the opening 102a to cover a portion of the first pad 110A or expose the first dielectric layer 120 beside the first pad 110A.
In the present embodiment, the first dielectric layer 120 is formed by 3D printing, for example, and the printing direction is along the direction from the first pads 110A to the third pads 110C. That is, for example, the second block 124, the slope block 126 and the first block 122 are sequentially formed. The printing ink used is, for example, insulating and viscous. Of course, in other embodiments, there may be other printing directions, or the first dielectric layer 120 may be formed by other suitable methods. In the present embodiment, the material of the first dielectric layer 120 may include a generally common dielectric material (such as silicon nitride, silicon oxide, silicon oxynitride), a low-k dielectric material, an organic material (such as benzocyclobutene (BCB), Polyimide (PI), Polybenzoxazole (PBO)), and other insulating materials.
Referring to fig. 1C, a first conductive structure 130 is then formed on the first dielectric layer 120. The first conductive structure 130 includes a first conductive portion 132, a second conductive portion 134 on the first conductive portion 132, and a connection portion 136 between the first conductive portion 132 and the second conductive portion 134, wherein the first conductive portion 132, the connection portion 136, and the second conductive portion 134 are integrally formed. In the present invention, "integrally formed" means that members connected to each other are continuously formed in the same material in the same manufacturing. For example, in the present embodiment, the first conductive portion 132, the connecting portion 136 and the second conductive portion 134 are continuously formed, so that the first conductive structure 130 is integrally formed. In the present embodiment, the first conductive portion 132, the connecting portion 136 and the second conductive portion 134 are respectively disposed on the first block 122, the slope block 126 and the second block 124 and are directly contacted with the first block 122, the slope block 126 and the second block 124, for example. In the embodiment, the first conductive portion 132 horizontally extends on the first block 122 and fills the opening 122a to electrically connect with the first pad 110A. The connecting portion 136 extends over the slope block 126, for example, in a sloping manner. In the present embodiment, the second conductive portion 134 extends horizontally on the second block 124, for example. A gap is formed between the exposed end of the first conductive portion 132 and the edge of the first block 122, and a gap is formed between the exposed end of the second conductive portion 134 and the edge of the second block 124. That is, the first conductive structures 130 do not cover opposite edges of the first dielectric layer 120. In this way, the exposed end of the first conductive portion 132 can be covered by the second dielectric layer 140 formed subsequently to avoid being exposed to the outside, and the exposed end of the second conductive portion 134 can be prevented from being electrically connected to the second pad 110B.
In the present embodiment, the first conductive structure 130 is formed by 3D printing, for example, and the printing direction is along the direction from the second block 124 to the first block 122. That is, for example, the second conductive portion 134, the connection portion 136, and the first conductive portion 132 are sequentially formed. Wherein the printing ink used is, for example, a conductive ink. Furthermore, the connecting portion 136 can be formed on the slope block 126 uniformly, easily and completely in thickness by means of 3D printing, so that the occurrence of wire breakage can be avoided. In addition, since the first conductive portion 132 is formed by 3D printing, even if the first conductive portion 132 is partially filled in the opening 122a, the first conductive portion 132 can have a substantially flat surface without having a slightly concave shape corresponding to the opening 122 a. Furthermore, compared to conventional fabrication in which bonding pads are formed on the entire surface of the chip, 3D printing can form the second conductive portions 134, which are subsequently used as bonding pads, respectively, so that the second conductive portions 134, such as bonding pads, can be formed or repaired, respectively. Of course, in other embodiments, the first conductive structure 130 may be formed by other suitable methods. In the present embodiment, the material of the first conductive structure 130 may include a metal material such as aluminum, silver, copper, and the like. In the present embodiment, the thickness of the first conductive structure 130 is, for example, equal to or greater than 1 μm.
Referring to fig. 1D, a second dielectric layer 140 is formed on the first conductive structure 130 to cover the first conductive structure 130. In the present embodiment, the uppermost surface of the second dielectric layer 140 is, for example, flush with the uppermost surface of the first dielectric layer 120. In the present embodiment, the second dielectric layer 140 includes a block 142 having a height between the first block 122 and the second block 124. The block 142 has a flat top surface, for example. In addition, the second dielectric layer 140 includes an opening 140a exposing the first conductive structure 130, for example. In the present embodiment, the second dielectric layer 140 covers the first conductive structure 130, i.e., covers the opposite exposed ends of the first conductive structure 130 (i.e., covers the exposed end of the first conductive portion 132 and the exposed end of the second conductive portion 134), except that the opening 140a exposes a portion of the first conductive structure 130. As such, the first conductive structure 130 is, for example, embedded in the first dielectric layer 120 and the second dielectric layer 140, and is electrically insulated from the second pad 110B. In addition, in the present embodiment, the second dielectric layer 140 covers at least one of the opposite edges of the first dielectric layer 120, for example. In the present embodiment, the material and the forming method of the second dielectric layer 140 can be as described above with respect to the first dielectric layer 120, and the material and the forming method of the second dielectric layer 140 can be the same as or different from those of the first dielectric layer 120. In the present embodiment, the second dielectric layer 140 is formed by, for example, 3D printing, and the details thereof can be referred to the above description, which is not repeated herein.
Referring to fig. 1E, a conductive portion 152 is then formed on the second dielectric layer 140. In the embodiment, the conductive portion 152 is disposed on the block 142 and fills the opening 102a to electrically connect with the second pad 110B. In the present embodiment, the conductive portion 152 extends through the opening 102a and bridges the dielectric layer 102 but is insulated from the third pad 110C. In the present embodiment, in the vertical direction, the conductive portion 152 is located between the first conductive portion 132 and the second conductive portion 134, and the conductive portion 152 overlaps with the first conductive portion 132 therebelow. In the present embodiment, the material and the forming method of the conductive portion 152 may refer to those described above with respect to the first conductive structure 130, and the material and the forming method of the conductive portion 152 may be the same as or different from those of the first conductive structure 130. In the present embodiment, the conductive portion 152 is formed by 3D printing, for example, and the details thereof can be referred to the above description, which is not repeated herein.
Referring to fig. 1F, a third dielectric layer 160 is formed on the conductive portion 152 and the second dielectric layer 140, wherein the third dielectric layer 160 has an opening 160a exposing the lower conductive structure (i.e., the conductive portion 152). In the present embodiment, the third dielectric layer 160 includes a block 162 and a block 164 having a height difference, and the opening 160a is formed between the block 162 and the block 164. In the present embodiment, the block 162 is lower than the block 164, and the top surface of the block 164 (i.e., the uppermost surface of the third dielectric layer 160) is coplanar with the uppermost surface of the second dielectric layer 140. In the present embodiment, the material and the forming method of the third dielectric layer 160 can be as described above with respect to the first dielectric layer 120, and the material and the forming method of the third dielectric layer 160 can be the same as or different from those of the first dielectric layer 120. In the present embodiment, the third dielectric layer 160 is formed by, for example, 3D printing, and the details thereof can be referred to the above description, which is not repeated herein.
Referring to fig. 1G, a via 154 is then formed in the opening 160a to electrically connect to the conductive portion 152. In the present embodiment, the top surface of the via 154 is coplanar with the top surface of the second conductive portion 134, for example. The conductive portion 152 and the via 154 form a second conductive structure 150, and an uppermost top surface of the second conductive structure 150 is, for example, coplanar with an uppermost top surface of the first conductive structure 130. In the present embodiment, since the conductive portion 152 and the through hole 154 may be formed by a 3D printing method and may be made of the same material, for example, there is substantially no junction between the conductive portion 152 and the through hole 154. In the present embodiment, the second conductive structure 150 is, for example, embedded in the second dielectric layer 140 and the third dielectric layer 160, and is electrically insulated from the first conductive structure 130 and the first pad 110A. In the present embodiment, the through-hole 154 is formed by, for example, 3D printing. Wherein the material of the via 154 and the conductive portion 152 may be the same or different.
Next, a third conductive structure 170 is formed on the third dielectric layer 160. In the embodiment, the third conductive structure 170 is formed on the block 162 and filled in the opening 102a to electrically connect with the third pad 110C. In the present embodiment, the third conductive structure 170 is separated from the via 154 to avoid electrical connection with the second conductive structure 150. Furthermore, the third conductive structure 170 extends from the block 162 through the opening 102a and bridges over the dielectric layer 102. In the present embodiment, the third conductive structure 170 overlaps the second conductive structure 150 therebelow in the vertical direction. In the present embodiment, the material and the forming method of the third conductive structure 170 may be as described above with reference to the first conductive structure 130, and the material and the forming method of the third conductive structure 170 may be the same as or different from those of the first conductive structure 130 and the second conductive structure 150. In the present embodiment, the third conductive structure 170 is formed by, for example, a 3D printing method, and details thereof can be referred to the foregoing description, which is not repeated herein. In this embodiment, the via 154 and the third conductive structure 170 can be completed in the same step.
Referring to fig. 1H, a fourth dielectric layer 180 is then formed on the third conductive structure 170, wherein an opening 180a is formed between the fourth dielectric layer 180 and the third dielectric layer 160 to expose the top of the second conductive structure 150. Note that in the present embodiment, the sidewall of the block 164 serves as both the sidewall of the opening 180a and the sidewall of the opening 160a, so the sidewall of the opening 180a is substantially aligned with the sidewall of the opening 160 a. In the present embodiment, the top surface of the fourth dielectric layer 180 is, for example, flush with the uppermost top surface of the third dielectric layer 160. In the present embodiment, the fourth dielectric layer 180 covers the exposed dielectric layer 102, for example. In the present embodiment, the material and the forming method of the fourth dielectric layer 180 may refer to those described above with respect to the first dielectric layer 120, and the material and the forming method of the fourth dielectric layer 180 may be the same as or different from those of the first to third dielectric layers 120, 140, 160. In the present embodiment, the fourth dielectric layer 180 is formed by, for example, 3D printing, and the details thereof can be referred to the above description, which is not repeated herein. In the present embodiment, the third conductive structure 170 is, for example, embedded in the third dielectric layer 160 and the fourth dielectric layer 180, and is electrically insulated from the second conductive structure 150 and the second pad 110B. In the present embodiment, the fourth dielectric layer 180 further includes a contact opening 180b, for example, and the contact opening 180b exposes the pad 110' thereunder. Specifically, the contact opening 180b penetrates through the fourth dielectric layer 180 and is located right above the pad 110'.
Referring to fig. 1I, a contact 182 is formed in the contact opening 180 b. In the present embodiment, the contact windows 182 are formed by 3D printing, for example, but in other embodiments, the contact windows 182 may be formed by other suitable methods.
Referring to fig. 1J and fig. 2, first to third conductive connecting members 190A, 190B, and 190C are formed in the openings 140A, 160A, and 180A, respectively. In this embodiment, forming a conductive connection 190' in the contact opening 180b is further included. In the present invention, a "conductive connector" is a connector for electrically connecting a semiconductor component such as a wafer or a chip with another semiconductor element (such as a circuit board or another wafer or chip). The first to third conductive connecting members 190A, 190B and 190C are electrically connected to the first to third pads 110A, 110B and 110C through the first to third conductive structures 130, 150 and 170, respectively. In the present embodiment, the first to third conductive connecting elements 190A, 190B and 190C are, for example, the first to third pads 110A, 110B and 110C electrically connected to the first to third conductive connecting elements, respectively, are staggered in the horizontal direction. In the embodiment, it is exemplified that the first to third conductive connectors 190A, 190B, 190C and the first to third pads 110A, 110B, 110C are not overlapped at all in the horizontal direction, but the invention is not limited thereto, and in other embodiments, the first to third conductive connectors 190A, 190B, 190C and the first to third pads 110A, 110B, 110C may be overlapped partially or not overlapped partially in the horizontal direction. In the embodiment, the first to third conductive structures 130, 150, and 170 respectively extend between the first to third pads 110A, 110B, and 110C and the first to third conductive connecting elements 190A, 190B, and 190C, and are, for example, in physical contact with the first to third pads 110A, 110B, and 110C and the first to third conductive connecting elements 190A, 190B, and 190C, respectively. In the embodiment, the conductive connection 190 ' is directly above the pad 110 ' and vertically overlaps the pad 110 '. In the embodiment, the first to third conductive connecting members 190A, 190B, 190C and the conductive connecting member 190 'are arranged in an array, for example, and the distances between two adjacent ones of the first to third conductive connecting members 190A, 190B, 190C and the conductive connecting member 190' are substantially the same, for example.
In the present embodiment, the first to fourth dielectric layers 120, 140, 160, 180 have substantially coplanar top surfaces, for example, so as to provide substantially flat surfaces for facilitating the formation of the first to third conductive connectors 190A, 190B, 190C and the conductive connector 190'. In the present embodiment, the first to third conductive connecting elements 190A, 190B, 190C and the conductive connecting element 190' are conductive balls such as solder balls, and the forming method thereof is, for example, screen printing, but the invention is not limited thereto. For example, in other embodiments, the first to third conductive connecting members 190A, 190B, 190C and the conductive connecting member 190' may also be suitable conductive connecting members such as conductive posts.
In the above-mentioned manufacturing, in the present embodiment, a foundation dielectric layer (such as the first dielectric layer 120) with a height difference is first fabricated, and then the conductive structures (such as the first to third conductive structures 130, 150, 170) and the dielectric layers (such as the second to fourth dielectric layers 140, 160, 180) are sequentially overlapped on the foundation dielectric layer. The conductive structure is manufactured in a manner that the bonding pad extends on the dielectric layer in the direction towards the conductive connecting piece and is overlapped with the conductive structure below the bonding pad in the vertical direction, and the dielectric layer covers the whole conductive structure but exposes the top surface of the conductive structure, so that the conductive structure is embedded in the two adjacent dielectric layers. It should be noted that although the embodiment is exemplified by fabricating a three-layer conductive structure, the invention is not limited thereto, and in other embodiments, more conductive structures, such as 4 to 6 layers of conductive structures, may be fabricated. Furthermore, since the plurality of dielectric layers may all be formed by 3D printing and may be made of the same material, for example, there is substantially no junction between adjacent dielectric layers.
In summary, since the conductive structure can be formed by a simple method such as 3D printing without using a mask or complicated manufacturing, the manufacturing method of the semiconductor device has a simple process, thereby further shortening the manufacturing time and reducing the manufacturing cost of the semiconductor device.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (9)
1. A semiconductor component, comprising:
a first pad and a second pad;
the first conductive connecting piece and the second conductive connecting piece are positioned above the first connecting pad and the second connecting pad;
a first conductive structure electrically connecting the first pad and the first conductive connector, the first conductive structure including a first conductive portion, a second conductive portion located on the first conductive portion, and a connecting portion connecting the first conductive portion and the second conductive portion, wherein the first conductive portion and the second conductive portion are staggered in a horizontal direction, and the first conductive portion, the connecting portion, and the second conductive portion are integrally formed;
a first dielectric layer including a first block, a second block having a top surface higher than the first block, and a slope block connecting the first block and the second block, wherein the first conductive portion, the connection portion, and the second conductive portion are disposed on the first block, the slope block, and the second block, respectively; and
and a second conductive structure electrically connecting the second pad and the second conductive connecting member, wherein a portion of the second conductive structure overlaps the first conductive structure thereunder in a vertical direction.
2. The semiconductor device as claimed in claim 1, wherein the first conductive connecting member is offset from the first pad in a horizontal direction.
3. The semiconductor device as defined in claim 1, wherein the first conductive structure directly contacts the first pad and the first conductive connection.
4. The semiconductor component of claim 1, further comprising a second dielectric layer overlying the first conductive structure, the second conductive structure being formed on the second dielectric layer, wherein the second dielectric layer is substantially coplanar with a top surface of the first dielectric layer.
5. The semiconductor device as claimed in claim 1, wherein the first dielectric layer further comprises an opening exposing the first pad, and the first conductive structure is electrically connected to the first pad through the opening.
6. The semiconductor device as claimed in claim 1, further comprising a second dielectric layer disposed between the first conductive structure and the second conductive structure, wherein the second dielectric layer includes an opening exposing the first conductive structure, and the first conductive structure is electrically connected to the first conductive connecting member through the opening.
7. The semiconductor element according to claim 1, wherein the portion of the second conductive structure is located between the first conductive portion and the second conductive portion in a vertical direction.
8. The semiconductor element of claim 7, wherein the second conductive structure further comprises a via located on the portion of the second conductive structure, the via being in direct contact with the portion of the second conductive structure.
9. The semiconductor element of claim 1, further comprising a third conductive structure, wherein the portion of the second conductive structure is located between a top surface and a bottom surface of the third conductive structure, and the third conductive structure overlaps the portion of the second conductive structure below it in a vertical direction.
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| CN201811580640.9A CN111354699B (en) | 2018-12-24 | 2018-12-24 | Semiconductor device with a plurality of semiconductor chips |
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| JP2009076530A (en) * | 2007-09-19 | 2009-04-09 | Seiko Epson Corp | Method of forming wiring pattern |
| US9859256B1 (en) * | 2016-10-26 | 2018-01-02 | Stmicroelectronics S.R.L. | Ink printed wire bonding |
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| KR100997787B1 (en) * | 2008-06-30 | 2010-12-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package and method of manufacturing the same |
| JP2011009653A (en) * | 2009-06-29 | 2011-01-13 | Seiko Epson Corp | Semiconductor device and method of manufacturing the same |
| US9496171B2 (en) * | 2014-09-26 | 2016-11-15 | Texas Instruments Incorporated | Printed interconnects for semiconductor packages |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2009076530A (en) * | 2007-09-19 | 2009-04-09 | Seiko Epson Corp | Method of forming wiring pattern |
| US9859256B1 (en) * | 2016-10-26 | 2018-01-02 | Stmicroelectronics S.R.L. | Ink printed wire bonding |
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