JP3435393B2 - Wireless communication method and wireless communication device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless communication method and a wireless communication device under a fading environment. For example, TDMA (Time Division Multiple Acces
In the digital mobile communication system for public service of the s) system, multi-valued QAM (Quadrature Amplitude Modulation:
The present invention relates to a fading distortion compensation technique when performing modulation by a quadrature amplitude modulation method.

[0002]

2. Description of the Related Art In mobile radio communication, the amplitude and phase of a received signal fluctuate due to fading. “Pilot signal insertion method” is a technique for compensating for fluctuations due to this fading. Seiichi Sampei, “16QAM for land mobile communication”
"Fading distortion compensation method" of the Institute of Electronics, Information and Communication Engineers, B-II, Vol.J72-B-II, No.1, pp.7-15, 1989-1. This method is known. A pilot symbol having a value of is inserted into the information symbol section and transmitted, and the receiving side estimates the fading fluctuation at the information symbol position from the received signal of the pilot symbol to perform fading distortion compensation.

FIG. 9 is a block diagram of a conventional radio communication apparatus using the "pilot symbol insertion method". 9A is a block diagram of the transmitter side, and FIG. 9B is a block diagram of the receiver side. In FIG. 9A, reference numeral 2 is a serial / parallel converter (S / P) that converts transmission data into parallel data in units of 4 bits. Reference numeral 3 is a baseband signal generator (BSG), which stores 16-bit 4-bit parallel data.
Convert to a baseband signal corresponding to one symbol of QAM modulation. Reference numeral 51 is a frame signal generation unit that periodically inserts pilot symbols at equal intervals in the information symbol section. 16QAM as the pilot symbol
Among the four symbols having the maximum amplitude in the signal space diagram of 1), the symbols are appropriately switched and used. 5
Is a low pass filter (LPF) for band limiting the baseband signal. 6 is a quadrature modulator, and 7 is a local oscillator. A reference frequency signal output from the local oscillator 7,
The quadrature reference frequency signal is 16QAM modulated with a band-limited baseband signal. Reference numeral 8 is an amplifier, and 9 is a transmission antenna, which amplifies and transmits the modulated signal.

On the other hand, in FIG. 9B, 11 is a receiving antenna, and 12 is a band pass filter (BPF), which limits the band of the received signal in order to normally operate the AGC 13 and AFC 14 which will be described later. An automatic gain controller (AGC) 13 keeps the received signal level constant.
An automatic frequency controller (AFC) 14 roughly adjusts the frequency offset between the transmitter side and the receiver side. 1
5 is a quadrature demodulator, 16 is a local oscillator, and 17 is a low-pass filter (LPF). 16QA is obtained by multiplying the received signal whose frequency offset is roughly adjusted by the reference frequency signal and the quadrature reference frequency signal output from the local oscillator 16.
The quasi-coherent detection of M is performed and the band is limited by the LPF 17 to output a reception signal (baseband signal of two channels of I phase and Q phase). The frequency of the reference frequency signal is orthogonally demodulated in a state where it does not completely match the frequency of the reference frequency signal of FIG.

Reference numeral 18 denotes a fading distortion estimation / compensation unit, which uses a pilot symbol to perform fading distortion estimation and fading distortion compensation, which will be described later with reference to FIG. 11, and also finely adjust the offset frequency. A symbol determination unit 19 outputs 4-bit output data per symbol by determining the received signal in which the fading distortion is compensated at the symbol timing.

FIG. 10 shows the "pilot symbol insertion method".
5 is an explanatory diagram showing a frame configuration of transmission data in FIG. In the illustrated example, a known 1-symbol pilot symbol is periodically inserted for each (N-1) symbol of the information symbol portion. One pilot symbol and the (N-1) information symbol portion form one frame. On the receiver side, amplitude / phase fluctuation compensation is performed with reference to this pilot symbol. The received signal of the pilot symbol is used to estimate the fading fluctuation which fluctuates with time. Next, for information symbols between pilot symbols, fading fluctuations are estimated using an interpolation method. A Gaussian interpolation formula or the like is generally used for the interpolation method.

FIG. 11 is a block diagram for explaining the fading distortion estimator / compensator 18 shown in FIG. 9B. In the figure, 18a is a fading distortion estimator, 18b
Is a fading distortion compensator. Reference numeral 61 denotes a sampling switch, which samples the reception signal U (t) from the LPF 17 in FIG. 9B. A frame synchronization unit 62 reproduces the frame timing of the cycle T _f from the received signal U (t). Sampling switch 6
1 is the input signal U (t) by the frame synchronization unit 62.
Only the inside pilot symbols are extracted and output to the delay unit 64. Reference numeral 63 denotes a clock reproducing unit, which is an input signal U
From (t), the clock timing (symbol timing) of the cycle T _S is reproduced. When the frame length is N,
There is a relationship of T _f = NT _S.

A delay unit 64 receives the pilot symbol output from the sampling switch 61,
An estimated value of the fading fluctuation obtained by dividing this by a predetermined pilot symbol value (for example, 3 + j · 3 having the maximum symbol amplitude) is delayed by one symbol timing and two symbol timings and output.
Note that in FIG. 11, the estimated value of the fading fluctuation obtained by dividing the output of the sampling switch 61 by the value of the pilot symbol as it is has a delay amount of zero, but the delay unit 6
4 as the first output. Delay unit 64
Is realized by a shift register by converting an analog delay element such as a CCD (Charge Coupled Device) or an input signal into a digital value by using an A / D converter (not shown).

Reference numerals 65, 66, and 67 are coefficient multipliers, which are pilot symbols output from the sampling switch 61, outputs obtained by delaying the pilot symbols by one clock timing,
Coefficients Q ₁ (m / N), Q ₀ (m / N), and Q, which will be described later, are respectively applied to the outputs delayed by two clock timings.
Multiply by _-1 (m / N). Here, N is the number of symbols in one frame, m is a symbol position in one frame, and a pilot symbol is inserted at a position of m = 0. The adder 68 adds the outputs of the coefficient multipliers 65, 66 and 67. The reciprocal calculator 69 calculates the reciprocal of the output of the adder 68 and outputs it to the multiplier 72.

Reference numeral 70 is also a sampling switch, and receives signal U (t) from LPF 17 in FIG. 9 (b).
Is sampled by the output of the clock reproducing unit 63, and the delay unit 7 of the fading distortion compensating unit 18b is sampled.
Output to 1. Reference numeral 71 denotes a delay unit, which is used for timing adjustment of two inputs in the multiplier 72, and outputs the output of the sampling switch 70 to one frame timing T
_{It is} delayed by _f and output to the multiplier 72.

Referring to FIG. 11, estimation of fading distortion
The compensation operation will be described using mathematical expressions. 1 while reproducing clock and synchronizing frame and symbol
When one pilot symbol is inserted into a frame (N symbols), the pilot symbol at the m = 0th position of the kth frame (t = kT _f , k = 0.1,2 ...,
The estimated value of the fading fluctuation in the symbol value 3 + j3) is as follows.

[Equation 1] However, the noise component included in the sample value is regarded as zero. Similarly, the estimated value of the fading fluctuation in the time before and after one symbol of t = kT _f is as follows.

[Equation 2]

The m-th information symbol of the k-th frame (t = kT _f + (m / N) T _f , k = 0.1, 2, ..., M =
The estimated value of the fading fluctuation in 1, 2, ..., N−1) is (k−1) th frame, kth frame,
By using a quadratic Gaussian interpolation formula based on the fading variation at each pilot symbol (m = 0) in the (k + 1) th frame, it is shown by the following equation.

[Equation 3] However,

[Equation 4]

[Equation 5]

[Equation 6]

The value of the above equation (1) is output from the adder 68 shown in FIG. The signal in which each information symbol of the received signal U (k + (m / N)) is compensated is obtained by dividing the complex baseband signal U (k + (m / N)) by the value of the equation (1). It becomes a street.

[Equation 7] The output of this equation (5) is obtained from the multiplier 72 shown in FIG. The "pilot symbol insertion method" described above is
Uniform Rayleigh fading is assumed (if there is no delayed wave after the direct wave or it can be ignored). If a delay wave is present, the influence of delay distortion increases as the delay time increases, and fading distortion compensation fails.

On the other hand, when there is a delayed wave and the influence of delay distortion is great, frequency selective fading occurs. As a countermeasure against delay distortion at this time, a method using an adaptive equalizer has been disclosed in, for example, “Mobile Communication” edited by Sasaoka, Ohmsha, Ltd. (Heisei 10-5-25), p. It is known as 256-282. This adaptive equalizer is a decision feedback equalizer (DF
E: Decision Feedback Equalizer) and maximum likelihood sequence estimation (M
LSE: Maximum Likelihood Sequence Estimation). However, the maximum likelihood sequence estimation increases the amount of calculation when the modulation multi-value number is large like 16QAM. For the initial acquisition of the adaptive equalizer, a training symbol sequence described later with reference to FIG. 13 is added before the information symbol section. Further, in the case where the time fluctuation is severe as in mobile communication, the decision feedback equalizer uses an RLS (Recursive Least Squares) algorithm having good followability.

FIG. 12 is a block diagram of a conventional radio communication apparatus using an adaptive equalizer. 12A is a block diagram showing the configuration of the transmitter side, and FIG. 12B is a block diagram showing the configuration of the receiver side. In the figure, parts similar to those in FIG. 9 are assigned the same reference numerals and explanations thereof are omitted. In FIG. 12A, reference numeral 81 is a frame signal generator, which adds a training symbol sequence to the information symbol section. In FIG. 12B, 2
Reference numeral 0 is an adaptive equalizer such as a decision feedback equalizer (RLS-DFE) using the RLS algorithm. FIG.
FIG. 4 is a frame configuration diagram when an adaptive equalizer is used.
The adaptive equalizer is configured to add a training symbol sequence (Nt symbol) consisting of a known signal before the information symbol section (Nd symbol) in one frame period.

FIG. 14 shows a pilot symbol insertion method (P
SAM) and RLS decision feedback equalizer (RLS-DFE)
FIG. 6 is a diagram showing a simulation result of a fading distortion compensation method using the. In the figure, the horizontal axis represents the delay time of the delayed wave with respect to the direct wave, and the maximum is one symbol period. The vertical axis represents BER (bit error rate). The characteristic is shown with the energy-to-noise power spectral density ratio (Eb / No) of the received modulated wave per bit as a parameter.

A simulation result in a 400 MHz band digital mobile communication system for public service is shown.
Bandwidth 12.5kHz / ch, 9.6ksymbol / sec (104
16 QAM of μsec / symbol). The maximum Doppler frequency fd = 20 Hz. The power of the direct wave and the power of the delayed wave are made equal. As the frame format, the frame format shown in FIG. 3, which will be described later as an embodiment of the present invention, is adopted. The synchronization word SW and the unique word UW are 16 symbols. The feed forward (FF) taps of the RLS decision feedback equalizer are 4 (tap interval 1/2 symbol), and the feedback (FB) taps are 2 (tap interval 1 symbol).

As can be seen from FIG. 14, the influence of delay distortion can be reduced by using the adaptive equalizer. However, even when the delay time is short, the BER does not decrease so much,
A sufficient equalization effect cannot be obtained. On the other hand, the pilot symbol insertion method is effective in a uniform fading environment where the influence of delayed waves can be ignored, but if the delay time becomes long, the BER rapidly deteriorates and the fading distortion compensation effect deteriorates. The environment for use in a large zone digital mobile communication system for public works is not limited to an area where the delay time of the delayed wave is short, such as an urban area. There are also long regions. In mobile terminals such as mobile phones, the area used is not constant, and
Since the use area may change depending on the time of use, if one of the above fading distortion compensation methods is fixedly used, it is not possible to effectively use the fading distortion compensation method to reduce the bit error rate. There was a problem that I could not.

[0019]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems and reduces the error rate of output data by using in parallel fading distortion compensation methods adapted to different propagation environments. It is an object of the present invention to provide a wireless communication method and a wireless communication device capable of performing the above .

[0020]

[0021]

[0022]

[0023]

[0024]

The present invention SUMMARY OF], in the invention according to claim 1, in the wireless communication apparatus, coding to transmit coded bit sequence is generated transmission data to the error detection code capable of, the transmission An information symbol sequence is generated based on the coded bit sequence, an information symbol interval is formed based on the information symbol sequence, at least one pilot symbol is inserted and / or added to the information symbol interval, and at least one training symbol Receiving means for receiving a signal modulated by a frame signal sequence is added to the information symbol section, demodulating means for demodulating the received signal, by estimating the fading distortion using the demodulated pilot symbol,
A first determining unit that determines the information symbol sequence after fading distortion compensation of the demodulated information symbol sequence, and operates in parallel with the first determining unit.
Then, adaptive equalization is performed using the demodulated training symbol sequence to obtain the demodulated information symbol sequence based on the outputs of the second determining means and the first determining means. A first received encoded bit string and a second obtained based on the output of the second determining means.
Error checking means for checking and comparing respective errors in the received coded bit strings of the above, and both of the first and second received coded bit strings according to the check result of the error checking means.
If no error was detected by one of the
If the received coded bit string is selected continuously and no error is detected in either one , the error is detected.
Select the received coded bit string that did not
Is detected, the reception of the previously selected one is received.
It further comprises output selection means for outputting the transmission data by continuously selecting the encoded bit string .
Further, in the invention described in claim 2,
In the wireless communication device described above, the output selection means is
According to the inspection result of the error checking means, the first and second receiving
When no error is detected in both the signal coded bit string
Replaces the previously selected received coded bit string.
Instead of selecting one after another, either one
This is for selecting one of the received encoded bit strings. Therefore, a fading distortion compensation method adapted to different propagation environments can be selected according to the error check result. As a result, the error rate of output data can be reduced. The fading distortion compensation mode different characteristics perform parallel operation is allowed by the error detection, actually because errors have adopted fading compensation method which is not detected, it is possible to further reduce the error rate of the output data .

[0025] In the invention of claim 3, claim
1 or 2 , wherein the error-detectable code is for encoding the transmission data in block units, and the first and second reception encoded bit strings are temporarily stored in block units. A data buffer for storing, the output selection means, in block units, according to the respective error check results of the first received coded bit string and the second received coded bit string,
The transmission data is output by selecting one of the first and second reception encoded bit strings stored in the data buffer. Therefore, since fading distortion compensation modes having different characteristics are operated in parallel and error detection is performed in block units, it is possible to output high-quality output data in block units according to the error check result. If the fading compensation method in which no error is actually detected is adopted, the error rate of the output data can be lowered.

[0026]

In the invention described in claim 4 ,
The wireless communication device according to any one of 1 to 3 , wherein the information symbol sequence is convolutionally encoded and interleaved after fixed bits are inserted into the transmission encoded bit sequence, The first and second reception code conversion means for outputting the first and second reception coded bit strings by deinterleaving the output of the second determination means and then performing Viterbi decoding to remove fixed bits are provided. I have. Therefore, error correction can be efficiently performed.

In the invention described in claim 5 ,
In the wireless communication device according to any one of 1 to 3 , the information symbol sequence is one in which the transmission coded bit sequence is scrambled, then fixed bits are inserted and convolutionally coded. The present invention has first and second reception code conversion means for outputting the first and second reception encoded bit strings by Viterbi decoding the output of the second determination means, removing fixed bits and descrambling. Is. Therefore, error correction can be efficiently performed.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the first embodiment of the present invention. Figure 1 (a) shows the transmitter,
FIG. 1B is a block diagram of the receiver. In the figure, parts similar to those in FIG. 9 and FIG. In the transmitter configuration of FIG. 1A, 1 is a CRC
It is an encoding unit. Figure 2 shows CRC (Cyclic Redundancy).
Check: Cyclic redundancy check) FIG. CRC
In the encoding unit 1, according to the CRC encoding rule,
As shown in FIG. 2, a redundant bit string is added to the information bit string of the transmission data to create a 1-block CRC code.
This CRC code is converted into 4-bit parallel data by the serial / parallel converter 2 and converted into a baseband signal corresponding to one information symbol of 16QAM modulation in the baseband signal generator 3.

In FIG. 1 (a), 4 is a frame signal generator, and at least 1 is assigned based on the information symbol sequence.
One information symbol section is formed, at least one pilot symbol is inserted and / or added to the information symbol section, and at least one training symbol sequence is added to the information symbol section to generate a frame signal. FIG. 3 is an explanatory diagram showing a frame format according to the embodiment of the present invention. In FIG. 3, SW (Sync Word) is a synchronization word and UW (Unique W)
ord) is a unique word and is a known symbol series, and the number of symbols is appropriately determined. p _{1 to} p
₁₀ is a pilot symbol of 1 symbol each, and Data is an information symbol of 15 symbols each. Each of the pilot symbols p _{2 to} p ₅ and p _{6 to} p ₉ has 5 Data items.
Are inserted in the first half and the second half of the information symbol section. The pilot symbols p ₁ and p ₁₀ are respectively
It is added to the beginning of the first half of the information symbol section and the end of the latter half of the information symbol section. The first and last 1 symbols of the unique word UW can also be used as pilot symbols.

In the illustrated example, pilot symbols are periodically inserted in the information symbol section at regular intervals.
It may not be inserted periodically or may be inserted at unequal intervals. Further, it is not always necessary to add it to the end of the information symbol section. If there is at least one pilot symbol in the frame signal, it is possible to perform fading compensation by estimating the fading distortion of each information symbol by interpolation from the estimated value of the fading fluctuation received by each pilot symbol. Even in the case of one pilot symbol, for example, it is possible to compensate the estimated value of the fading fluctuation received by this pilot symbol as it is as the estimated value of the fading distortion received by each information symbol. The synchronization word SW is used not only for frame synchronization, but also as a training symbol sequence for initial pulling in the adaptive equalizer 20. The unique word UW is provided as needed. As shown in the figure, the information symbol section is divided and added to the middle, and used as a training symbol sequence for retraining the adaptive equalizer 20 in the middle of the information symbol section. In addition, TDMA (Time Div
In the public mobile digital communication system of the ision multiple access type, the frame format shown in FIG. 3 corresponds to one slot (one burst) of one mobile terminal. In this case, when transmitted from the mobile terminal to the base station, a guard symbol, a ramp symbol, etc. are added to the beginning of the frame.

Here, a symbol sequence according to the 16QAM modulation rule will be described. FIG. 4 is a diagram showing a signal space diagram of 16QAM. As shown in FIG. 4, in 16QAM, in binary 4-bit transmission data, the values of the I-phase component and the Q-phase component are -3 and-, respectively.
It is assigned to one of 16 symbol points of 1, 1, and 3. As the pilot symbols and the training symbol series of the adaptive equalizer, the symbols A, B, C, and D shown in the figure, which have the largest symbol amplitude, are used.

In the receiver configuration of FIG. 1B, the fading distortion estimation / compensation unit 18 and the symbol determination unit 19 interpolate from the received complex baseband signal with the periodically inserted known pilot symbols. Then, the fading distortion is estimated by the following, and the fading distortion compensation is performed based on this estimated value, and the symbol determination unit 19 determines the symbol of multi-level QAM. On the other hand, the adaptive equalizer 20 estimates the fading gain using the training symbol sequence, and R
The tap coefficient is updated based on the LS algorithm or the like, the delay distortion and the fading distortion are compensated for the information symbol sequence, and the multi-level QAM symbol determination is performed.

CRC check and error state comparison unit 21
Is a CRC error for the decision output of the fading distortion estimation / compensation unit 18 and the symbol determination unit 19 in the first fading distortion compensation mode and the decision output of the adaptive equalizer 20 in the second fading distortion compensation mode. Detect. As a result, the error states of the respective modes are compared and a comparison result is output, and an information bit string of each mode in which redundant bits are removed is output. In FIG. 1B, parallel-serial conversion is performed inside the determiner 19 and the adaptive equalizer 20, and the CRC code in which the redundant bit string is added to the information bit string is the determiner 19 and the adaptive equalizer. Bowl 20
Shall be output from.

Reference numeral 22 denotes an output selection unit, which is a two-mode information consisting of an information bit string from the symbol determination unit 19 with redundant bits removed and an information bit string from the adaptive equalizer 20 with redundant bits removed. Enter the bit string. The output selection unit 22 also receives a signal indicating the error state of each mode from the CRC check and error state comparison unit 21. The output selection unit 22 selects one of the two-mode information bit strings as output data based on the signal indicating the error state of each mode.

As described above, on the transmitter side shown in FIG. 1A, pilot symbol insertion is performed so that the respective fading compensation methods can be applied to two fading types of uniform fading and frequency selective fading. And a training signal sequence for the adaptive equalizer is added and transmitted in a frame signal format. On the transmitter side, redundant bits are added to the information bit string to
The code is converted into an error detection code such as an RC code and then converted into an information symbol string for transmission.

FIG. 5 is a diagram schematically showing the relationship between delay time and BER (bit error rate) for the pilot symbol insertion method and the two fading distortion compensation methods using the adaptive equalizer. In the fading distortion compensation method by inserting pilot symbols, BE is used when the delay time is small.
Although R is low, the BER rapidly increases as the delay time increases. On the other hand, in the fading distortion compensation method using the adaptive equalizer, the BER does not decrease so much when the delay spread is small, but the increase rate of the BER is small even if the delay time becomes long. Fading distortion can be efficiently compensated by selecting the pilot symbol insertion method when the delay is small with _respect to the threshold τ _th and the method using the adaptive equalizer when the delay is large. But,
Therefore, it is necessary to accurately estimate the delay amount of the propagation path.

On the other hand, in the embodiment of the present invention,
Instead of switching the fading distortion compensation method by directly estimating the delay amount of the propagation path, an error detection code such as a CRC (Cyclic Redundancy Check) code is added to the information bit string in advance, and the receiver On the side, according to two fading compensation modes, fading compensation is performed respectively, and a method in which an error is not detected in the determination output is selected and output. That is, on the receiver side shown in FIG. 1B, a fading distortion compensation mode by pilot symbol insertion and two fading distortion compensation modes of a method using an adaptive equalizer are prepared, and both fading distortion compensation modes are prepared. In each mode, symbol determination is performed, and based on the check result for the CRC code string after determination,
One of the system information bit strings to which the fading compensation mode is applied is selected as output data. Although a CRC code is used in the following description, any error detection code may be used, and the invention is not limited to the CRC code.

FIG. 6 shows the judgment output by the pilot symbol insertion method (PSAM) for the CRC check result,
The determination output by the adaptive equalizer (RLS-DFE),
It is explanatory drawing which shows an example of the reference | standard which selects the determination output of two systems by two fading compensation modes. Where C
The RC check is performed for each block of the CRC code (information bit string + redundant bit string shown in FIG. 2) to detect whether or not there is at least one error in each block. Next, based on the CRC check result in each block, it is determined whether or not the information bit string in the block is selected as output data. The block length is not directly related to the frame length shown in FIG. Therefore, when a binary bit string of one block is converted into an information symbol, it may be designed to be equal to the information symbol string for one frame, or the block length may be independently determined.

When the error detection result is the same in the two fading compensation modes, that is, when both CRC check results are NG (with error) or both (OK without error), the previous block is used. The output of the selected fading compensation mode system is continuously selected. Note that if both are OK (no error), it may be decided to select the output of one of the modes, for example, the output of the mode 1 system. On the contrary,
When only one of the CRC check results is NG (error is present), the output of the fading compensation mode system whose CRC check result is OK (no error) is selected.

Since the information bit sequence in the block is selected according to the CRC check result for one block, it is necessary to temporarily hold the information bit sequences of both the modes 1 and 2. Therefore, a data buffer for holding the information bit sequence is provided in the CRC check and error state comparison unit 21, the output selection unit 22, or the like.

FIG. 7 is a block diagram showing the second embodiment of the present invention. In the figure, portions similar to those in FIG. 9 and FIG. This embodiment uses a convolutional code and interleaving in the first embodiment shown in FIGS. Figure 7
FIG. 1A is a partial configuration diagram on the transmitter side, and FIG.
In front of the serial / parallel converter 2 in FIG. Reference numeral 31 is a fixed bit insertion unit, 32 is a convolutional coding unit, and 33 is an interleave unit. In the CRC encoding unit 1, the CRC code as the error detection code is, for example,
It is generated by the generator polynomial shown in the following equation. Redundant bit string: 6-bit generator polynomial: X ⁶ + X + 1

The fixed bit inserting section 31 inserts 5 fixed bits "0" at the end of the bit string of the CRC code. The convolutional encoding unit 32 receives, as an error correction code, a bit string after insertion of fixed bits, and performs the following convolutional encoding, for example. Convolutional coding coding rate R = 1/2 (constraint length K = 6) generator polynomial: G1 (D) = 1 + D + D 3 + D 5 G2 (D) = 1 + D 2 + D 3 + D 4 + D 5

In mobile communication, interleaving is introduced in order to improve the bit error rate by randomizing burst errors caused by fading and effectively operating error correction codes. Although there are various methods for interleaving processing, for example, a method of converting rows and columns of a matrix is adopted. In order to perform the interleave processing, it is necessary to store data corresponding to the row × column size in the memory. The interleave unit 33 on the transmitter side writes the data in the row direction to the memory, reads the data in the column direction, and outputs the data to the serial-parallel converter 2 in FIG. The length of one cycle of this interleave is usually longer than the block length of the CRC code described above.

FIG. 7 (b) is a partial block diagram of the receiver side, which shows the decision unit 19 and the adaptive equalizer 20 of FIG. 1 (b).
It is provided between the CRC check and error state comparison unit 21. 34a and 34b are deinterleave units, and 35
Reference characters a and 35b are Viterbi decoding units, and reference characters 36a and 36b are fixed bit removal units. The subscript a indicates the output system of mode 1,
The subscript b indicates the output system of mode 2. As shown in FIG. 7A, when the transmitter side performs CRC code insertion and then convolutional code and interleaving to improve the error rate, the receiver side de-interleave units 34a, 34
b and Viterbi decoding units 35a and 35b for decoding the convolutional code.

The fixed bit removing units 36 a and 36 b remove the fixed bit “0” of 5 bits from the Viterbi-decoded data and output the data to the CRC check and error state comparing unit 21. Since the de-interleaving process is performed in units of the interleaving cycle, the CRC
The check can be performed at the shortest interleaving cycle. Therefore, rather than the interleave period, (CR
If the length of one block composed of (C code + fixed bit) is short, a plurality of CRC check results may be obtained by one check.

As another configuration, it is also possible to perform scramble processing and convolutional coding on the transmitter side and Viterbi decoding and descramble processing on the receiver side in the reverse order. FIG. 8 is a block diagram showing the third embodiment of the present invention. In the figure, portions similar to those in FIG. 9 and FIG. Figure 8
FIG. 1A is a partial configuration diagram on the transmitter side, and FIG.
In front of the serial / parallel converter 2 in FIG. Reference numeral 41 is a scramble processing unit 41. In the CRC encoding unit 1, the CRC code as the error detection code is
For example, it is generated by the generator polynomial shown in the following equation. Redundant bit string: 17-bit generator polynomial: X ¹⁷ + X ¹⁶ + X ¹⁵ + X ¹³ + X ¹² + X ⁸ + X ⁷
+ X ⁵ + X ² +1 If the transmission data is 82 bits, 1 block length is 99
Become a bit.

The scramble processing is a function introduced for the purpose of protection against interference of the communication control operation, and makes the data arrangement random, thereby improving the error correction capability. In the scramble processing unit 41, the output of the shift register PN (9, 5) and the scrambled data string,
That is, an exclusive OR (EXOR) operation for each bit is performed with the bit string of the CRC code in the CRC encoding unit 1. The fixed bit insertion adding unit 31 adds 5 fixed bits “0” to the end of the bit string of the scrambled CRC code before error correction coding. One block length is 104 bits.

The convolutional encoding unit 32 receives the bit string (104 bits in the above-mentioned specific example) after the fixed bit insertion as an input, and performs the following convolutional encoding as an error correction code. The output bits are alternately read in the order of 1 and 2. Convolutional coding coding rate R = 1/2 (constraint length K = 6) generator polynomial: G1 (D) = 1 + D + D 3 + D 5 G2 (D) = 1 + D 2 + D 3 + D 4 + D 5

FIG. 8 (b) is a partial block diagram of the receiver side, which includes the decision unit 19 and the adaptive equalizer 20 of FIG. 1 (b).
It is provided between the CRC check and error state comparison unit 21. 42a and 42b are descrambling processing units. On the receiver side, Viterbi decoding and descrambling processing are performed on the two types of determination outputs of mode 1 and mode 2, and CRC check and output selection are performed on the determination results. The descrambling process is a process of restoring a scrambled code string, and includes a scramble pattern obtained by setting the register initial value set when the bit string of the CRC code is scrambled on the transmitting side, and the scrambled code string. Is possible by adding 1 bit at a time.

Next, the CRC check and error state comparison unit 21 and the output selection unit 22 in the above-described second and third embodiments of the present invention will be described. Also in the above-described third embodiment of the present invention, the above-described CRC check and error state comparison unit 21 and output selection unit 22 operate in the same manner as in the above-described first embodiment. However, in the second embodiment, if the interleaving cycle is long, the processing is performed in units of this interleaving cycle. The output selection in the output selection unit 22 is
Even at the shortest, it will be done in the interleaving cycle. Then, for one block of each CRC code, it is determined whether to select the information bit string in the block according to NG (error is present) or OK (no error) of the CRC check result.

Alternatively, when there are a plurality of blocks within the interleaving cycle, it is determined whether or not the information bit of each block is selected by a comprehensive judgment of the CRC check results of each block, for example, a majority vote. It is also possible to decide. Also in the above-described second and third embodiments, since the information bit sequence is selected according to the CRC check result, it is necessary to temporarily hold the information bit sequences of both modes of modes 1 and 2. . Therefore, the CRC check and error state comparison unit 21 or the output selection unit 2
2, a buffer is provided for holding the information bit sequence. In the second embodiment, the processing is performed in units of the interleaving cycle, so the capacity that the buffer must store becomes large.

In the above description of the first to third embodiments, the two fading compensation modes are simultaneously operated in parallel. The probability that an error will occur simultaneously in a system with two fading distortion compensation modes is small. Therefore, the error rate of the output data is reduced by selecting and outputting the information bit sequence of the system determined to be OK (no error). This action is an action that can be said regardless of the fading environment of the propagation path in any range of the delay time shown in FIG. In particular, in the system of two fading distortion compensation modes, the action is remarkable in the vicinity of τ _th shown in the drawing, where the BERs of the two are close to each other.

On the other hand, as the second method of selecting the output in the first to third embodiments, the receiver side determines the two fading compensation methods from the history information of the error check result of the selected mode. For a certain time, or
After that, control such as stopping one operation can be continuously performed. On the side where the operation is stopped, when the signal processing is performed by software, the processing load of software can be reduced. When the signal processing is performed by hardware, power supply can be cut off to reduce power consumption. At the next predetermined switching timing, C again for the two fading compensation methods.
Output selection can be redone by comparing the RC check with the error condition. Further, in this case, it is not always necessary to temporarily store the information bit string of the block subjected to the CRC check in the buffer. Output selection may be performed for blocks received thereafter.

The second method of output selection described above is effective when the fading environment does not change abruptly even when the mobile terminal moves. As a timing at which switching selection is possible by the CRC check, a predetermined plurality of block intervals or a certain regular time interval can be set. It may be performed in the call setup sequence at the start of communication or at the time of handoff for switching the zone. Alternatively, like a receiver of a base station, once installed, it is also effective in a usage form in which the usage environment does not change. A CRC check should be performed at the first installation. However, in the second method of output selection described above,
The advantage of operating the two fading compensation modes simultaneously in parallel disappears.

In the above description, except for the second embodiment, the CRC check is performed for each block of the CRC code. Instead of this, in particular, in the second method of output selection described above, whichever bit is estimated to reduce bit errors based on the CRC check results for a predetermined period, for example, a plurality of block periods, Alternatively, the output of one of the fading compensation mode systems may be selected. For example, it is possible to select a fading compensation mode system having a larger number of OKs (no errors) in a plurality of predetermined block periods, or a fading compensation mode system having a predetermined number of consecutive OKs. Good. Further, the transmitting side may add the redundant bits to perform the CRC coding, and / or the receiving side may perform the CRC check only when it is necessary to determine whether to switch the output. Good.

[0057]

As is apparent from the above description, according to the present invention, a configuration in which the error-free one is selected from the error check results for the determination results of the two fading compensation modes is used, and therefore, different propagation is performed. There is an effect that fading distortion compensation can be accurately performed by adapting to the environment. Further, since the parallel use of the fading distortion compensation mode different characteristics, the bit error rate has the effect of lowered.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a CRC code.

FIG. 3 is an explanatory diagram showing a frame format according to the embodiment of the present invention.

FIG. 4 is a diagram showing a signal space diagram of 16QAM.

FIG. 5 is a diagram schematically showing a relationship between delay time and BER (bit error rate) for two fading distortion compensation methods using a pilot symbol insertion method and an adaptive equalizer.

FIG. 6 is an explanatory diagram showing an example of criteria for selecting two systems of determination outputs in two fading compensation modes, that is, a determination output by a pilot symbol insertion method and a determination output by an adaptive equalizer with respect to a CRC check result.

FIG. 7 is a block configuration diagram of a second embodiment of the present invention.

FIG. 8 is a block configuration diagram of a third embodiment of the present invention.

FIG. 9 is a block configuration diagram of a conventional wireless communication device using the “pilot symbol insertion method”.

FIG. 10 is an explanatory diagram showing a frame configuration of transmission data in the “pilot symbol insertion method”.

FIG. 11 is a block configuration diagram for explaining a fading distortion estimation / compensation unit 18 shown in FIG. 9B.

FIG. 12 is a block configuration diagram of a conventional wireless communication device using an adaptive equalizer.

FIG. 13 is a frame configuration diagram when an adaptive equalizer is used.

FIG. 14 is a diagram showing a simulation result of a fading distortion compensation method using a pilot symbol insertion method and an RLS decision feedback equalizer.

[Explanation of symbols]

1 ... CRC encoding unit, 2 ... Serial / parallel converter,
3 ... Baseband signal generator, 4 ... Frame signal generator, 5 ... Low-pass filter, 6 ... Quadrature modulator, 7 ... Local oscillator, 8 ... Amplifier, 9 ... Transmit antenna, 11 ... Receive antenna, 12 ... Bandpass filter , 13 ... Automatic gain control unit, 14 ... Automatic frequency control unit, 15 ... Quadrature demodulator, 1
6 ... Local oscillator, 17 ... Low-pass filter, 18 ... Fading distortion estimation / compensation unit by pilot symbol, 1
9 ... Symbol determination unit, 20 ... Adaptive equalizer, 21 ... CRC
Check and error state comparison unit, 22 ... Output selection unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H03M 13/41 H04B 3/10 C H04B 3/10 H04J 3/00 G 7/26 H04L 1/00 B H04J 3/00 27 / 00 K H04L 1/00 H04B 7/26 C (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 27/00 H03M 13/00 H04B 3/00-7/26 H04J 3/00 H04L 1 / 00

Claims (5)

(57) [Claims] 1. A transmission coded bit string is generated by coding transmission data into a code capable of error detection, an information symbol string is generated based on the transmission coded bit string, and an information symbol section is generated based on the information symbol string. Is formed, at least one pilot symbol is inserted and / or added to the information symbol section, and at least 1
Receiving means for receiving a signal modulated by a frame signal in which one training symbol sequence is added to the information symbol section, demodulating means for demodulating the received signal, and estimating fading distortion using the demodulated pilot symbols As a result, the demodulated information symbol sequence is compensated for fading distortion, and the first determination unit for determining the information symbol sequence and the first determination unit operate simultaneously in parallel.
Then, adaptive equalization is performed using the demodulated training symbol sequence to obtain the demodulated information symbol sequence based on the outputs of the second determining unit and the first determining unit. Error checking means for checking and comparing respective errors of the first received coded bit string and the second received coded bit string obtained based on the output of the second judging means, and the error checking means. Whether an error is detected in both of the first and second received coded bit strings depending on the inspection result
The received coded bit that was previously selected.
Selected rows continuously, and an error is detected in either
If there is not, the received code of which the error was not detected
If you select an encrypted bit string and an error is detected in both,
Continue the previously selected received coded bit string
By selecting Te, wireless communication apparatus characterized by having the output selecting means for outputting the transmission data. 2. The output selecting means is the error checking means.
According to the inspection result of the above, the first and second received coding bits are
If no error is detected in both
Continue to select the received encoded bit string that was selected
In stead of
The wireless communication device according to claim 1 , wherein a selected bit string is selected . 3. The error-detectable code encodes the transmission data in block units, and a data buffer for temporarily storing the first and second reception encoded bit strings in block units. The output selection means stores in the data buffer, in block units, in accordance with respective error check results of the first received coded bit string and the second received coded bit string. The radio communication device according to claim 1 or 2 , wherein the transmission data is output by selecting one of the first and second reception encoded bit strings. 4. The information symbol sequence is convolutionally encoded and interleaved after fixed bits are inserted into the transmission encoded bit sequence, and the outputs of the first and second determining means are deinterleaved. by the Viterbi decoding is fixed bit removed after the first, first outputs the second reception encoded bit sequence, a second received code converting means 3 to claim 1, characterized in that The wireless communication device according to any one of items 1 to 7 . 5. The information symbol sequence is a convolutional encoded sequence in which fixed bits are inserted after scrambling the transmission encoded bit sequence, and Viterbi-decoded the outputs of the first and second determining means. by fixing bit removal descrambling after the first, the first outputs the second reception encoded bit sequence, a second received code converting means, that from claim 1, wherein up to 3 the wireless communication apparatus according to any one.