JP3431544B2 - Wideband signal analyzer - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wideband signal analyzer suitable for frequency domain signal analysis, particularly frequency domain signal analysis in a wide band.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing the configuration of the main part of a conventional signal analyzer in the frequency domain. The signal under measurement is converted into an IF (intermediate frequency) signal by a known frequency converter 10 including a mixer, a local oscillator and the like. This IF signal is a BPF (band pass filter) 12
Gives a signal with an appropriate bandwidth. The output signal of the BPF 12 is amplified by the IF amplifier 14 and further AD
It is converted into a digital signal by a C (analog / digital converter) 16. The output signal of the ADC 16 is subjected to FFT operation processing by a DSP (digital signal processor) 18 and converted into frequency domain data. This frequency domain data is sequentially stored in the memory 20.

The trigger detector 21 detects whether or not the frequency domain data from the DSP 18 satisfies a predetermined trigger condition. That is, the data designated as the trigger condition is compared with the frequency domain data of the signal under measurement, and when they match, a trigger signal is generated. The data designated as the trigger condition means, for example, that the operator sets a specific region in the measurement region in which the frequency is displayed on the horizontal axis and the amplitude is displayed on the display screen (not shown) as the trigger condition. It is data.

When the trigger condition is satisfied, a trigger signal is generated, and the memory controller 23 controls the storage operation of the memory 20 according to the trigger signal. That is, the time until the storage operation of the memory 20 is stopped after the generation of the trigger signal can be adjusted. When the storage operation of the memory 20 is immediately stopped from the time when the trigger signal is generated, the memory stores data up to the time when the trigger signal is generated, and such a function is called a pre-trigger function. On the other hand, when the storage operation of the memory 20 is continued for a certain period after the generation of the trigger signal and then the storage operation is stopped, the data mainly after the generation of the trigger signal is stored in the memory 20. It will be. This function is called the post-trigger function.

After the data is stored in the memory 20 in this way, the data in the memory 20 is read out and C
The analysis result in the frequency domain is displayed on an appropriate display device (not shown) such as an RT or a liquid crystal display.

[0006]

In recent years, along with the widening of the communication system and the speeding up of the operation of electronic devices, it has been desired to widen the measuring frequency range (span) of the signal under measurement.
However, in the conventional signal analyzer as shown in FIG.
It has been found that the following problems occur when trying to realize a wide band. That is, if the band width of the band pass filter is widened, the band width of the IF amplifier must be expanded and the sampling frequency of the ADC must be increased. One of the reasons why it is difficult to speed up the sampling frequency of the ADC is to decompose about 8 bits in a time domain signal analysis such as an oscilloscope, but to 12 or more in a frequency domain signal analysis such as a spectrum analyzer. This is because a resolution of 14 bits is desired.
Along with that, it becomes necessary to increase the calculation speed of the DSP.
It is necessary to speed up the data transfer rate and the memory operation. As a result, it becomes more susceptible to disturbances and noises over a wide band of frequencies, and spurious characteristics tend to deteriorate. Moreover, it is clear that this will lead to a significant increase in costs.

Further, since the detection of the trigger condition is performed on the FFT-calculated data in the frequency domain, as a result, the detection of the trigger condition becomes very difficult due to the above reason.

Therefore, an object of the present invention is to provide a wideband signal analyzer which is low in cost and can suppress deterioration of the characteristics accompanying the widening of the band to a minimum.

Another object of the present invention is to provide a wideband signal analyzer which realizes a low cost and practical event trigger function in wideband signal measurement.

[0010]

A wideband signal analyzer according to the present invention realizes a wide band while suppressing deterioration of signal characteristics to a minimum. The frequency conversion means converts the signal under measurement into an intermediate frequency signal. The narrowband signal processing means receives the intermediate frequency signal and generates a first digital signal representing a signal in the first frequency band of the intermediate frequency signal. The wideband signal processing means receives the intermediate frequency signal and generates a second digital signal representing a signal in the second frequency band of the intermediate frequency signal having a band wider than the first frequency band. The transfer speed reduction unit is configured by, for example, a FIFO memory or the like, and reduces the transfer speed of the second digital signal. The calculation means outputs the calculation result of the first digital signal or the output signal of the transfer rate reduction means. The storage means stores the calculation result of the calculation means. At this time, the calculation means may selectively output the calculation result of the first digital signal or the output signal of the transfer rate reduction means.

When the event trigger function is not used (for example, the roll mode in a spectrum analyzer), the calculating means uses the first digital signal when the measured frequency band of the signal under measurement is within the first frequency band. The calculation result of the signal may be output, and when the measurement frequency band is wider than the first frequency band, the calculation result of the output signal of the transfer rate reducing means may be output. The data thus obtained is used for continuous waveform display and other continuous signal analysis.

Trigger detection means may be further provided to detect whether the calculation result of the first digital signal by the calculation means satisfies a predetermined trigger condition. Then, the control means controls the transfer rate reducing means according to the output signal of the trigger detecting means. More specifically, the transfer speed reducing means is a FIFO.
The memory is used to control the storage operation of the transfer rate reducing means in order to realize a well-known event trigger function such as a pre-trigger function and a post-trigger function. At this time, it is designed so that the first frequency band is included in the second frequency band. this is,
For the trigger detection, the fact that the calculation result of the first digital signal corresponding to the first frequency band narrower than the second frequency band is practically sufficient is used in many cases.

Further, the transfer rate reducing means may store the second digital signal, and the time from the time when the control means detects the predetermined trigger condition to the time when the storing operation of the transfer rate reducing means is stopped may be controlled. . As a result, the event trigger function can be effectively realized in wideband signal processing.

More specifically, the above-mentioned transfer speed reducing means reduces the transfer speed of the second digital signal to the maximum processing speed of the arithmetic means or less. This enables the processing speed of the wideband signal processing means to be higher than the processing speed of the calculation means.

More specifically, the configuration of the wideband signal processing means is such that the wideband passing means for receiving the intermediate frequency signal and passing the signal of the second frequency band and the output signal of the wideband passing means are converted into a second digital signal. And high-speed analog-to-digital conversion means for At this time, high-speed analog
The processing speed of the digital converting means is set to be higher than the processing speed of the computing means.

According to the above configuration, in the case of a narrow band measurement frequency range, measurement can be performed by using the same configuration as the conventional narrow band side, so that noise and spurious characteristics are deteriorated due to widening of the band. Never. On both the narrow band side and the wide band side, filters, amplifiers, ADCs, etc. optimized for the measured bandwidth can be selected, respectively, which is advantageous in terms of technology and cost. Since the transfer rate of the output data of the high-speed analog-to-digital conversion means is reduced, DS
It is not necessary to increase the operating speed of P and the like. At the same time, the event trigger function can be realized by making a slight change to the conventional configuration.

[0017]

1 is a block diagram showing the configuration of the main part of a wideband signal analyzer according to the present invention. Figure 2
The same reference numerals are attached to the components corresponding to the conventional example. The signal under measurement is converted into an appropriate IF signal (intermediate frequency signal) by the frequency converter 10. The frequency converter 10 may have a conventional configuration including a mixer, a local oscillator and the like. The IF signal, which is the output signal of the frequency converter 10, is supplied to both the BPF (bandpass filter) 12 and the wideband BPF 22.

The wideband signal analyzer according to the present invention has at least two signal paths, a narrowband side and a wideband side. The BPF 12 is a filter similar to the conventional example of FIG. 2, and has a relatively narrow pass frequency bandwidth (for example, 5 MH).
z), the entrance of the signal path on the narrow band side. Below, BP
The frequency band of the output signal of F12 will be called the first frequency band. At the output end of the BPF 12, I
An F amplifier 14 is connected, and an ADC (analog / digital converter) 16 is connected to the output terminal of the IF amplifier 14. The digital signal output from the ADC 16 will be referred to as a first digital signal below. The first digital signal thus obtained eventually represents a signal in the first frequency band of the intermediate frequency signal. These, BP
The narrow band side signal path (narrow band signal processing means) composed of the F12, the IF amplifier 14, and the ADC 16 is exactly the same as the configuration of the conventional signal path of FIG.

On the other hand, the wide band BPF 22 is set to have a relatively wide pass frequency band width (for example, 30 MHz) and serves as an entrance of a signal path on the wide band side. Below, broadband BPF
The frequency band of the output signal of 22 will be referred to as a second frequency band. That is, the frequency band (second frequency band) of the output signal of the wide band BPF 22 is set wider than the frequency band (first frequency band) of the output signal of the BPF 12. The output signal of the wide band BPF 22 is appropriately amplified by the wide band IF amplifier 24, and then converted into a digital signal by a high speed ADC (analog / digital converter) 26. The digital signal output by this high-speed ADC 26 is
Hereinafter, it will be referred to as a second digital signal. The second digital signal thus obtained consequently represents a signal in the second frequency band of the intermediate frequency signal. These wide band BPF 22, wide band IF amplifier 24 and high speed ADC 2
Reference numeral 6 constitutes a wideband side signal path (wideband signal processing means).

By the way, according to the sampling theorem well known to those skilled in the art, the sampling frequency at the time of analog-digital conversion needs to be at least twice the highest frequency of the analog input signal. Therefore, the high speed ADC 26
The sampling frequency is set to twice or more the maximum frequency of the output signal of the wide band IF amplifier 24. Therefore, the output data of the high-speed ADC 26 (second digital signal)
Is higher than the transfer rate of the output data (first digital signal) of the ADC 16 on the narrow band side.

The output data (second digital signal) of the high speed ADC 26 is sequentially stored in the FIFO memory 28. The FIFO memory 28 is a so-called first-in first-out memory, and is a memory that sequentially stores and reads out data in chronological order. However, this FIFO memory 28
Functions as a data transfer speed reduction means and reads data at a speed slower than the data write speed. This is because the processing speed (clock frequency) of the high speed ADC 26 is
Since it is faster than the processing speed (clock frequency) of the DSP 18, which will be described later, the FIFO speed is below the maximum processing speed of the DSP 18.
This is because it is necessary to reduce the transfer rate of the output data of the memory 28. It should be noted that this is not an essential condition of the present invention but a design convenience. However, if the data transfer rate of the output data of the FIFO memory 28 and the data transfer rate of the output of the ADC 16 are made to coincide with each other, the DSP 18 and the ADC 18
Data transfer to and from 16 and FIFO memory 28, respectively, is facilitated.

The MPX (multiplexer) 30 is an ADC
It functions as a selection unit that receives both the output signal of 16 and the output signal of the FIFO memory 28 as input signals and selects and outputs one of them. The output of the MPX 30 is supplied to a DSP (digital signal processor) 18, and an operation such as an FFT operation is executed as in the conventional case. D
The output data of the SP 18 is sequentially stored in the memory 20 and also supplied to the trigger detector 32.

The trigger detector 32 compares the calculation result (frequency domain data) of the first digital signal by the DSP 18 with preset trigger condition data, and generates a trigger signal when the trigger condition is satisfied. That is, when detecting the trigger condition, the MPX 30 selects and outputs the first digital signal output from the ADC 16. This trigger signal is supplied to the memory controller 34. The trigger condition is set, for example, in the same manner as the above-mentioned conventional example.

The memory controller 34 includes a memory 20 or FI.
The storage operation of the FO memory 28 is controlled. At this time, when realizing the above-described event trigger function, the storage operation of the memory 20 or the FIFO memory 28 is controlled especially according to the trigger signal. Also, the memory controller 3
As will be described later, the memory 4 or the memory 4 has a memory 20 or a FIFO memory 2 even when the event trigger function is not used.
8 memory operation control. However, in this case, since it is not related to the trigger signal, the memory controller 34 that receives the trigger signal does not necessarily need to control the storage operation, and control by another method may be adopted.

In using the signal analyzer,
The operator indicates to the signal analyzer the frequency band to be measured. This is usually the frequency of the center of measurement (center frequency) and the frequency span (frequency bandwidth you want to measure).
It is done by instructing one. Then, the signal analyzer according to the present invention determines whether to use the narrow band signal processing means or the wide band signal processing means according to the measured frequency band. However, the operator may forcibly set which one to use. For example, even if the measurement frequency band is narrower than the first frequency band, the operator may instruct the analyzer to use the wideband signal processing means and can set it.

At this time, when the data of the signal under measurement is acquired using the narrow band signal processing means and a trigger is applied to this data, the memory controller 34 causes the memory 2 to operate.
The memory operation of 0 is controlled in exactly the same way as in the conventional case of FIG. That is, similarly to the above, the storage operation of the memory 20 is controlled according to the pre-trigger function, the post-trigger function, and the like.

On the other hand, when the data of the signal under measurement is acquired by using the wide band signal processing means and the trigger is applied to this data, the memory controller 34 of the FIFO memory 28 realizes the above-mentioned event trigger function. Controls memory operation. That is, the FIFO memory 28 is data (second digital signal) obtained by wideband signal processing the signal under measurement.
Is stored, by controlling the storage operation,
The event trigger function in wideband signal processing can be effectively realized. The method of controlling the storage operation of the FIFO memory 28 is the same as the event trigger function such as the pre-trigger function described above. The FIFO memory 28
If the capacity is filled with data before the memory stops its storage operation, the oldest data is erased and the latest data is stored. As a result, the FIFO memory 28 stores the latest data within the range permitted by the capacity.

By the way, when the event trigger operation is executed in the wideband signal processing according to the present invention described above, the output frequency domain data of the DSP 18 which is the target of trigger detection is the data (first digital signal) generated by the narrowband signal processing means. ) Is the calculation result. Further, at this time, the broadband B
Frequency band of output signal of PF22 (second frequency band)
Is wider than the frequency band (first frequency band) of the output signal of the BPF 12, and is set so that the second frequency band includes the first frequency band. That is, the frequency band of the signal used for trigger detection is part of the frequency band of the signal that generates the data to be stored. This means that even if the trigger condition is not detected for all the frequency bands of the signal that generates the data to be stored, it is sufficient for practical use in many cases by only detecting the trigger condition for some of the frequency bands. We are using.

With this configuration, a substantially sufficient event trigger function can be realized in wideband signal processing, and the change in the trigger detection mechanism from the conventional basic configuration can be extremely reduced. Therefore, the cost increase can be suppressed to a minimum.

After storing the desired wideband signal processing data in the FIFO memory 28, the MPX 30 is switched and the F
The data in the IFO memory 28 is read and supplied to the DSP 18, the FFT operation is executed, and frequency domain data for wideband signal processing is generated. The frequency domain data of this wideband signal processing is stored in the memory 20, and based on this data, the measurement result is displayed on a display device (not shown) such as a CRT (cathode ray tube), or further analysis processing is performed. Can be executed. When the frequency domain data for wideband signal processing is stored in the memory 20, if the previous data remains, it may be transferred to another storage means (not shown) such as a magnetic disk. . Memory 2
0 is connected to the bus of a well-known microprocessor system using a CPU (not shown), through which these operations are performed.

By the way, it is not always necessary to use the event trigger function. In this case, data is generated by the narrow band signal processing means or the wide band signal processing means according to the instruction of the operator, the data is continuously stored in the memory 20 via the MPX 30 and the DSP 18, and a display device (not shown) may be used as necessary. ) To display the data. Note that the operation of continuously acquiring data regardless of such a trigger is the "roll mode" in the spectrum analyzer.
Known as. However, in the case of generating data from the wideband signal processing means, it is necessary to provide a stop time for occasionally stopping the acquisition of data because the output data (second digital signal) is decelerated by the FIFO memory 28.

Further, the memory 20 or FIFO at this time
The storage operation of the memory 28 is preferably performed by the memory controller 34. However, since the memory operation control in this case is performed independently of the trigger signal, the memory controller 34 that receives the trigger signal does not necessarily have to perform it, and the memory operation may be simply controlled by a known address control method. Please note. Further, in this case, since the trigger detection is not performed, it is not necessary to set the second frequency band so as to include the first frequency band, and the second frequency band may simply be set wider than the first frequency band. In the above, an example having two signal paths on the narrow band side and the wide band side has been shown.
Further, a large number of signal paths having different bandwidths may be provided, and the optimum element for the band may be selected and used in each path.

FIG. 3 is a block diagram of another preferred embodiment of the present invention. Components corresponding to those in FIG. 1 are designated by the same reference numerals. In the following, a part different from the embodiment of FIG. 1 will be described in detail. In the embodiment shown in FIG. 3, instead of using the MPX (multiplexer) 30, it has first and second DSPs 17 and 19 that receive the output signals of the ADC 16 and the FIFO memory 28 independently of each other. The first DSP 17 receives the first digital signal generated by the narrow band signal processing means, performs FFT calculation and the like, and supplies the calculation result of the first digital signal to the first memory 36 and the trigger detector 32. Second DSP 19
Receives the decelerated second digital signal from the FIFO memory 28, performs FFT calculation and the like, and
Supply the calculation result to. First and second memories 36 and 3
Reference numeral 8 is connected to a bus of a well-known microprocessor system using a CPU (not shown), and displays stored data on a display device (not shown) as necessary,
Data is transferred to a magnetic disk and used for other signal analysis.

The trigger detector 32 compares the calculation result of the first digital signal with predetermined trigger condition data and generates a trigger signal when the trigger condition is satisfied. The memory controller 34 controls the storage operation of the FIFO memory 28 according to the trigger signal from the trigger detector 32, as described above,
Realizes the event trigger function in wideband signal processing. Also in this case, the trigger is detected using the calculation result generated by the first DSP 17 from the first digital signal from the narrow band signal processing means, and the FIFO memory 28 stores the data (second digital signal) from the wide band signal processing means. The points to be stored are the same as in the example of FIG. Further, at the same time, the memory controller 34 controls the storage operation of the first memory 36 in accordance with the trigger signal from the trigger detector 32 to realize the event trigger function in the narrow band signal processing, as described above. . On the other hand, in so-called roll mode,
The first and second DSPs 17 and 1 regardless of the trigger signal
The data of the operation result of the first and second digital signals by 9 are stored in the first and second memories 36 and 38, respectively.
In this way, the data generated by the narrowband signal processing means and the wideband signal processing means can be stored simultaneously.

When the memory controller 34 realizes the event trigger function in the narrow band signal processing,
This is realized by controlling the storage operation of the first memory 36 as described above. On the other hand, the memory controller 34 is
It also controls the storage operation of memory 38, which is an event
It does not realize the trigger function. Therefore, the storage operation control of the second memory 38 may be performed by well-known address control without using the memory controller 34 that receives the trigger signal. Further, in the roll mode, the storage operation control of the FIFO memory 28 and the first and second memories 36 and 38 may be performed by well-known address control without using the memory controller 34.

Since the embodiment of FIG. 3 uses two DSPs, it is more expensive than the embodiment shown in FIG. However, since the FIFO memory 28 reduces the transfer speed of the second digital signal to the maximum processing speed of the second DSP 19 or less, a relatively inexpensive DSP can be used as in the above case.

FIG. 4 is a block diagram of still another preferred embodiment of the present invention. Components corresponding to those in FIG. 3 are designated by the same reference numerals. Parts different from the embodiment of FIG. 3 will be described below. In the embodiment shown in FIG.
MPX output signals of the first and second DSPs 17 and 19
A (multiplexer) 30 selectively supplies the memory 20. Which of the narrow band side data and the wide band side data the MPX 30 supplies to the memory 20 is determined according to the measurement frequency band instructed by the operator. The trigger detector 32 compares the calculation result of the first digital signal by the first DSP 17 with predetermined trigger condition data, and generates a trigger signal when the trigger condition is satisfied. The memory controller 34
When realizing the event trigger function in the narrow band signal processing, this is realized by controlling the storage operation of the memory 20 as described above. In other cases, it is as described above.

The preferred embodiment of the present invention has been described above.
It will be apparent to those skilled in the art that the present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the gist of the present invention.

As described above, according to the present invention, in the case of a narrow band measurement frequency range, measurement can be performed using the same configuration as the conventional one, so that noise and spurious characteristics are deteriorated due to widening of the band. There is no. Since it is possible to select filters, amplifiers, ADCs, etc. optimized for the bandwidth to be measured on both the narrowband signal path and the wideband signal path,
It is advantageous in terms of technology and cost. Further, since the data transfer speed reducing means reduces the transfer speed of the output data of the high speed analog / digital converting means, there is no need to increase the operating speed of the DSP, the memory, etc., and the increase in cost is suppressed to a minimum. be able to. Further, the event trigger function can be easily realized by making a relatively slight change to the conventional configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of a wideband signal analyzer according to the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of a conventional signal analyzer.

FIG. 3 is a block diagram showing a configuration of a main part of another embodiment of a wideband signal analyzer according to the present invention.

FIG. 4 is a block diagram showing a configuration of a main part of still another embodiment of a wideband signal analyzer according to the present invention.

[Explanation of symbols]

10 frequency converter 12 band pass filter 14 IF amplifier 16 ADC 17 First DSP 18 DSP 19 Second DSP 20 memory 22 Wide band pass filter 24 Wideband IF amplifier 26 high speed ADC 28 FIFO memory 30 multiplexer 32 Trigger detector 34 Memory controller 36 First memory 38 Second memory

Continuation of the front page (56) Reference JP 62-225964 (JP, A) JP 5-26921 (JP, A) JP 10-170567 (JP, A) Actual development 61-115978 (JP , U) Actual development Sho 58-57977 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01R 23/16 G01R 23/173

Claims (7)

(57) [Claims] 1. A narrow band signal for converting a signal under test into an intermediate frequency signal, and a narrow band signal for receiving the intermediate frequency signal and generating a first digital signal representing a signal in a first frequency band of the intermediate frequency signal. Processing means, wideband signal processing means for receiving the intermediate frequency signal and generating a second digital signal representing a signal in a second frequency band of the intermediate frequency signal having a band wider than the first frequency band; The present invention comprises a transfer rate reducing means for reducing the transfer rate of the digital signal, a computing means for outputting the computation result of the first digital signal or the output signal of the transfer rate reducing means, and a storage means for storing the computation result. Wideband signal analyzer. 2. The wideband signal analyzer according to claim 1, wherein the calculation means selectively outputs the calculation result of the first digital signal or the output signal of the transfer rate reduction means. 3. The calculating means, if the measurement frequency band of the signal under measurement is within the first frequency band, the first frequency band is calculated.
3. The calculation result of the digital signal is output, and when the measured frequency band is wider than the first frequency band, the calculation result of the output signal of the transfer rate reducing means is output. Wideband signal analyzer as described. 4. Trigger detection means for detecting whether or not the calculation result of the first digital signal by the calculation means satisfies a predetermined trigger condition, and the transfer speed reduction means is controlled according to an output signal of the trigger detection means. 3. The wideband signal analyzer according to claim 1, further comprising a control means for controlling the second frequency band, wherein the second frequency band includes the first frequency band. 5. The transfer speed reduction means stores the second digital signal, and the control means controls a time from when the predetermined trigger condition is detected to when the storage operation of the transfer speed reduction means is stopped. The wideband signal analyzer according to claim 4, wherein 6. The processing speed of the wideband signal processing means is higher than the processing speed of the computing means, and the transfer speed reducing means sets the transfer speed of the second digital signal to a maximum processing speed of the computing means or less. The wideband signal analyzer according to any one of claims 1 to 5, characterized in that: 7. The wideband signal processing means receives the intermediate frequency signal and passes a signal in the second frequency band, and converts an output signal of the wideband passage means into the second digital signal. 7. A wideband signal according to claim 1, further comprising high-speed analog-digital conversion means, wherein the processing speed of the high-speed analog-digital conversion means is higher than the processing speed of the arithmetic means. analyzer.