JP3425378B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3425378B2 JP3425378B2 JP29924098A JP29924098A JP3425378B2 JP 3425378 B2 JP3425378 B2 JP 3425378B2 JP 29924098 A JP29924098 A JP 29924098A JP 29924098 A JP29924098 A JP 29924098A JP 3425378 B2 JP3425378 B2 JP 3425378B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- forming
- resin
- boundary
- integrated circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Dicing (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップとほ
ぼ同一寸法のパッケージに組み立てられたチップサイズ
パッケージ（以下、「ＣＳＰ」という）型の半導体装置
の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device of a chip size package (hereinafter referred to as "CSP") type which is assembled into a package having substantially the same size as a semiconductor chip.
【０００２】[0002]
【従来の技術】ＩＣ（集積回路）カードやメモリカード
の発達に伴い、これらのカードに組み込まれる半導体装
置には、薄型かつ小型のものが要求されるている。この
要求に対応するために、半導体素子の裏面を露出させる
ことで薄型化を図り、かつ半導体素子サイズ内に外部接
続用の半田バンプを設けて、小型化を図ったＣＳＰ型の
半導体装置が用いられている。2. Description of the Related Art With the development of IC (integrated circuit) cards and memory cards, semiconductor devices incorporated in these cards are required to be thin and small. In order to meet this demand, a CSP type semiconductor device is used in which the back surface of the semiconductor element is exposed to reduce the thickness, and solder bumps for external connection are provided within the size of the semiconductor element to reduce the size. Has been.
【０００３】図２（ａ）〜（ｅ）は、従来のＣＳＰ型の
半導体装置の製造工程図であり、次のような工程によっ
て製造されている。図２（ａ）の工程に示すように、例
えば直径約２０ｃｍ、厚さ３５０μｍの半導体ウエハ１
の表面（回路形成面）に、薄膜形成、不純物添加、及び
微細加工等のウエハ処理が順次施され、縦及び横方向に
整然と並んだ複数の同一パターンの集積回路２が形成さ
れる。各集積回路２は、外部接続用の複数の電極３を有
しており、これらの複数の電極３上に所定の厚さの銅め
っきが施されて層間接続用のヴィアポスト４が形成され
る。ヴィアポスト４が形成された半導体ウエハ１は、図
２（ｂ）の工程に示すように、表面を上にして下金型１
１の上に配置され、その上に所定量の封止用のエポキシ
樹脂５が供給される。エポキシ樹脂５の上から、上金型
１２を圧接して加熱することにより、加熱溶融されたエ
ポキシ樹脂５が半導体ウエハ１の表面に圧着されて、樹
脂封止面が形成される。2A to 2E are manufacturing process diagrams of a conventional CSP type semiconductor device, which are manufactured by the following processes. As shown in the process of FIG. 2A, for example, a semiconductor wafer 1 having a diameter of about 20 cm and a thickness of 350 μm
The surface (circuit forming surface) is subjected to wafer processing such as thin film formation, impurity addition, and microfabrication in order to form a plurality of integrated circuits 2 having the same pattern arranged in the vertical and horizontal directions. Each integrated circuit 2 has a plurality of electrodes 3 for external connection, and copper plating of a predetermined thickness is applied to the plurality of electrodes 3 to form via posts 4 for interlayer connection. . The semiconductor wafer 1 on which the via posts 4 are formed has the surface thereof facing upward as shown in the step of FIG.
1, and a predetermined amount of epoxy resin 5 for sealing is supplied thereon. When the upper mold 12 is pressed against the epoxy resin 5 and heated, the heat-melted epoxy resin 5 is pressure-bonded to the surface of the semiconductor wafer 1 to form a resin sealing surface.
【０００４】エポキシ樹脂５による封止が施された半導
体ウエハ１は、金型１１，１２から取り出され、図２
（ｃ）の工程に示すように、接着テープ１３によって研
磨台１４に固定される。そして、ヴィアポスト４の頭部
が露出するまでグラインダ１５で樹脂封止面の研磨処理
が施される。ヴィアポスト４の露出面には、図２（ｄ）
の工程に示すように、半田バンプ６が形成される。そし
て、図２（ｅ）の工程に示すように、半導体ウエハ１上
に並んだ複数の集積回路２は、ダイシングブレード１６
によって縦及び横方向に切断される。これによって、半
導体ウエハ１上の各集積回路２は個片に分割され、ＣＳ
Ｐ型の半導体装置１０が完成する。The semiconductor wafer 1 sealed with the epoxy resin 5 is taken out from the metal molds 11 and 12, and
As shown in the step (c), it is fixed to the polishing table 14 by the adhesive tape 13. Then, the resin sealing surface is polished by the grinder 15 until the head of the via post 4 is exposed. The exposed surface of the via post 4 is shown in FIG.
As shown in the process of (1), the solder bumps 6 are formed. Then, as shown in the step of FIG. 2E, the plurality of integrated circuits 2 arranged on the semiconductor wafer 1 are separated by the dicing blade 16
It is cut vertically and horizontally. As a result, each integrated circuit 2 on the semiconductor wafer 1 is divided into individual pieces,
The P-type semiconductor device 10 is completed.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、従来の
ＣＳＰ型の半導体装置の製造方法では、次のような課題
があった。即ち、図２（ｂ）の工程において、半導体ウ
エハ１の表面全体にエポキシ樹脂５を加熱して溶融した
後、硬化させている。このため、半導体ウエハ１とエポ
キシ樹脂５の熱膨張率の相違により半導体ウエハ１に反
りが発生し、半導体ウエハ１にひび割れが生じたり、そ
の後の図２（ｃ）の工程においてヴィアポスト４を封止
樹脂面に均一に露出させることが困難になるという課題
があった。However, the conventional method for manufacturing a CSP type semiconductor device has the following problems. That is, in the step of FIG. 2B, the epoxy resin 5 is heated and melted on the entire surface of the semiconductor wafer 1 and then cured. Therefore, the semiconductor wafer 1 is warped due to the difference in thermal expansion coefficient between the semiconductor wafer 1 and the epoxy resin 5, the semiconductor wafer 1 is cracked, and the via post 4 is sealed in the subsequent step of FIG. 2C. There is a problem that it becomes difficult to uniformly expose the resin surface.
【０００６】また、封止後は半導体ウエハ１の表面がエ
ポキシ樹脂５によって覆われるので、図２（ｅ）の工程
で個片の認識が困難となり、誤った箇所で切断するおそ
れがあるという課題があった。本発明は、前記従来技術
が持っていた課題を解決し、樹脂封止後の変形が少な
く、切断時に個片を容易に認識することができる半導体
装置の製造方法を提供するものである。Further, since the surface of the semiconductor wafer 1 is covered with the epoxy resin 5 after the sealing, it is difficult to recognize the individual pieces in the step of FIG. was there. The present invention provides a method for manufacturing a semiconductor device, which solves the problems of the above-mentioned conventional techniques, has a small amount of deformation after resin encapsulation, and can easily recognize individual pieces during cutting.
【０００７】[0007]
【課題を解決するための手段】前記課題を解決するため
に、本発明の内の第１の発明は、半導体装置の製造方法
において、次のような工程を順次行っている。まず、半
導体ウエハ表面の回路形成面に形成された複数の集積回
路中の外部接続電極上に、所定の厚さの層間接続用のヴ
ィアポストを形成するヴィアポスト形成工程と、前記半
導体ウエハの裏面で前記複数の集積回路の境界線に対応
する位置に、所定の深さの溝を形成する境界溝形成工程
とを行う。In order to solve the above-mentioned problems, the first invention of the present invention sequentially performs the following steps in a method for manufacturing a semiconductor device. First, a via post forming step of forming via posts for interlayer connection having a predetermined thickness on external connection electrodes in a plurality of integrated circuits formed on a circuit formation surface of a semiconductor wafer surface, and a back surface of the semiconductor wafer. Then, a boundary groove forming step of forming a groove having a predetermined depth at a position corresponding to a boundary line of the plurality of integrated circuits is performed.
【０００８】次に、前記複数の集積回路の境界線に対応
する位置に所定の高さの凸部が設けられた封止金型を用
いて前記半導体ウエハの回路形成面を封止樹脂で封止
し、集積回路区分用の溝を有する樹脂封止面を形成する
溝付樹脂封止工程と、前記半導体ウエハの樹脂封止面を
研磨して前記ヴィアポストを露出させる研磨工程とを行
う。更に、前記研磨工程によって露出されたヴィアポス
ト上に接続用の導電層を形成する導電層形成工程を行
い、そして、前記溝付樹脂封止工程で形成された樹脂封
止面の溝に沿って前記半導体ウエハを切断して個々の半
導体装置に分割する切断工程を行う。Next, the circuit forming surface of the semiconductor wafer is sealed with a sealing resin by using a sealing die in which a convex portion having a predetermined height is provided at a position corresponding to a boundary line of the plurality of integrated circuits. Then, a grooved resin sealing step of forming a resin sealing surface having a groove for dividing an integrated circuit and a polishing step of polishing the resin sealing surface of the semiconductor wafer to expose the via post are performed. Further, a conductive layer forming step of forming a conductive layer for connection on the via post exposed by the polishing step is performed, and along the groove of the resin sealing surface formed in the grooved resin sealing step. A cutting step of cutting the semiconductor wafer into individual semiconductor devices is performed.
【０００９】第１の発明によれば、以上のように半導体
装置の製造方法を構成したので、次のような作用が行わ
れる。ヴィアポスト形成工程により、半導体ウエハ表面
上の外部接続電極に層間接続用のヴィアポストが形成さ
れ、境界溝形成工程により、この半導体ウエハ裏面で集
積回路の境界線に対応する箇所に所定の深さの溝が形成
される。溝付樹脂封止工程により、半導体ウエハ表面に
集積回路区分用の溝を有する樹脂封止面が形成され、研
磨工程により、前記ヴィアポストが露出するまで、樹脂
封止面の研磨が行われる。導電層形成処理により、ヴィ
アポスト上に接続用の導電層が形成された後、切断工程
により、樹脂封止面の溝に沿って半導体ウエハが切断さ
れ、個々の半導体装置に分割される。According to the first aspect of the present invention, since the method of manufacturing a semiconductor device is configured as described above, the following operation is performed. The via post formation step forms via posts for interlayer connection on the external connection electrodes on the semiconductor wafer surface, and the boundary groove formation step forms a predetermined depth on the back surface of the semiconductor wafer at a position corresponding to the boundary line of the integrated circuit. Grooves are formed. The grooved resin sealing step forms a resin sealing surface having grooves for dividing integrated circuits on the surface of the semiconductor wafer, and the polishing step polishes the resin sealing surface until the via posts are exposed. After the conductive layer for connection is formed on the via post by the conductive layer forming process, the semiconductor wafer is cut along the groove of the resin sealing surface and divided into individual semiconductor devices by the cutting step.
【００１０】第２の発明は、半導体装置の製造方法にお
いて、次のような工程を順次行っている。まず、第１の
発明と同様のヴィアポスト形成工程と、境界溝形成工程
と、溝付樹脂封止工程とを行う。次に、前記半導体ウエ
ハの樹脂封止面の所定の位置にレーザを照射して前記ヴ
ィアポストを露出させるヴィアポスト露出工程と、前記
ヴィアポスト露出工程によって露出されたヴィアポスト
上に接続用の導電層を形成する導電層形成工程とを行
う。そして、第１の発明と同様の切断工程を行う。第２
の発明によれば、ヴィアポスト露出工程において、半導
体ウエハの樹脂封止面の所定の位置にレーザが照射さ
れ、前記ヴィアポストが露出される。その他の作用は、
第１の発明と同様である。According to a second aspect of the invention, in the method of manufacturing a semiconductor device, the following steps are sequentially performed. First, the same via post forming step, boundary groove forming step, and grooved resin sealing step as in the first aspect of the invention are performed. Next, a via post exposure step of exposing the via post by irradiating a predetermined position on the resin sealing surface of the semiconductor wafer, and a conductive layer for connection on the via post exposed by the via post exposure step. And a conductive layer forming step of forming a layer. Then, a cutting step similar to that of the first invention is performed. Second
According to the invention, in the via post exposing step, a laser is applied to a predetermined position on the resin sealing surface of the semiconductor wafer to expose the via post. Other actions are
It is similar to the first invention.
【００１１】第３の発明は、半導体装置の製造方法にお
いて、次のような工程を順次行っている。まず、半導体
ウエハ表面の回路形成面に形成された複数の集積回路中
の外部接続電極上に層間接続用のヴィアポストを、及び
該複数の集積回路の境界線上に境界識別用の境界ポスト
をそれぞれ形成するポスト形成工程と、第１の発明と同
様の境界溝形成工程とを行う。次に、前記半導体ウエハ
の回路形成面を封止樹脂で封止して樹脂封止面を形成す
る樹脂封止工程と、前記半導体ウエハの樹脂封止面を研
磨して前記ヴィアポスト及び境界ポストを露出させる研
磨工程とを行う。更に、第１の発明と同様の導電層形成
工程を行い、そして、前記研磨工程によって露出された
境界ポストに基づいて前記半導体ウエハを切断して個々
の半導体装置に分割する切断工程とを行う。According to a third aspect of the invention, in the method of manufacturing a semiconductor device, the following steps are sequentially performed. First, via posts for interlayer connection are provided on external connection electrodes in a plurality of integrated circuits formed on a circuit formation surface of a semiconductor wafer surface, and boundary posts for boundary identification are provided on boundaries of the plurality of integrated circuits. A post forming step for forming and a boundary groove forming step similar to the first invention are performed. Next, a resin sealing step of sealing the circuit forming surface of the semiconductor wafer with a sealing resin to form a resin sealing surface, and polishing the resin sealing surface of the semiconductor wafer to form the via post and the boundary post. And a polishing step for exposing the film. Further, a conductive layer forming step similar to that of the first invention is performed, and a cutting step of cutting the semiconductor wafer based on the boundary posts exposed by the polishing step to divide the semiconductor wafer into individual semiconductor devices is performed.
【００１２】第３の発明によれば、次のような作用が行
われる。ポスト形成工程により、半導体ウエハ表面上の
外部接続電極に層間接続用のヴィアポストが形成される
と共に、集積回路の境界線上に境界ポストが形成され、
境界溝形成工程により、この半導体ウエハ裏面で集積回
路の境界線に対応する箇所に所定の深さの溝が形成され
る。溝付樹脂封止工程により、半導体ウエハ表面に集積
回路区分用の溝を有する樹脂封止面が形成され、研磨工
程により、前記ヴィアポスト及び境界ポストが露出する
まで樹脂封止面の研磨が行われる。導電層形成処理によ
り、ヴィアポスト上に接続用の導電層が形成された後、
切断工程により、境界ポストに基づいて半導体ウエハが
切断され、個々の半導体装置に分割される。According to the third invention, the following operation is performed. By the post forming step, via posts for interlayer connection are formed on the external connection electrodes on the surface of the semiconductor wafer, and boundary posts are formed on the boundary lines of the integrated circuit.
By the boundary groove forming step, a groove having a predetermined depth is formed on the back surface of the semiconductor wafer at a position corresponding to the boundary line of the integrated circuit. The grooved resin encapsulation process forms a resin encapsulation surface having grooves for dividing integrated circuits on the semiconductor wafer surface, and the polishing process polishes the resin encapsulation surface until the via posts and boundary posts are exposed. Be seen. After the conductive layer for connection is formed on the via post by the conductive layer forming process,
By the cutting process, the semiconductor wafer is cut based on the boundary posts and divided into individual semiconductor devices.
【００１３】[0013]
【発明の実施の形態】第１の実施形態
図１（ａ）〜（ｆ）は本発明の第１の実施形態を示すＣ
ＳＰ型の半導体装置の製造工程図、及び図３（ａ）〜
（ｃ）は図１の詳細を示す説明図であり、図２（ａ）〜
（ｅ）中の要素と共通の要素には共通の符号が付されて
いる。以下、これらの図１（ａ）〜（ｆ）及び図３
（ａ）〜（ｃ）を参照しつつ、このＣＳＰ型の半導体装
置の製造方法の工程（１）〜（６）を説明する。BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIGS. 1A to 1F show a first embodiment C of the present invention.
Manufacturing process drawing of the SP type semiconductor device, and FIG.
(C) is an explanatory view showing the details of FIG. 1, and FIG.
Elements common to the elements in (e) are assigned common reference numerals. Hereinafter, these FIG. 1 (a)-(f) and FIG.
The steps (1) to (6) of the method for manufacturing the CSP type semiconductor device will be described with reference to (a) to (c).
【００１４】（１） ヴィアポスト形成工程
図１（ａ）に示すように、例えば直径約２０ｃｍ、厚さ
３５０μｍの半導体ウエハ１の表面（回路形成面）に、
薄膜形成、不純物添加、及び微細加工等のウエハ処理を
順次施し、複数の同一パターンの集積回路２を形成す
る。各集積回路２は、例えば、縦及び横の寸法が５ｍｍ
の矩形に形成され、これらが半導体ウエハ１の上に縦及
び横方向に整然と並んで配置される。各集積回路２は、
外部接続用の複数の電極３を有しており、これらの複数
の電極３上に、例えば銅めっき等を施し、直径１００μ
ｍ、厚さ１５０μｍ程度の層間接続用のヴィアポスト４
を形成する。これにより、図３（ａ）に示すような表面
を有する半導体ウエハ１が形成される。(1) Via Post Forming Step As shown in FIG. 1A, for example, on the surface (circuit forming surface) of a semiconductor wafer 1 having a diameter of about 20 cm and a thickness of 350 μm,
Wafer processing such as thin film formation, impurity addition, and microfabrication is sequentially performed to form a plurality of integrated circuits 2 having the same pattern. Each integrated circuit 2 has, for example, a vertical and horizontal dimension of 5 mm.
Of rectangular shape, and these are arranged on the semiconductor wafer 1 in orderly in the vertical and horizontal directions. Each integrated circuit 2
It has a plurality of electrodes 3 for external connection. For example, copper plating is applied on these plurality of electrodes 3 to obtain a diameter of 100 μm.
m, thickness 150 μm, via post 4 for interlayer connection
To form. As a result, the semiconductor wafer 1 having the surface as shown in FIG. 3A is formed.
【００１５】（２） 境界溝形成工程
図１（ｂ）に示すように、例えば切削用ブレード１７を
用いて、半導体ウエハ１の裏面に複数の集積回路２の境
界線に対応する境界溝７を形成する。これにより、半導
体ウエハ１の裏面に、図３（ｂ）に示すような幅１１０
μｍ、深さ１５０μｍ程度の溝が縦横方向に形成され
る。(2) Boundary Groove Forming Step As shown in FIG. 1B, a boundary groove 7 corresponding to the boundary lines of a plurality of integrated circuits 2 is formed on the back surface of the semiconductor wafer 1 by using, for example, a cutting blade 17. Form. As a result, the width 110 on the back surface of the semiconductor wafer 1 as shown in FIG.
Grooves with a depth of about 150 μm are formed in the vertical and horizontal directions.
【００１６】（３） 溝付樹脂封止工程
ヴィアポスト４、及び境界溝７が形成された半導体ウエ
ハ１を、図１（ｃ）に示すように、表面を上にして下金
型１１の上に配置し、その上に所定量の封止用のエポキ
シ樹脂５を供給する。エポキシ樹脂５の上から、各集積
回路２の境界線に対応する位置に、例えば幅１１０μｍ
程度で、所定の高さの凸部１２ａが設けられた上金型１
２Ａを圧接して加熱する。これにより、加熱溶融された
エポキシ樹脂５が半導体ウエハ１の表面に圧着され、凸
部１２ａに対応して集積回路区分用の区分溝８を有する
樹脂封止面が形成される。ここで、上金型１２Ａの凸部
１２ａの高さは、区分溝８の底がヴィアポスト４の頭部
よりも低くなるような寸法に構成されている。(3) Grooved Resin Sealing Process As shown in FIG. 1C, the semiconductor wafer 1 having the via post 4 and the boundary groove 7 formed thereon is placed on the lower die 11 with the surface upward. , And a predetermined amount of the epoxy resin 5 for sealing is supplied thereon. At a position corresponding to the boundary line of each integrated circuit 2 from above the epoxy resin 5, for example, a width of 110 μm
The upper die 1 provided with a convex portion 12a having a predetermined height.
2A is pressed and heated. As a result, the heat-melted epoxy resin 5 is pressure-bonded to the surface of the semiconductor wafer 1, and a resin sealing surface having the dividing grooves 8 for dividing the integrated circuit is formed corresponding to the convex portions 12a. Here, the height of the convex portion 12a of the upper mold 12A is set to a dimension such that the bottom of the partition groove 8 is lower than the head of the via post 4.
【００１７】（４） 研磨工程
エポキシ樹脂５による封止が施された半導体ウエハ１
を、金型１１，１２Ａから取り出し、図１（ｄ）に示す
ように、接着テープ１３によって研磨台１４に固定す
る。そして、ヴィアポスト４が露出するまでグラインダ
１５で樹脂封止面を一様に研磨する。これにより、図３
（ｃ）に示すように、半導体ウエハ１の樹脂封止面に
は、区分溝８で区分された各集積回路２のヴィアポスト
４が現れる。(4) Polishing step Semiconductor wafer 1 sealed with epoxy resin 5
Is taken out from the molds 11 and 12A, and is fixed to the polishing table 14 by the adhesive tape 13 as shown in FIG. 1 (d). Then, the resin sealing surface is uniformly polished by the grinder 15 until the via post 4 is exposed. As a result, FIG.
As shown in (c), the via post 4 of each integrated circuit 2 sectioned by the sectioning groove 8 appears on the resin sealing surface of the semiconductor wafer 1.
【００１８】（５） 導電層形成工程
図１（ｅ）に示すように、樹脂封止面が研磨されて露出
したヴィアポスト４の上に、例えば半田バンプ６等の接
続用の導電層を形成する。
（６） 切断工程
図１（ｆ）に示すように、半導体ウエハ１上に並んだ複
数の集積回路２を、例えば幅１１０μｍのダイシングブ
レード１６を用い、樹脂封止面の区分溝８に沿って、縦
及び横方向に切断する。これによって、半導体ウエハ１
上の各集積回路２は個片に分割され、ＣＳＰ型の半導体
装置１０が完成する。(5) Conductive Layer Forming Step As shown in FIG. 1E, a conductive layer for connection such as a solder bump 6 is formed on the via post 4 exposed by polishing the resin sealing surface. To do. (6) Cutting Process As shown in FIG. 1 (f), the plurality of integrated circuits 2 arranged on the semiconductor wafer 1 are cut along the dividing grooves 8 on the resin sealing surface by using, for example, a dicing blade 16 having a width of 110 μm. Cut vertically and horizontally. As a result, the semiconductor wafer 1
Each integrated circuit 2 above is divided into individual pieces, and the CSP type semiconductor device 10 is completed.
【００１９】以上のように、この第１の実施形態のＣＳ
Ｐ型の半導体装置の製造方法では、集積回路２の境界線
に合わせて半導体ウエハ１の裏面に境界溝７を形成する
境界溝形成工程と、集積回路２の区分溝８を形成するた
めの凸部１２ａを有する上金型１２Ａを用いて樹脂封止
面を形成する溝付樹脂封止工程とを行っている。これに
より、半導体ウエハ１とエポキシ樹脂５の熱膨張率の相
違による反りが緩和され、樹脂封止後の変形が少ないと
いう利点がある。更に、研磨工程後に、樹脂封止面に区
分溝８が残るので、切断工程において各集積回路２に対
応する個片を容易に認識することができるという利点が
ある。As described above, the CS of the first embodiment is
In the method of manufacturing a P-type semiconductor device, a boundary groove forming step of forming a boundary groove 7 on the back surface of the semiconductor wafer 1 in accordance with the boundary line of the integrated circuit 2 and a convex for forming the dividing groove 8 of the integrated circuit 2. A grooved resin encapsulation step of forming a resin encapsulation surface using the upper mold 12A having the portion 12a is performed. As a result, there is an advantage that the warp due to the difference in the coefficient of thermal expansion between the semiconductor wafer 1 and the epoxy resin 5 is alleviated and the deformation after the resin sealing is small. Further, since the dividing groove 8 remains on the resin sealing surface after the polishing step, there is an advantage that the individual piece corresponding to each integrated circuit 2 can be easily recognized in the cutting step.
【００２０】第２の実施形態
図４（ａ）〜（ｆ）は、本発明の第２の実施形態を示す
ＣＳＰ型の半導体装置の製造工程図であり、図１（ａ）
〜（ｆ）中の要素と共通の要素には共通の符号が付され
ている。以下、この図４（ａ）〜（ｆ）を参照しつつ、
このＣＳＰ型の半導体装置の製造方法の工程（１）〜
（６）を説明する。 Second Embodiment FIGS. 4A to 4F are manufacturing process drawings of a CSP type semiconductor device showing a second embodiment of the present invention, and FIG.
Elements common to the elements in (f) to (f) are designated by common reference numerals. Hereinafter, referring to FIGS. 4 (a) to 4 (f),
Steps (1) to (1) of the method for manufacturing the CSP type semiconductor device
(6) will be described.
【００２１】（１） ポスト形成工程
図４（ａ）に示すように、半導体ウエハ１における各集
積回路２の複数の電極３上に、第１の実施形態と同様の
層間接続用のヴィアポスト４を形成するとともに、これ
らの集積回路２の縦及び横の境界線の交差箇所に、例え
ば銅めっき等を施し、直径２００μｍ、厚さ１５０μｍ
程度の境界識別用の境界ポスト９を形成する。
（２） 境界溝形成工程
図４（ｂ）に示すように、第１の実施形態と同様の境界
溝形成工程を行う。(1) Post Forming Process As shown in FIG. 4A, the via post 4 for interlayer connection similar to that of the first embodiment is formed on the plurality of electrodes 3 of each integrated circuit 2 in the semiconductor wafer 1. Is formed, and at the intersections of the vertical and horizontal boundary lines of these integrated circuits 2, for example, copper plating or the like is performed to have a diameter of 200 μm and a thickness of 150 μm.
A boundary post 9 is formed to identify the boundary. (2) Boundary Groove Forming Step As shown in FIG. 4B, the same boundary groove forming step as in the first embodiment is performed.
【００２２】（３） 樹脂封止工程
ヴィアポスト４、境界ポスト９、及び境界溝７が形成さ
れた半導体ウエハ１を、図４（ｃ）に示すように、表面
を上にして下金型１１の上に配置し、その上に所定量の
封止用のエポキシ樹脂５を供給する。エポキシ樹脂５の
上から、上金型１２を圧接して加熱する。これにより、
加熱溶融されたエポキシ樹脂５が半導体ウエハ１の表面
に圧着され、樹脂封止面が形成される。
（４） 研磨工程
エポキシ樹脂５による封止が施された半導体ウエハ１
を、金型１１，１２から取り出し、図４（ｄ）に示すよ
うに、接着テープ１３によって研磨台１４に固定する。
そして、ヴィアポスト４、及び境界ポスト９が露出する
までグラインダ１５で樹脂封止面を一様に研磨する。(3) Resin Encapsulation Step The semiconductor wafer 1 having the via post 4, the boundary post 9, and the boundary groove 7 formed thereon, as shown in FIG. And a predetermined amount of the epoxy resin 5 for sealing is supplied thereon. The upper die 12 is pressed against the epoxy resin 5 and heated. This allows
The heat-melted epoxy resin 5 is pressure-bonded to the surface of the semiconductor wafer 1 to form a resin sealing surface. (4) Polishing step Semiconductor wafer 1 sealed with epoxy resin 5
Is taken out from the molds 11 and 12, and is fixed to the polishing table 14 with the adhesive tape 13 as shown in FIG.
Then, the resin sealing surface is uniformly polished by the grinder 15 until the via post 4 and the boundary post 9 are exposed.
【００２３】（５） 導電層形成工程
図４（ｅ）に示すように、樹脂封止面が研磨されて露出
したヴィアポスト４の上に、例えば半田バンプ６等の接
続用の導電層を形成する。
（６） 切断工程
図４（ｆ）に示すように、半導体ウエハ１上に並んだ複
数の集積回路２を、例えば幅１１０μｍのダイシングブ
レード１６を用い、樹脂封止面に現れた境界ポスト９に
従って、縦及び横方向に切断する。これによって、半導
体ウエハ１上の各集積回路２は個片に分割され、ＣＳＰ
型の半導体装置１０が完成する。(5) Conductive Layer Forming Step As shown in FIG. 4E, a conductive layer for connection such as a solder bump 6 is formed on the via post 4 exposed by polishing the resin sealing surface. To do. (6) Cutting Process As shown in FIG. 4 (f), the plurality of integrated circuits 2 arranged on the semiconductor wafer 1 are processed in accordance with the boundary posts 9 appearing on the resin sealing surface using a dicing blade 16 having a width of 110 μm, for example. Cut vertically and horizontally. As a result, each integrated circuit 2 on the semiconductor wafer 1 is divided into individual pieces,
Die semiconductor device 10 is completed.
【００２４】以上のように、この第２の実施形態のＣＳ
Ｐ型の半導体装置の製造方法では、集積回路２の境界線
に合わせて半導体ウエハ１の裏面に境界溝７を形成する
境界溝形成工程を行っている。これにより、半導体ウエ
ハ１とエポキシ樹脂５の熱膨張率の相違による応力が緩
和され、樹脂封止後の変形が少ないという利点がある。
更に、ポスト形成工程においてヴィアポスト４に加えて
境界識別用の境界ポスト９を形成している。これによ
り、研磨工程後に樹脂封止面に境界ポスト９が現れるの
で、切断工程において各集積回路２に対応する個片を容
易に認識することができるという利点がある。As described above, the CS of the second embodiment is
In the method of manufacturing a P-type semiconductor device, a boundary groove forming step of forming a boundary groove 7 on the back surface of the semiconductor wafer 1 in accordance with the boundary line of the integrated circuit 2 is performed. As a result, the stress due to the difference in the thermal expansion coefficient between the semiconductor wafer 1 and the epoxy resin 5 is relieved, and there is an advantage that the deformation after the resin sealing is small.
Further, in the post forming step, in addition to the via post 4, a boundary post 9 for boundary identification is formed. Thereby, since the boundary post 9 appears on the resin sealing surface after the polishing step, there is an advantage that the individual piece corresponding to each integrated circuit 2 can be easily recognized in the cutting step.
【００２５】なお、本発明は、上記実施形態に限定され
ず、種々の変形が可能である。この変形例としては、例
えば、次の（ａ）〜（ｃ）のようなものがある。
（ａ） 第１の実施形態における研磨工程では、ヴィア
ポスト４が露出するまで樹脂封止面を一様に研磨してい
るが、この研磨工程に代えて、所定の位置にレーザを照
射してエポキシ樹脂５を焼き切り、これらのヴィアポス
ト４を露出させるヴィアポスト露出工程を行っていも良
い。これにより、研磨工程による半導体ウエハ１へ圧力
を回避することができるので、ひび割れ等による破損を
防止することができるという利点がある。The present invention is not limited to the above embodiment, and various modifications can be made. Examples of this modification include the following (a) to (c). (A) In the polishing step in the first embodiment, the resin sealing surface is uniformly polished until the via post 4 is exposed. Instead of this polishing step, laser is irradiated to a predetermined position. It is also possible to burn out the epoxy resin 5 and perform a via post exposure step of exposing these via posts 4. As a result, it is possible to avoid pressure on the semiconductor wafer 1 due to the polishing process, and there is an advantage that damage due to cracks or the like can be prevented.
【００２６】（ｂ） 第２の実施形態における樹脂封止
工程では、凸部の無い平らな上金型１２を用いてエポキ
シ樹脂５を圧着しているが、第１の実施形態における溝
付樹脂封止工程と同様に、凸部１２ａが設けられた上金
型１２Ａを用いて区分溝８の付いた樹脂封止面を形成す
るようにしても良い。これにより、半導体ウエハ１とエ
ポキシ樹脂５の熱膨張率の相違による応力を、更に緩和
することができるという利点がある。
（ｃ） 第２の実施形態におけるポスト形成工程では、
集積回路２の縦及び横の境界線の交差箇所に境界ポスト
９を形成しているが、境界ポスト９の位置は境界線の交
差箇所に限定されず、例えば交差箇所の中間等で、この
境界線を識別することができる位置であればどこでも良
い。(B) In the resin sealing step of the second embodiment, the epoxy resin 5 is pressure-bonded by using the flat upper die 12 having no convex portion. However, the grooved resin of the first embodiment is used. Similar to the sealing step, the upper mold 12A provided with the convex portion 12a may be used to form the resin sealing surface with the dividing groove 8. This has the advantage that the stress due to the difference in the coefficient of thermal expansion between the semiconductor wafer 1 and the epoxy resin 5 can be further alleviated. (C) In the post forming step in the second embodiment,
Although the boundary posts 9 are formed at the intersections of the vertical and horizontal boundary lines of the integrated circuit 2, the position of the boundary posts 9 is not limited to the intersections of the boundary lines. It may be anywhere as long as the line can be identified.
【００２７】[0027]
【発明の効果】以上詳細に説明したように、第１の発明
によれば、半導体ウエハの裏面に集積回路の境界線に対
応する所定の深さの溝を形成する境界溝形成工程と、半
導体ウエハの回路形成面に集積回路区分用の溝を有する
樹脂封止面を形成する溝付樹脂封止工程とを行うように
している。これにより、半導体ウエハと封止樹脂の熱膨
張率の相違による反りが緩和され、樹脂封止後の変形が
少ないという効果がある。更に、研磨工程後に、樹脂封
止面に区分用の溝が残るので、切断工程において個片を
容易に認識することができるという効果がある。As described in detail above, according to the first invention, a boundary groove forming step of forming a groove having a predetermined depth corresponding to a boundary line of an integrated circuit on the back surface of a semiconductor wafer, and a semiconductor A grooved resin sealing step of forming a resin sealing surface having a groove for dividing an integrated circuit on the circuit forming surface of the wafer is performed. As a result, warpage due to the difference in thermal expansion coefficient between the semiconductor wafer and the sealing resin is mitigated, and there is an effect that deformation after resin sealing is small. Further, since the dividing groove remains on the resin sealing surface after the polishing step, the individual pieces can be easily recognized in the cutting step.
【００２８】第２の発明によれば、第１の発明と同様の
境界溝形成工程と、溝付樹脂封止工程とを行うようにし
ている。これにより、第１の発明と同様の効果がある。
更に、半導体ウエハの樹脂封止面の所定の位置にレーザ
を照射してヴィアポストを露出させるヴィアポスト露出
工程を行うので、研磨等によってヴィアポストを露出さ
せる場合に比べて、半導体ウエハへ圧力を回避すること
が可能になり、ひび割れ等による破損を防止することが
できるという効果がある。According to the second invention, the boundary groove forming step and the grooved resin sealing step similar to those of the first invention are performed. Thereby, the same effect as the first aspect of the invention can be obtained.
Further, since the via post exposure process of exposing the via posts by irradiating a laser to a predetermined position on the resin-sealed surface of the semiconductor wafer is performed, pressure is applied to the semiconductor wafer as compared with the case where the via posts are exposed by polishing or the like. It is possible to avoid it, and it is possible to prevent damage due to cracking or the like.
【００２９】第３の発明によれば、半導体ウエハの裏面
に集積回路の境界線に対応する所定の深さの溝を形成す
る境界溝形成工程を行うようにしている。これにより、
半導体ウエハと封止樹脂の熱膨張率の相違による反りが
緩和され、樹脂封止後の変形が少ないという効果があ
る。更に、半導体ウエハ表面に、ヴィアポストと共に集
積回路の境界識別用の境界ポストを形成するポスト形成
工程を行っている。このため、研磨工程によって樹脂封
止面に境界ポストが現れるので、切断工程において各集
積回路に対応する個片を容易に認識することができると
いう効果がある。According to the third aspect of the invention, the boundary groove forming step of forming a groove having a predetermined depth corresponding to the boundary line of the integrated circuit is performed on the back surface of the semiconductor wafer. This allows
There is an effect that warpage due to the difference in thermal expansion coefficient between the semiconductor wafer and the sealing resin is alleviated and the deformation after the resin sealing is small. Further, a post forming step is performed on the surface of the semiconductor wafer to form a boundary post for identifying the boundary of the integrated circuit together with the via post. Therefore, since the boundary post appears on the resin sealing surface in the polishing step, there is an effect that the individual piece corresponding to each integrated circuit can be easily recognized in the cutting step.
【図１】本発明の第１の実施形態を示すＣＳＰ型の半導
体装置の製造工程図である。FIG. 1 is a manufacturing process diagram of a CSP type semiconductor device showing a first embodiment of the present invention.
【図２】従来のＣＳＰ型の半導体装置の製造工程図であ
る。FIG. 2 is a manufacturing process diagram of a conventional CSP type semiconductor device.
【図３】図１の詳細を示す説明図である。FIG. 3 is an explanatory diagram showing details of FIG.
【図４】本発明の第２の実施形態を示すＣＳＰ型の半導
体装置の製造工程図である。FIG. 4 is a manufacturing process diagram of a CSP type semiconductor device showing a second embodiment of the present invention.
１ 半導体ウエハ ２ 集積回路 ３ 電極 ４ ヴィアポスト ５ エポキシ樹脂 ６ 半田バンプ ７ 境界溝 ８ 区分溝 ９ 境界ポスト １０ 半導体装置 １１，１２，１２Ａ 金型 1 Semiconductor wafer 2 integrated circuits 3 electrodes 4 Via Post 5 Epoxy resin 6 Solder bump 7 boundary groove 8 division grooves 9 boundary post 10 Semiconductor device 11,12,12A mold
Claims (3)
れた複数の集積回路中の外部接続電極上に、所定の厚さ
の層間接続用のヴィアポストを形成するヴィアポスト形
成工程と、 前記半導体ウエハの裏面で前記複数の集積回路の境界線
に対応する位置に、所定の深さの溝を形成する境界溝形
成工程と、 前記複数の集積回路の境界線に対応する位置に所定の高
さの凸部が設けられた封止金型を用いて前記半導体ウエ
ハの回路形成面を封止樹脂で封止し、集積回路区分用の
溝を有する樹脂封止面を形成する溝付樹脂封止工程と、 前記半導体ウエハの樹脂封止面を研磨して前記ヴィアポ
ストを露出させる研磨工程と、 前記研磨工程によって露出されたヴィアポスト上に接続
用の導電層を形成する導電層形成工程と、 前記溝付樹脂封止工程で形成された樹脂封止面の溝に沿
って前記半導体ウエハを切断して個々の半導体装置に分
割する切断工程とを、 順次行うことを特徴とする半導体装置の製造方法。1. A via post forming step of forming a via post for interlayer connection having a predetermined thickness on an external connection electrode in a plurality of integrated circuits formed on a circuit formation surface of a semiconductor wafer surface, said semiconductor A boundary groove forming step of forming a groove having a predetermined depth on the back surface of the wafer at a position corresponding to the boundary line of the plurality of integrated circuits; and a predetermined height at a position corresponding to the boundary line of the plurality of integrated circuits. Grooved resin encapsulation for encapsulating the circuit forming surface of the semiconductor wafer with an encapsulating resin using an encapsulating mold provided with convex portions A step of polishing the resin-sealed surface of the semiconductor wafer to expose the via posts, and a conductive layer forming step of forming a conductive layer for connection on the via posts exposed by the polishing step, Formed in the grooved resin sealing process Method of manufacturing a semiconductor device and a cutting step along the groove of the resin sealing surface by cutting the semiconductor wafer is divided into individual semiconductor devices, and carrying out sequentially a.
れた複数の集積回路中の外部接続電極上に、所定の厚さ
の層間接続用のヴィアポストを形成するヴィアポスト形
成工程と、 前記半導体ウエハの裏面で前記複数の集積回路の境界線
に対応する位置に、所定の深さの溝を形成する境界溝形
成工程と、 前記複数の集積回路の境界線に対応する位置に所定の高
さの凸部が設けられた封止金型を用いて前記半導体ウエ
ハの回路形成面を封止樹脂で封止し、集積回路区分用の
溝を有する樹脂封止面を形成する溝付樹脂封止工程と、 前記半導体ウエハの樹脂封止面の所定の位置にレーザを
照射して前記ヴィアポストを露出させるヴィアポスト露
出工程と、 前記ヴィアポスト露出工程によって露出されたヴィアポ
スト上に接続用の導電層を形成する導電層形成工程と、 前記溝付樹脂封止工程で形成された樹脂封止面の溝に沿
って前記半導体ウエハを切断して個々の半導体装置に分
割する切断工程とを、 順次行うことを特徴とする半導体装置の製造方法。2. A via post forming step of forming a via post for interlayer connection having a predetermined thickness on an external connection electrode in a plurality of integrated circuits formed on a circuit formation surface of a semiconductor wafer surface, said semiconductor A boundary groove forming step of forming a groove having a predetermined depth on the back surface of the wafer at a position corresponding to the boundary line of the plurality of integrated circuits; and a predetermined height at a position corresponding to the boundary line of the plurality of integrated circuits. Grooved resin encapsulation for encapsulating the circuit forming surface of the semiconductor wafer with an encapsulating resin using an encapsulating mold provided with convex portions A step of exposing the via posts by irradiating a predetermined position on the resin-sealed surface of the semiconductor wafer with a laser, and a conductive layer for connection on the via posts exposed by the via post exposure step. Guide forming layers Characterized in that a layer forming step and a cutting step of cutting the semiconductor wafer along the grooves of the resin-sealed surface formed in the grooved resin-sealing step to divide the semiconductor wafer into individual semiconductor devices are performed sequentially. Of manufacturing a semiconductor device.
れた複数の集積回路中の外部接続電極上に層間接続用の
ヴィアポストを、及び該複数の集積回路の境界線上に境
界識別用の境界ポストをそれぞれ形成するポスト形成工
程と、 前記半導体ウエハの裏面で前記複数の集積回路の境界線
に対応する位置に、所定の深さの溝を形成する境界溝形
成工程と、 前記半導体ウエハの回路形成面を封止樹脂で封止して樹
脂封止面を形成する樹脂封止工程と、 前記半導体ウエハの樹脂封止面を研磨して前記ヴィアポ
スト及び境界ポストを露出させる研磨工程と、 前記研磨工程によって露出されたヴィアポスト上に接続
用の導電層を形成する導電層形成工程と、 前記研磨工程によって露出された境界ポストに基づいて
前記半導体ウエハを切断して個々の半導体装置に分割す
る切断工程とを、 順次行うことを特徴とする半導体装置の製造方法。3. A via post for interlayer connection on an external connection electrode in a plurality of integrated circuits formed on a circuit formation surface of a semiconductor wafer surface, and a boundary for boundary identification on a boundary line of the plurality of integrated circuits. A post forming step of forming respective posts; a boundary groove forming step of forming a groove having a predetermined depth at a position corresponding to a boundary line of the plurality of integrated circuits on the back surface of the semiconductor wafer; and a circuit of the semiconductor wafer A resin sealing step of sealing the formation surface with a sealing resin to form a resin sealing surface; a polishing step of polishing the resin sealing surface of the semiconductor wafer to expose the via post and the boundary post; A conductive layer forming step of forming a conductive layer for connection on the via posts exposed by the polishing step, and cutting the semiconductor wafer based on the boundary posts exposed by the polishing step to separate individual semiconductor wafers. Method of manufacturing a semiconductor device and a cutting step of dividing the body unit, and performs sequential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29924098A JP3425378B2 (en) | 1998-10-21 | 1998-10-21 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29924098A JP3425378B2 (en) | 1998-10-21 | 1998-10-21 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000124168A JP2000124168A (en) | 2000-04-28 |
| JP3425378B2 true JP3425378B2 (en) | 2003-07-14 |
Family
ID=17869972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29924098A Expired - Fee Related JP3425378B2 (en) | 1998-10-21 | 1998-10-21 | Method for manufacturing semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3425378B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4617559B2 (en) * | 2000-10-30 | 2011-01-26 | 富士電機システムズ株式会社 | Method for manufacturing power semiconductor device |
| US7034386B2 (en) | 2001-03-26 | 2006-04-25 | Nec Corporation | Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same |
| KR100856977B1 (en) | 2004-11-11 | 2008-09-04 | 야마하 가부시키가이샤 | Semiconductor device, semiconductor wafer, chip size package, and method of manufacturing and inspection therefor |
| JP4696595B2 (en) * | 2005-02-28 | 2011-06-08 | ヤマハ株式会社 | Semiconductor wafer, semiconductor element, and method for manufacturing semiconductor element |
| JP5259336B2 (en) * | 2008-10-23 | 2013-08-07 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP7313968B2 (en) | 2019-08-15 | 2023-07-25 | 株式会社ディスコ | Wafer processing method |
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1998
- 1998-10-21 JP JP29924098A patent/JP3425378B2/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| JP2000124168A (en) | 2000-04-28 |
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