JP3417765B2 - Optical character reader - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical character reader (hereinafter referred to as OCR) for optically reading and recognizing characters and symbols written or printed on a form, and more particularly, The present invention relates to an OCR image writing method and an image memory configuration.

[0002]

2. Description of the Related Art In OCR, an image memory is a dynamic random access memory (Dynamic Random Access Memory).
ss Memory (hereinafter referred to as DRAM), and is a memory that stores the image data acquired by the image input unit as a two-dimensional array. In the past, an image memory was configured by using a large number of small-capacity DRAMs, but in recent years, due to demands for reduction in power consumption and miniaturization, a large-capacity DRAM (for example, 16M bits) is used, and the number is as small as possible. Number D
It is necessary to configure the image memory with RAM. DRA
M determines the address by the column address and the row address and reads / writes the data. When reading with the same row address, setting the row address is not necessary, and reading is performed only by setting the column address. It is possible to read in the high-speed page mode. Further, in the DRAM, byte-by-byte access is possible, and the data bits of the data terminals are associated with the upper and lower columns of each byte. For example, when the data bits are 16 bits, the upper 8 bits are associated with the upper column area and the lower 8 bits are associated with the lower column area to form a 2CAS configuration. By configuring the image memory with the DRAM as described above, a flexible and efficient memory configuration can be obtained according to the purpose of the OCR to be used and device conditions, and from the viewpoint of image rotation, high-speed reading in each direction is possible. .

FIG. 2 is a block diagram of a conventional OCR. The OCR includes an image input unit 1, an analog / digital conversion (hereinafter referred to as A / D conversion) / level correction unit 2, a line memory control unit 3, line memories 4-1 and 4-2, an image memory 5, an image. memory control section 6, the scanning direction address counter 7 X, and includes a sub-scanning direction address counter 7Y, and the recognition control unit 8. The image input unit 1 is an optical
Or by mechanical scanning, it has a function of converting the print or handwritten character on the document into electric image signals. The A / D conversion / level correction unit 2 has a function of performing A / D conversion of an electric image signal from the image input unit 1 and normalizing a white level and a black level on a form. The line memories 4-1 and 4-2 absorb one line of data before writing to the image memory 5 in order to absorb the speed difference between the image acquisition of the image input unit 1 and the image writing to the image memory 5. Two speed buffer memories prepared for the purpose of buffering, and a function of writing / reading image data according to the write / read control signal input to the terminal WE and the terminal OE and the address input to the address terminal. have. The line memory controller 3 writes image data in the two line memories 4-1 and 4-2.
It has a function of controlling reading. The image memory 5 is a memory that stores, as a form image, image data that has been A / D converted and level-corrected and buffered as one line of data, and is composed of a DRAM.

The image memory control unit 6 includes a scanning direction address counter 7X and a sub-scanning direction address counter 7.
It has a function of controlling Y. The scanning direction address counter 7X and the sub-scanning direction address counter 7Y have a function of storing / incrementing two-dimensional coordinates for actual writing / reading of the image memory 5.
The recognition control unit 8 has a function of taking out image data from the image memory 5 and cutting out and recognizing characters. The operation of FIG. 2 will be described below. The character printed or handwritten on the form is converted into an electric image signal by the image input unit 1, and is converted by the A / D conversion / level correction unit 2.
It is converted into a digital signal, and the white / black level on the form is further normalized and written in the line memories 4-1 and 4-2. The line memory control unit 3 arbitrates writing and reading of image data in the two line memories 4-1 and 4-2 as follows. FIG. 3 is a diagram showing a conventional line memory control flow. As shown in FIG.
While writing image data for one line of main scanning to one line memory 4-1 (or 4-2), the image data is read from the other line memory 4-2 (or 4-1) to The image data is sent to 5. When both writing and reading for one line are completed, the writing side is switched to the reading side and the reading side is switched to the writing side, and the same operation is performed, and the image data for one screen of the form is sent to the image memory 5. In this way, the line memory control unit 3 controls the two line memories 4-1 and 4-2 by the toggle buffer.

FIG. 4 is a diagram showing writing to a conventional image memory using 16 M bits (10 bits for address, 16 bits for data). 5 (a) and 5 (b),
It is a figure which shows the write flow to the conventional image memory. As shown in FIGS. 4 and 5, in the image memory control unit 6, the image data of the odd-numbered lines read from the line memory 4-1 makes the terminal UCAS active at a low level (hereinafter referred to as “L”), Data terminal D
Image data of even lines read from the line memory 4-2 after being written from 15-D8 is output to the terminal LCA.
Data terminal D7-D0 by making S active "L"
Scan direction address counter 7 to write from
It controls the X and sub-scanning direction address counter 7Y.
In this way, in the 16-bit data line, the upper 8 bits are divided into an odd row and the lower 8 bits are divided into an even row and two rows, and one cell (address) is formed by one row.
If 6-bit data is allocated, 1024x in the scanning direction
This is because 16 bits (pixels) = 16 K bits, which greatly exceeds the number of pixels required in the scanning direction of the image input unit 1 of the OCR, and the memory utilization efficiency deteriorates.

For example, when the image data of the first row is written, the image data of 8 pixels from the line memory 4-1 is transferred to the data terminals D15 to D8 of the image memory 5 in accordance with the write timing of the odd lines in FIG. , And only the terminal UCAS is set to “L” to be valid, and the data of the first row is written to the end. Next, the image data of the second row from the line memory 4-2 is input to the data terminals D7 to D0 of the image memory 5 according to the write timing of the even lines in FIG. 5B, and only the terminal LCAS is set to "L". To enable it and write the data of the second line to the end. For reading, by validating the control signals of both the terminal UCAS and the terminal LCAS, data of 8 pixels for 2 lines is read in one read cycle. As a result of the above configuration, the image memory 5 configured by one 16 Mbit DRAM is, as shown in FIG. 4, scanning direction: 1024 × 8 pixels = 8096 pixels, sub-scanning direction: 1024 × 2 pixels (row) = 2048 pixels, which is horizontally long in the scanning direction.

[0007]

However, the conventional OCR has the following problems (a) and (b). (A) Problem relating to memory efficiency FIG. 6 is a diagram showing a conventional problem. Since the cell unit in which the same row address and column address of the conventional image memory 5 can be written has a structure of 8 pixels × 2 lines, this image memory 5 has a laterally long shape in the scanning direction, that is, a structure of 8K × 2K. turn into. For example, when the image memory 5 of 4K in the scanning direction and 8K in the sub-scanning direction is required, as shown in FIG. 6, the structure of 4 DRAMs (as a result, 8K × 8K) is required, so that the image memory 5 is 4K in the scanning direction.
The memory part of (8K-4K) is wasted, and 4K in total
There is a problem that the memory portion of × 8K is wasted and the use efficiency of the image memory 5 is deteriorated.

(B) Problem of reading speed In the conventional image memory 5, the scanning direction address counter 7X has a column address and a sub-scanning direction address counter 7.
Since the row address is assigned to Y, the row address is matched when reading in the scanning direction, and by using the high-speed page mode of the DRAM, the cycle period can be shortened and high-speed reading can be performed. But,
Since the row address changes in the sub-scanning direction, it is necessary to execute a normal DRAM read cycle for the terminals RAS, CAS, and OE.
For example, in the case of reading image data of a form rotated by 90 degrees, it is necessary to read continuously in the sub-scanning direction, so there is a problem that the reading speed becomes slow.

[0009]

In order to solve the above problems, the present invention optically reads characters or symbols written or printed on a form in an OCR and scans the image data of the form in the scanning direction. Image acquisition means for acquiring each row in the sub-scanning direction, first and second line memories storing the image data for each row, and writing the image data to the first and second line memories. Alternate for each row,
Each of the two rows of the image data is read from the first and second line memories by m (m ≧ 1 even number) bits .
A line memory control means for cormorants control, and a random access memory (Random Access Memory, hereinafter referred to as a RAM). The RAM 2 includes × and a data terminal of the m bits, a plurality of bits of address terminals for inputting a row address and a column address, and a control terminal heading write read inputs a control signal for writing and reading ing. Further, in the OCR of the present invention, the address in the scanning direction of the form is counted and the scanning direction address counter for outputting the column address to the address terminal, and the address in the sub-scanning direction of the form are counted,
A sub-scanning direction address counter that outputs the row address to the address terminal, and sets the write and read control signals to write and outputs to the write / read control terminal to control the count operation of the sub-scanning direction address counter. Image memory control means for setting an initial value of the scanning direction address counter, and (m / 2)
Bits of the image data of the first line memory and
The (m / 2) -bit image data of the second line memory is stored in a predetermined manner in the 2 × m-bit data terminal.
The data terminals of the m bits, reads a data conversion means for outputting simultaneously, the image data from the RAM,
A recognition control means for recognizing characters is provided. Since the OCR is configured as described above, the image data of the two rows read from the first and second line memories are simultaneously written in the RAM in the area where the row address and the column address are the same. As a result, in the direction of the RAM column, 2
One RAM that can store image data of rows
Can store twice as much image data in the row direction.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a block diagram of an OCR showing a first embodiment of the present invention. The OCR according to the first embodiment is composed of an image input unit 11 and an A / D conversion / level correction unit 1 having substantially the same configuration as the conventional one.
2, line memories 14-1 and 14-2, image memory 15, scanning direction address counter 17X, sub-scanning direction address counter 17Y, and recognition control unit 18, line memory control unit 13 having a configuration different from the conventional one, and image memory Control unit 16 and new data conversion unit 2 that has not existed in the past
It has 0 and. The output side of the image input unit 11 is an A / D
It is connected to the input side of the conversion / level correction unit 12. A
The output side of the / D conversion / level correction unit 12 is connected to the input sides of the line memories 14-1 and 14-2. The output side of the line memory control unit 13 has line memories 14-1,
14-2 is connected to the address terminal, the terminal WE, and the terminal OE. The output sides of the line memories 14-1 and 14-2 are connected to the input side of the data conversion unit 20. The output side of the data converter 20, the data terminal D15～D 8 image memory 15 is connected to D7 to D0.

[0011] Image output side of the memory control unit 16, a load terminal of the scanning direction address counter 17X, and the enable pin及 beauty load terminal in the sub-scanning direction address counter 17Y, the data converter 20 pin up and pin low
It is connected to the door. The output side of the image memory control unit 16 has terminals RAS and UCA of the image memory 15.
S, a terminal LCAS, a terminal WE, and a terminal OE, respectively. The output sides of the scanning direction address counter 17X and the sub scanning direction address counter 17Y are connected to the address terminal ADR of the image memory 15 via a selector (not shown). The output side of the recognition control unit 18 is connected to the input side of the image memory control unit 16. The data terminals D15 to D0 are connected to the input side of the recognition control unit 18. The image input unit 11 has a function of converting the characters that are handwritten printing or on form by optical or mechanical scanning into an electrical image signal. A / D
The conversion / level correction unit 12 has a function of A / D converting an electrical image signal and normalizing a white level / black level on a form. The image input unit 11 and the A / D conversion / level correction unit 12 configure an image acquisition unit that acquires image data of a form. Line memories 14-1, 14-2
Is prepared for the purpose of buffering one row of data before writing to the image memory 15 in order to absorb the speed difference of the image writing to the image memory 15.
This is a speed buffer memory of a book, for example, a 2-port static RAM (hereinafter SR
It is called AM). This SRAM is an 8-bit access memory in which writing / reading is controlled by terminals WE and OE, and the read cycle is shorter than the write cycle.

The line memory control unit 13 alternately writes the image data of the form into the line memories 14-1 and 14-2 row by row, and after writing the image data of two rows,
The line memory 14-1 has a function of simultaneously reading out row data.
An even numbered row is written in 4-2. The image memory 15 is composed of, for example, a DRAM, and has a 10-bit address terminal ADR and a 16-bit data terminal D.
15～D0, 1 to terminal RAS, terminal UCAS (column setting terminal), the terminal LCAS (mosquito ram setting terminal), the terminal WE, and write / read light through a terminal OE is controlled
It has a memory capacity of 6 bits × 2 ¹⁰ × 2 ¹⁰ bits = 16 Mbits. Writing is active when the terminal WE is "L", and reading is active when the terminal OE is "L". It becomes active when the terminal RAS is "L", and the terminals UCAS and LCAS are at high level (below.
Below, "H") , the row address becomes active and the row address becomes effective. When the terminal UCAS is "L", the data terminals D15 to D8 are used for writing / reading to the column area above the area specified by the row address and the column address.
Done by. When the terminal LCAS is "L", the data terminals D7 to D0 perform writing / reading to the lower column area of the lower column area specified by the row address and the column address.

The scanning direction address counter 17X is a 10-bit counter which is loaded with an initial value from a load terminal and performs a counting operation in synchronization with a clock to generate a column address of the image memory 15. The sub-scanning direction address counter 17Y performs the counting operation in synchronization with the clock when the initial value is loaded from the load terminal and the enable signal is active, and the image memory 15 is operated.
Is a 10-bit counter for generating the row address of.
The image memory control unit 16 loads the initial value 0 of the scanning direction address counter 17X, loads the initial value of the sub-scanning direction address counter 17Y, outputs the enable signal to the enable terminal, and the terminal up / up of the data conversion unit 20.
It has a function of generating a control signal for designating whether low is the upper 4 bits or the lower 4 bits. The data conversion unit 20 selects the upper 4 bits or the lower 4 bits of the 8 bits output from the line memories 14-1 and 14-2 based on the control signal input to the terminal up / low to output the data. It is a circuit that outputs to terminals D15 to D8 and D7 to D0 .

The recognition control unit 18 instructs the image memory control unit 16 about the address in the scanning direction, the address in the sub-scanning direction, the reading direction, the reading width, etc., and reads the image data from the image memory 15, It has the function of character recognition. FIG. 7 is a configuration diagram of the data conversion unit 20 in FIG. This data conversion unit 20
Bit registers 21 and 22 and selectors 23 and 24
have. The input side of the register 21 is connected to the 8-bit output terminal LM1 [7: 0] of the line memory 14-1. LM1 [7: of the output terminal of the register 21
4] and LM1 [3: 0] are connected to the input terminals of the selector 23. Selector 23 terminal up / low
Are connected to the output terminals of the image memory control unit 16. The output terminals D [3: 0] of the selector 23 are the data terminals D15 to D11 and D7 to D of the image memory 15.
4 is connected. The input side of the register 22 is an 8-bit output terminal LM2 [7: 0] of the line memory 14-2.
It is connected to the. Output terminal LM2 of register 22
[7: 4] and LM2 [3: 0] are connected to the input terminals of the selector 24. Terminal up / l of selector 24
ow is connected to the output terminal of the image memory control unit 16. The output terminals D [3: 0] of the selector 24 are the data terminals D11 to D8 and D3 to of the image memory 15.
It is connected to D0.

The registers 21 and 22 are used for the line memory 14
-1, 14-2 output terminals LM1 [7: 0], LM2
It is for storing the 8-bit image data output from [7: 0]. The selector 23, when the terminal up is active (for example, “L”), the line memory 14
-1 output terminal LM1 [7: 4] is selected, and when the terminal low is active (for example, "L"), the output terminal LM1 [3: 0] of the line memory 14-1 is selected.
Is a circuit for selecting an output signal from the data terminal and outputting it to the data terminals D15 to D12 and D7 to D4. The selector 24 is
When the terminal up is active (for example, "L"), the output signal from the output terminal LM2 [7: 4] of the line memory 14-2 is selected and output, and the terminal low is active (for example, "L"). ), It is a circuit that selects the output signal from the output terminal LM2 [3: 0] of the line memory 14-2 and outputs it to the data terminals D11 to D8 and D3 to D0.

FIG. 8 shows the line memory controller 13 in FIG.
It is a figure which shows the control flow of. FIG. 9 is a diagram showing writing to the image memory 15 in FIG. Further, FIG. 10 is an operation explanatory diagram of the data conversion unit 20 of FIG. 7.
The operation of the OCR of FIG. 1 will be described below with reference to FIGS. 7 to 10. The image input unit 11 in FIG. 1 converts the characters printed or handwritten on the form into an electric image signal and outputs the electric image signal to the A / D conversion / level correction unit 12. The A / D conversion / level correction unit 12 converts the electric image signal into a digital signal and normalizes it according to the white / black level on the form,
Output to the line memories 14-1 and 14-2. As shown in FIG. 8, the line memory control unit 13 outputs “L” to the terminal WE of the line memory 14-1 upon receiving a signal that a form is set from a transport control unit (not shown), and synchronizes with the clock. Then, the write address of the image data of the first line is generated and counted, and the line memory 14-
Output to 1 address terminal. Line memory 14-1
Writes the image data of the first line output from the A / D conversion / level correction unit 12 in the designated address area.

When the writing of the image data of the first row is completed, the line memory control section 13 finishes writing the line memory 14-2.
"L" is output to the terminal WE of the line memory, and the write address of the image data of the second row is generated by counting in synchronization with the clock and output to the address terminal of the line memory 14-2. The line memory 14-2 writes the image data of the second line output from the A / D conversion / level correction unit 12 in the designated address area. The line memory control unit 13
When the writing of the image data of the first and second rows is completed, the terminal OE of the line memories 14-1 and 14-2 is set to "L", the read address is output to the address terminal, and at the same time, to the image memory control unit 16. Output the transfer start signal. Then, the line memory control unit 13 reads the image data of the first and second lines and at the same time, sets the data of the third line to the same as the image data of the first line.
1 and the writing of the image data of the third row is completed, the image data of the fourth row is written to the line memory 14-
Write in 2.

8-bit image data from the line memories 14-1 and 14-2 are transferred to the data terminals LM1 [7: 0], LM.
2 [7: 0] and read from the line memory 14-1
, The image data of the third row is written at the same time, but since the read cycle is shorter than the write cycle, the read is normally performed. The line memory control unit 13 outputs a line data transfer end signal to the image memory control unit 16 when the reading of the image data of the first row and the second row is completed. Image memory control unit 1
6 receives a signal that a form has been set from a transport control unit (not shown), the scanning direction address counter 17
X and the sub-scanning direction address counter 17Y are cleared from the load terminal. Upon receiving the transfer start signal from the line memory control unit 13, the image memory control unit 16 outputs "L" to the terminal RAS only for the image data write cycle. The sub-scanning direction address counter 17Y is cleared by the image memory control unit 16, and the row address (0) h (h is the address of the address terminal ADR of the image memory 15 is passed through a selector (not shown) controlled by the image memory control unit 16. (Indicating hex) is output. The scanning direction address counter 17X is cleared by the image memory control unit 16, and the column address (0) h is supplied to the address terminal ADR of the image memory 15 through a selector (not shown) controlled by the image memory control unit 16.
Is output.

The image memory control unit 16 has a terminal UCA.
"L" is output to S (for example, the line memory control unit 13
1-bit counter for reading is incremented each time a transfer start signal is input from the terminal to output “L” to the terminal UCAS or the terminal LCAS according to the counter value), and outputs “L” to the terminal up of the data conversion unit 20. Output (eg,
Incremented by 1 bit counter for writes each write, and outputs "L" to the terminal Stay up-/ low the counter value). In the data conversion unit 20, the image data LM output from the line memories 14-1 and 14-2.
1 [7: 0] and LM2 [7: 0] are set to registers 21 and 22.
Latched by and output to the selectors 23 and 24. Since the terminal up is "L", the selector 23 selects the upper 4 bits LM1 [7: 4] of the image data from the line memory 14-1 to select the image memory 15 as shown in FIG.
Data terminals D15 to D12 and D7 to D4. Since the terminal up of the selector 24 is "L",
As shown in, the upper 4 bits LM2 [7: 4] of the image data from the line memory 14-2 are selected and output to the data terminals D11 to D8 and D3 to D0 of the image memory 15.

Since the terminal UCAS is "L", the image memory 15 has a row address (0) h and a column address (0) h.
1 input to the data terminals D15 to D8 in the area above
The upper 4 bits of the first 8 bits of the row and the upper 4 bits of the first 8 bits of the second row are written. The image memory control unit 16 outputs “L” to the terminal RAS when the writing of the upper 4 bits is completed.
The row address (0) h is output from the sub-scanning direction address counter 17Y to an address terminal through a selector (not shown). The image memory control unit 16 has a terminal UCA.
“L” is output to S and “L” is output to the terminal low of the data conversion unit 20. Scanning direction address counter 17X
Performs a counting operation in synchronization with the clock and outputs the column address (1) h to the address terminal. Since the terminal low of the selector 23 is "L", as shown in FIG. 10, the lower 4 bits LM1 of the image data from the line memory 14-1 are input.
Select [3: 0] and output to the data terminals D15 to D12 and D7 to D4 of the image memory 15. Since the terminal low is "L", the selector 24 selects the lower 4 bits LM2 [3: 0] of the image data from the line memory 14-2, as shown in FIG.
Data terminals D11 to D8 and D3 to D0.

Since the terminal UCAS is "L", the image memory 15 has a row address (0) h and a column address.
(1) In the area of the column above h, the lower 4 bits of the first 8 bits of the first row and the lower 4 bits of the first 8 bits of the second row that are input to the data terminals D15 to D8 Write the image data of. The above processing is performed on the image data of the first and second rows, and the data of 4K (4 × 1024) pixels in each row is written in the image memory 15. 1st line and 2
When the line data transfer end signal is input from the line memory control unit 13 after the reading (writing to the image memory 15) of the image data of the row from the line memories 14-1 and 14-2 is completed, the scanning direction address counter 17X
To clear. Upon receiving the transfer start signal from the line memory control unit 13, the image memory control unit 16 outputs the image data of the third and fourth lines to the terminal RA of the image memory 15.
"L" is output to S, "L" is output to the terminal LCAS, and "L" is alternately output to the terminal up / low. The sub-scanning direction address counter 17Y outputs the row address (0) h to the address terminal ADR. Scanning direction address counter 17X
Performs a counting operation in synchronization with the clock and outputs the column address to the address terminal ADR.

The data conversion section 20 operates in the same manner as the image data of the first and second lines, and depending on the value of the terminal up / low, of the 8 bits from the line memories 14-1 and 14-2. The upper 4 bits or the lower 4 bits are output to the data terminals D15 to D0. Since the terminal LCAS is "L", the image memory 15 writes the image data of the third row and the fourth row in the row address (0) h and the column area below the column address (0) h. After the writing of the image data on the third and fourth lines is completed, the line memory control unit 13
When a line data transfer end signal is input from, the sub-scanning direction address counter 17Y is enabled and incremented by 1 (for example, one sub-scanning direction address counter 17Y is written every four rows by the value of the 1-bit counter for reading. Is incremented). Then, as shown in FIG. 9, 4 bits of the 1st and 2nd rows are written in the upper column area, and 4 bits of the 3rd and 4th rows are written in the lower column area. 4 pixels × 4 lines can be accessed with the same row address and column address. When writing the image data of the fifth and sixth lines to the image memory 15, the image memory control unit 16
Output "L" to terminal RAS and "L" to terminal UCAS,
"L" is alternately output to the terminal up / low. The sub-scanning direction address counter 17Y is incremented after the writing of the image data of the third and fourth rows and the counter value is (1) h. Therefore, the row address (1) h is set to the address terminal A.
Output to DR. The scanning direction address counter 17X is
The counting operation is performed in synchronization with the clock, and the column address is output to the address terminal ADR.

The data converter 20 selects the upper 4 bits or the lower 4 bits from the line memories 14-1 and 14-2 according to the value of the terminal up / low and outputs them to the data terminals D15 to D0. The image data of the fifth and sixth lines is written in the area of the column above the row address (0) h and the column address (0) h of the image memory 15.
Image data of the seventh row and the eighth line, the row address (0) h, and the column address (0) <br/> are written in the area of the column bottom h. The above is repeated every four lines, and all the pixels of one sheet are written in the image memory 15. As a result, 4K pixels in the scanning direction and 4K pixels in the sub-scanning direction.
The image data of the line will be written in one image memory 15 of 16 Mbits. Recognition control unit 18
Instructs the image memory control unit 16 about the address in the scanning direction, the sub-scanning direction, the reading direction, the reading width, and the like. According to the instruction from the recognition control unit 18, the image memory control unit 16 simultaneously sets the terminals UCAS and LCAS to "L" and reads out the image data of one cell of 4 pixels × 4 lines. The recognition control unit 18 inputs the image data read from the image memory 15 and cuts out and recognizes characters.

As described above, the first embodiment has the following advantages (a) and (b). (A) By writing image data to the image memory 15 in units of two rows, one cell (address) can be made into a unit of 4 pixels × 4 lines. For the address, the scanning direction address counter 17X is assigned to the column address, and the sub-scanning direction address counter 17Y is assigned to the row address. As a result, the image memory 15 composed of one DRAM has the following: scanning direction: 1024 × 4 pixels and sub-scanning direction: 1024 × 4 pixels. (B) FIG. 11 is a configuration diagram showing an example of the image memory 15 in FIG. The image memory 15 is configured by vertically arranging two DRAMs 15-1 and 15-2. With this configuration, for example,
Image memory 1 with 4K scanning direction and 8K sub-scanning direction
Even if 5 is required, it can be efficiently constructed.

Second Embodiment FIG. 12 is a block diagram of an OCR showing a second embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are designated by common reference numerals. Is attached. In the OCR of the second embodiment, the data conversion unit 20 of FIG. 1 is deleted, and the output sides of the line memories 14-1 and 14-2 are connected to the data terminals D15 to D8 and D7 to D0 of the image memory 15. There is. Further, in place of the image memory control unit 16 of FIG. 1, an image memory control unit 16A having a different configuration is provided and an address conversion unit 30 is newly added. The output side of the image memory control unit 16A has terminals WE, OE, RAS,
It is connected to the terminal UCAS and the terminal LCAS. Further, the output side of the image memory control unit 16A is connected to the load terminal of the scanning direction address counter 17X, the load terminal of the sub-scanning direction address counter 17Y, and the enable terminal. Scanning direction address counter 1
The output side of the 7X and the sub-scanning direction address counter 17Y is connected to the input side of the address conversion unit 30. The output side of the address conversion unit 30 is connected to the address terminal ADR of the image memory 15 through a selector (not shown).

In the second embodiment, for example, it is assumed that the image data of the form requires 8 bits × 512 × 8 bits = 4K bits in the scanning direction and 512 × 2 pixels = 1K bits in the sub-scanning direction. Scanning direction address counter 17
X is a 10-bit counter, and sub-scanning direction address counter 17Y is a 10-bit counter. The image memory 15 is a DRAM having a structure of 16 bits × 1024 × 1024 = 16 Mbits. Image memory control unit 16
A controls the terminal RAS, the terminal UCAS, the terminal LCAS, the terminal WE, and the terminal OE to clear the sub-scanning direction address counter 17Y and write the image data of two rows, the sub-scanning direction address counter 17Y. Is incremented to clear the scanning direction address counter 17X. The address translation unit 30
10-bit row address of image memory 15 [9:
[8: 0] of 0] = sub-scanning direction address counter 17
[9: 1] and [9: 9] of Y = address conversion to [9: 9] of the scanning direction address counter 17X to generate a row address, and a 10-bit column address [9: 0] of the image memory 15 is generated. ] [8: 0] = scan direction address counter 17X [8: 0], column address [9: 9]
= A circuit for converting the address into [0: 0] of the sub-scanning direction address counter 17Y to generate a column address.
Other configurations are the same as those in the first embodiment.

FIG. 13 shows the address conversion unit 30 shown in FIG.
It is a figure which shows the address conversion of. FIG. 14 is a diagram showing the relationship between the image memory 15 and addresses in FIG. FIG. 15 is a diagram showing writing to the image memory 15 in FIG. The operation of the OCR of FIG. 12 will be described below with reference to FIGS. Image input section 1
Reference numeral 1 converts a character printed or handwritten on a form into an electric image signal, and the A / D conversion / level correction unit 12 converts the electric image signal into a digital signal, and a white / white image on the form.
Normalize according to the black level. Line memory control unit 13
Reads the image data from the other line memory 14-2 (or 14-1) while writing the image data for one main scanning line into the one line memory 14-1 (or 14-2), The image data is sent to the image memory 15, and a read start signal is output to the image memory control unit 16A. When writing and reading for one line are completed, a line data transfer end signal is output to the image memory control unit 16A, the writing side is switched to the reading side and the reading side is switched to the writing side, and the same operation is performed.
The image data for the screen is sent to the image memory 15.
The image memory control unit 16A clears the scanning direction address counter 17X and the sub-scanning direction address counter 17Y when a signal that a form is set is input from a conveyance control unit (not shown).

The image memory control unit 16A outputs "L" to the terminal RAS for the write cycle when the line memory control unit 13 inputs the read start signal of the image data of the first row from the line memory 14-1. The sub-scanning direction address counter 17Y is cleared by the image memory control unit 16A, and (0) h is transferred to the address conversion unit 30.
Output to. The scanning direction address counter 17X is cleared and outputs (0) h to the address conversion unit 30. The address conversion unit 30, as shown in FIG. 13, has a row address [8: 0] = [9: of the sub-scanning address counter 17Y.
1], row address [9: 9] = address in the scanning direction address counter 17X is converted to [9: 9] to generate a row address, and the image memory 15 is passed through a selector (not shown) controlled by the image memory control unit 16A.
The row address (0) h is output to the address terminal ADR.
As shown in FIG. 13, the address conversion unit 30 includes a column address [8: 0] = [8: 0] of the scanning direction address counter 17X, a column address [9: 9] = [0 of the sub-scanning direction address counter 17Y. : 0] to generate a column address, and the image memory control unit 16A
A column address is supplied to the address terminal ADR of the image memory 15 through a selector (not shown) controlled by
Outputs (0) h.

The image memory control unit 16A has a terminal UC.
Output "L" to AS. The image memory 15 is provided with a row address (0) h and a column area above the column address (0) h from the line memory 14-1 to the data terminal D15-.
The 8-bit image data of the first row input to D8 is written. Each time the 8-bit image data of the first line is written,
The image memory control unit 16A outputs "L" to the terminal RAS for a write cycle and "L" to the terminal UCAS, and the scanning direction address counter 17X performs counting operation in synchronization with the clock. The address conversion unit 30 generates a row address and a column address in the same manner as described above, and outputs the row address and the column address to the address terminal ADR through a selector (not shown). As a result, the image data of the first row is stored in the image memory 15 at the row address (0) h and the column address (0) h.
~ (1FF) h (the number of pixels in one row is 8 bits x 512 bits)
Written in the area of the column above. Line memory 14
When the reading of the image data from the first row to the first row is completed, the line memory control unit 13 to the image memory control unit 16A
A transfer end signal is output to. Image memory control unit 1
When 6A receives the transfer end signal, 6A clears the scanning direction address counter 17X. Image memory control unit 1
6A receives the read start signal of the line memory 14-2 for the image data of the second row from the line memory control unit 13, sets the terminal LCAS to "L" and sets the row address (0).
Writing is performed in the area under h and the column addresses (0) h to (1FF) h.

When the reading of the image data of the second line from the line memory 14-2 is completed, a transfer end signal is output from the line memory control unit 13 to the image memory control unit 16A. Upon receiving the transfer end signal, the image memory control unit 16A clears the scanning direction address counter 17X, enables the sub-scanning direction address counter 17Y, and increments it. At the time of writing to the third line image data, the image memory control unit 16A
It operates in the same way as the first line. Scanning direction address counter 1
7X is the same operation as the first line in synchronization with the clock, is incremented, and outputs to the address converter 30. Since the sub-scanning direction address counter 17Y has been incremented when the writing of the image data of the second row is completed, it outputs (1) h. Since the sub-scanning direction address counter 17Y is (1) h, the address converting unit 30 generates the row address (0) h, and the column address according to the counter values (0) h to (1FF) h of the scanning direction address counter 17X. (200) h ~ (3
FF) h is sequentially generated, and the column address is output to the address terminal ADR through a selector (not shown).

In the image memory 15, as shown in FIG. 14, the image data of the third row is stored in the area above the row address (0) h and the column addresses (200) h to (3FF) h every 8 bits. Written in. For the image data on the fourth line, see FIG.
As shown in, row address (0) h and column address
It is written in the area under (200) h to (3FF) h every 8 bits. As a result, in the image memory 15, as shown in FIG. 15, the image data of the first row is stored at the row address (0) h,
The area above the column addresses (0) h to (1FF) h and the image data in the second row are the row address (0) h and the column address.
The area under (0) h to (1FF) h, the image data in the third row is the area above row address (0) h and column address (200) h to (3FF) h, and the image in the fourth row. The image data is written in the area under the row address (0) h and the column addresses (200) h to (3FF) h and four rows in the area of the row address (0) h. Similar to the above operation for the first to fourth lines, the fifth to eighth lines,
The row address is incremented by one every four rows by repeating the same process for the image data of the ninth row to the twelfth row, and the column addresses of the first two rows are (0) h.
Areas of columns above and below (1FF) h and the next two lines are written in areas having column addresses (200) h to (3FF) h.

The recognition control unit 18 instructs the image memory control unit 16A on the scanning direction and sub-scanning direction position, the reading direction, the reading width, and the like. The image memory control unit 16A sets the terminal OE and the terminal RAS to "L" and makes them valid according to the reading instruction from the recognition control unit 18, and simultaneously sets the terminals UCAS and LCAS to "L".
Then, the scanning direction address counter 17X and the sub-scanning direction address counter 17Y are controlled in the same manner as the writing of the image data, and the image memories 15 to 16 are controlled.
Image data is read bit by bit. The address conversion unit 30 performs address conversion from the count values of the scanning direction address counter 17X and the sub scanning direction address counter 17Y in the same manner as writing to generate a row address and a column address. For example, when the form is rotated by 90 degrees and only the value designated by the read width in the sub-scanning direction is read by the counter value (0) h of the scanning direction address counter 17X, the first to fourth lines are read. Since the row address is stored in the area of (0) h, reading can be performed in the high speed page mode during that time. The image data read from the image memory 15 is recognized by the recognition control unit 18. As described above, according to the second embodiment, it is possible to read in the high speed page mode in the sub-scanning direction of the image memory 15, the read cycle period can be shortened, and high speed operation can be realized. Also,
Since four rows of image data are written in the image memory 15 at the same row address, the column direction area can be used effectively.

Third Embodiment FIG. 16 is a block diagram of an OCR showing a third embodiment of the present invention, in which elements common to those in FIG. 12 showing the second embodiment are designated by common reference numerals. Is attached. In the OCR of the third embodiment, an address conversion unit 30A having a different configuration is provided instead of the address conversion unit 30 of FIG. In the third embodiment, for example, it is assumed that the image data of the form needs 2K (256 × 8) pixels in the scanning direction and 1K (256 × 8) lines in the sub-scanning direction. The scanning direction address counter 17X is an 8-bit counter, and the sub-scanning direction address counter 17Y is a 12-bit counter. The image memory 15 is a 16M-bit D
RAM. The address conversion unit 30A sets the 10-bit row address [9: 0] of the image memory 15 to
[7: 0] = [9: 2] of sub-scanning direction address counter 17Y, [9: 8] = scanning direction address counter 1
A row address is generated by converting to 7X [9: 8], and a 10-bit column address [9: 0] of the image memory 15 [7: 0] = scanning direction address counter 1
This is a circuit for converting a 7-bit 10-bit value [7: 0], [9: 8] = [1: 0] of the sub-scanning direction address counter 17Y to generate a column address.

FIG. 17 shows the address conversion unit 30 in FIG.
It is a figure which shows the address conversion of A. Furthermore, FIG.
FIG. 17 is a diagram showing a relationship between the image memory 15 and addresses in FIG. 16. The operation of FIG. 16 will be described below with reference to FIGS. 17 and 18. The image input unit 11 converts the characters printed or handwritten on the form into an electric image signal, and the A / D conversion / level correction unit 12 converts the electric image signal into a digital signal, and the white on the form. -Normalize according to the black level. The line memory control unit 13 writes the image data for one line of the main scanning to the one line memory 14-1 (or 14-2) while the other line memory 14-2 (or 14-1) Read the image data,
The image data is sent to the image memory 15. When the writing and reading for one line are completed, the writing side is switched to the reading side and the reading side is switched to the writing side, and the same operation is performed, and the image data for one screen of the form is sent to the image memory 15. The image memory control unit 16A has a second
In the same manner as in the first embodiment, the scanning direction address counter 17X is cleared every time a transfer start signal is input from the line memory control unit 13, and odd-numbered rows 1, 3, ...
Set CAS to "L", and even-numbered rows 2, 4, ...
The CAS is set to "L", and the sub-scanning direction address counter 17
Y is incremented every two rows, and while the scanning direction address counter 17X is incremented, writing of image data to the upper and lower regions of the column is controlled.

As shown in FIG. 17, the address conversion unit 30A generates an address for the row address [9: 0] by using the upper bits except the lower 2 bits of the sub-scanning direction address counter 17Y. The row address is incremented each time. Address conversion unit 30
As shown in FIG. 17, A is a column address [9: 0].
2), the upper 2 bits are set as the lower 2 bits of the sub-scanning direction address counter 17Y.
When writing the image data of the row, since the sub-scanning direction address counter 17Y is (1) h, the column address is (1
FF) h. When writing the image data of the fifth and sixth lines, the sub-scanning direction address counter 17Y is (2) h,
The column address is (200) h to (2FF) h. Line 7 and 8
When writing the image data of the row, the sub-scanning direction address counter 17Y is (3) h, so the column address is (30
It will be 0) h to (3FF) h. As a result, as shown in FIG. 18, the image data in the first row is the area above the row address (0) h and the column addresses (0) h to (FF) h, and the image data in the second row is Row address (0) h and column address (0) h ~
Written in the area below (FF) h.

The image data in the third line is row address (0).
Area above h and column address (100) h to (1FF) h, 4
The image data of the row is written in the area below the row address (0) h and the column addresses (100) h to (1FF) h. The image data on the fifth row is the area above the row address (0) h and the column addresses (200) h to (2FF) h, and the image data on the sixth row is the row address (0) h and the column address. (200) h ~ (2
It is written in the area below FF) h. The image data of the 7th row includes row address (0) h and column addresses (300) h to (3
The area above FF) h, the image data on the 8th row is the row address.
It is written in the area below (0) h and column addresses (300) h to (3FF) h. By performing the above processing on the image data for every 8th row from the 9th row to the 16th row, the 17th row to the 24th row and thereafter, the image data of the 8th row has the same row address and the column address (0 ) h ~ (FF) h column area above and below, (1
It is written in the upper and lower column areas of 00) h to (1FF) h, the upper and lower column areas of (200) h to (2FF) h, and the upper and lower column areas of (300) h to (3FF) h. .

The recognition control unit 18 instructs the image memory control unit 16A about the position in the scanning direction and the sub-scanning direction, the reading direction, the reading width, and the like. According to the instruction, the image memory control unit 16A controls the scanning direction address counter 17X and the sub-scanning direction address counter 17Y similarly to the writing, and the address conversion unit 30A
A row address and a column address are generated from the count values of the scanning direction address counter 17X and the sub-scanning direction address counter 17Y and are read from the image memory 15. For example, when the form is rotated by 90 degrees and when reading only the value specified by the read width in the sub-scanning direction from the counter value (0) h of the scanning direction address counter 17X, 8 lines of image data are read in the high-speed page mode. Can be read with. The recognition control unit 18 cuts out characters from the image data read from the image memory 15 and performs character recognition. As described above, according to the third embodiment, it is possible to read in the high-speed page mode for a longer period than in the first embodiment, the read cycle period can be shortened, and high speed can be realized. The present invention is
The present invention is not limited to the above embodiment, and various modifications are possible. The following are examples of such modifications.

(1) Image memory 1 of the above embodiment
Although the case of the configuration of the DRAM of 16 Mbits is described in Section 5, it may be 1 Mbits, 4 Mbits, or the like. (2) In the second embodiment, the case where the scanning direction is 4K pixels has been described. However, in the case where the scanning direction is 8K pixels, for pixels whose scanning direction exceeds 4K, [9: 9] of the scanning direction address counter 17X. ] Becomes “1” and the row address
Image data is written in the area of (300) h to (3FF) h. (3) The image of the form is 4 bits × in the scanning direction
When 152 = 2K and 1024 × 8 = 8K bits in the sub scanning direction, the first embodiment and the second embodiment can be combined. In this case, the first and second lines are
The row area (0) h, the column area above the column addresses (0) h to (1FF) h, the third row and the fourth row are row address (0) h,
The area of the column below the column address (0) h to (1FF) h, the fifth line and the sixth line are the row address (0) h and the column address (20
The area of the column above 0) h to (3FF) h, the 7th and 8th lines,
The data is written in the column area below the row address (0) h and the column addresses (200) h to (3FF) h.

(4) In the second and third embodiments, the sub-scanning direction address counter 17Y has 11 bits,
The row address may be configured by 12 bits and the row address may be configured by [10: 1] and [11: 2] of the sub-scanning direction address counter 17Y. (5) 16 × in the column direction of the image memory 15
Assuming that 2 ^n- bit image data and one row of the form are composed of 16 × 2 ^k- bit pixels, the s-bits (1 ≦ s ≦ nk) of the scanning direction address counter 17X to the upper bits and the sub-scanning direction. The column address may be generated from 0 bit to (s-1) bit of the address counter 17Y and the upper bits thereof.

[0040]

As described in detail above, the first and second
According to the fourth invention, since the RAM stores the image data of two different rows in the area of the same column address, the utilization efficiency of the memory in the column direction is improved. According to the third and fourth inventions, the image data of a plurality of different rows is stored in the area of the same row address and the same column address. Therefore, when the image data of a plurality of rows is read,
The row address does not change and the image data can be read in the high speed page mode, and the processing speed becomes high.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an OCR according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional OCR.

FIG. 3 is a diagram showing a conventional line memory control flow.

FIG. 4 is a diagram showing writing to a conventional image memory.

FIG. 5 is a diagram showing a flow of writing into a conventional image memory.

FIG. 6 is a diagram showing a conventional problem.

FIG. 7 is a configuration diagram of a data conversion unit 20 in FIG.

8 is a diagram showing a control flow of a line memory controller 13 in FIG.

9 is a diagram showing writing to the image memory 15 in FIG. 1. FIG.

10 is an operation explanatory diagram of the data conversion unit 20 of FIG.

11 is a configuration diagram of an image memory 15 in FIG.

FIG. 12 is a configuration diagram of an OCR according to a second embodiment of the present invention.

13 is a diagram showing address conversion by an address conversion unit 30 in FIG.

14 is a diagram showing the relationship between the image memory 15 and addresses in FIG.

15 is a diagram showing writing to the image memory 15 in FIG.

FIG. 16 is a configuration diagram of an OCR according to a third embodiment of the present invention.

17 is a diagram showing address conversion by the address conversion unit 30A in FIG.

18 is a diagram showing the relationship between the image memory 15 and addresses in FIG.

[Explanation of symbols]

11 Image Input Unit 12 A / D Conversion / Level Correction Unit 13 Line Memory Control Units 14-1, 14-2 Line Memory 15 Image Memory 16, 16A Image Memory Control Unit 17X Scanning Direction Address Counter 17Y Sub-scanning Direction Address Counter 18 Recognition Control unit 20 Data conversion unit 30, 30A Address conversion unit

Claims (4)

(57) [Claims] 1. An image acquisition unit that optically reads characters or symbols written or printed on a form and acquires image data of the form in the sub-scanning direction for each line in the scanning direction. The first and second line memories that store the data for each row, and the image data writing to the first and second line memories that are alternately performed for each row, Each of the image data of the row is m (even if m ≧ 1
Number) bit line memory control means for controlling to read bit by bit, data terminal of 2 × m bits, address terminal of a plurality of bits for inputting row address and column address, write for inputting write and read control signals. only write
A random access memory having a control terminal out read counts the address of the scanning direction of the document, a scanning direction address counter for outputting the column address to the address terminals, the sub-scanning direction addresses of the form A sub-scanning direction address counter that counts and outputs the row address to the address terminal, and sets the write and read control signals to write and outputs the write and read control signals to the write and read control terminal, Image memory control means for controlling a count operation and setting an initial value of the scanning direction address counter; and (m / 2) bits of the image data of the first line memory and (m / 2) bits of the first image data. 2 of the image data of the line memory and the 2 × m-bit data terminal
A data terminal for a predetermined m-bit in, reads a data conversion means for outputting simultaneously, the image data from said random access memory, and a recognition control unit that performs recognition of the character, characterized by comprising Optical character reader. 2. An image acquisition unit for optically reading characters or symbols written or printed on a form to acquire image data of the form in the sub-scanning direction for each line in the scanning direction, and the image data. The first and second line memories that store the data for each row, and the image data writing to the first and second line memories that are alternately performed for each row, Line memory control means for controlling to read out the image data of each row by m (even number of m ≧ 1) bits, a 2 × m-bit data terminal, and n (n ≧ n) for inputting a row address and a column address. 1 integer) and address terminals of bits, writing and a control terminal heading write read inputs a control signal for reading, the column of or below the column address that areas of m bits of the column above m A random access memory having a column setting terminal for inputting a column setting signal indicating whether it is a bit area, and a random access memory having a memory capacity of 2 × m × 2 ⁿ × 2 ⁿ bits, and counting addresses in the scanning direction of the form A scanning direction address counter that outputs the column address to the address terminal; a sub-scanning direction address counter that counts the address of the form in the sub-scanning direction and outputs the row address to the address terminal; A write / read control signal is set to write and output to the write / read control terminal, and the row address is incremented by one each time four lines of the image data are written to the random access memory.
Controlling the counting operation of the sub-scanning direction address counter, setting an initial value in the scanning direction address counter,
Above / below the column area or below / below the column setting terminal
Image memory control means for outputting the column setting signal in the above order, the image data of the first line memory of (m / 2) bits and the image of the second line memory of (m / 2) bits. and data, prior to correspond to the column setting signal
Serial to data terminals of the m bits in the data terminals of the 2 × m bits, reads a data conversion means for outputting simultaneously said image data from said random access memory, recognition control means for recognizing a character An optical character reader comprising: 3. Characters or symbols written or printed on a form are optically read, and m × 2 ^k (m ≧ 1 integer, k ≧ 1 integer) pixels for each line in the scanning direction of the form. Image acquisition means for acquiring the image data in the sub-scanning direction, a 2 × m-bit data terminal, an n (n ≧ 1 integer) -bit address terminal for setting a row address and a column address, and writing. a control terminal heading write read inputs a control signal for reading, the column set terminal to which the column address is input column setting signal indicating whether the column of the m bit below what columns of m bits of the upper A random access memory having a memory capacity of 2 × m × 2 ⁿ × 2 ⁿ bits, and storing the image data for each row, and the 2 × m number of the image data for each m-bit image data. Corresponding to the data terminal First and second line memories for outputting to each of the data terminals, and writing of the image data to the first and second line memories is alternately performed for each row, and one of the first or second line memories is provided. While writing the image data in the line memory of
Line memory control means for reading the image data from the other second or first line memory, a scanning direction address counter for counting addresses in the scanning direction of the form, and an address in the sub-scanning direction for the form. a sub-scanning direction address counter, is set to write the write and read control signal to output to the set terminal heading the write write read, the sub-scanning direction address counter in the random access memory 2
Each time the image data of ^j (j = 0 or 1) rows is written, it is controlled to be incremented by one, an initial value is set in the scanning direction address counter, and the column setting terminal is set to the upper or lower part of the column. Alternatively, an image memory control means for outputting a column setting signal in the order of lower and upper, and lower 1-j + s (1) of the sub-scanning direction address counter.
≦ s ≦ n−k−1) A predetermined upper bit from the 0th bit is converted to the row address as a higher bit from the 0th bit of the row address, and a predetermined upper bit from the 0th bit of the scanning direction address counter is converted. The high-order bits are converted into the high-order bits from the 0th bit of the column address, and the 0th to (s-1) th bits of the sub-scanning direction address counter are converted into the high-order bits of the column address to the column address. An optical character reading apparatus comprising: an address conversion unit; and a recognition control unit that reads the image data from the random access memory and recognizes a character. 4. A character or symbol written or printed on a form is optically read and m × 2 ^k (an even number of m ≧ 2, an integer of k ≧ 1) pixels for each line in the scanning direction of the form. Image acquisition means for acquiring the image data in the sub-scanning direction, first and second line memories that store the image data for each row, and write the image data to the first and second line memories. Alternately for each row, the line memory control means for reading out the image data of two rows from the first and second line memories by m (even number of m ≧ 1) bits, and a 2 × m-bit data terminal. When the address terminal of the n (n ≧ 1 integer) bits for a row address and a column address, a write control terminal heading write read inputting a control signal of the read, the column address above M of the column And a column set terminal for receiving a column setting signal indicating Tsu or bets space of what areas of the m bits of the column bottom, a random access memory having a memory capacity of ^{2 × m × 2 n × 2} n bits A scanning direction address counter that counts addresses in the scanning direction of the form; a sub-scanning direction address counter that counts addresses in the sub-scanning direction of the form; It is output to the write / read control terminal and the image data is output to the random access memory by 2 ^j (j = 0,
1 or 2) The sub-scanning direction address counter is incremented by 1 each time a row is written, an initial value is set in the scanning direction address counter, and the column setting terminal is set to the upper / lower or lower / upper of the column area. And (m / 2) -bit image data of the first line memory and (m / 2) -bit second image data of the second line memory. the prior corresponding to the column setting signal
Serial 2 × m in the data terminals of the m bits in the data terminals of the bit, the data converting means and the low-order 2-j + s of the sub-scanning direction address counter (1 simultaneously output
≦ s ≦ n−k−1) A predetermined upper bit from the 0th bit is converted into the row address as a higher bit from the 0th bit of the row address, and a predetermined upper bit from the 0th bit of the scanning direction address counter is converted. The high-order bits are converted into the high-order bits from the 0th bit of the column address, and the 0th to (s-1) th bits of the sub-scanning direction address counter are converted into the high-order bits of the column address as the high-order bits. An optical character reading apparatus comprising: an address conversion unit; and a recognition control unit that reads the image data from the random access memory and recognizes a character.