JP3413940B2 - Arithmetic circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a DSP (Digital Signa).
MA, which is used for a processor
The present invention relates to an arithmetic circuit having a C structure (Multiply-Accumulate architecture).

[0002]

2. Description of the Related Art An arithmetic circuit having a MAC structure used in a DSP is usually used to find a solution of the following equation. A = M ₁ · N ₁ + M ₂ · M ₂ + ... + M _n · N _n (1) Then, this equation can be divided into so-called MAC operations, which are basic steps shown in the following equation. A _i = A _i-1 + M _i · N _i (2) In recent DSPs, this MAC operation is executed in one instruction cycle.

FIG. 4 is a block diagram showing a configuration example of an arithmetic circuit having a general MAC structure, and FIG. 5 is a flow chart showing a MAC operation by the circuit of FIG. In FIG. 4, 1 is a multiplier storage register, 2 is a multiplicand storage register, 3 is a multiplier, 4 is a product register, 5 is an arithmetic logic unit (ALU / adder), and 6 is an accumulator.

In such a configuration, the initialization
The value P of the product register 4 and the accumulation
The value A of the data 6 is “0”. MAC operation
Once started, the multiplier M_iIs stored in the multiplier storage register 1
Multiplicand N_iIs stored in the multiplicand storage register 2.
However, the parameter i satisfies the relationship of 1 ≦ i ≦ n.
It is a natural number. Then, in the multiplier 3, the multiplier storage register
Multiplier M stored in star 1_iAnd the multiplicand storage register 2
Stored multiplicand N_iAnd are multiplied, and the multiplication result (M_i・
N_i) Is stored in the product register 4. As a result, the product cash register
Value P of star 4_iIs (M_i・ N_i), And this product Regis
Value P_iIs input to the arithmetic and logic unit 5. Arithmetic logic
In the arithmetic unit 5, the value P of the input product register 4 is input._i
(= M_i・ N _i) And MAC operation one cycle before
Accumulated by arithmetic logic unit 5
Value A held in data 6_i-1(= A_i-2+ P_i-1)When
Arithmetic logic operation based on the above equation (2) is performed using
Be done. Then, the calculation result [A_i-1+ P_i(= M_i・
N_i)] Is stored in the accumulator 6. as a result,
Accumulator 6 value A_iIs (A_i-1+ P_i),
Value A of this accumulator 6_iEnters the arithmetic logic unit 5
And the arithmetic logic of the next cycle MAC operation
Used for calculation. The above process is usually performed in one clock
It will be done sequentially for each cycle.

FIG. 6 is a block diagram showing a concrete configuration example of the multiplier 3 in the circuit of FIG. As shown in FIG. 6, the multiplier 3 is generally composed of a partial product generator 31, a partial product converter 32, and a carry-propagate adder 33 having two inputs and one output. In the multiplier 3, the partial product generator 31 first obtains the partial product of the multiplier M and the multiplicand N based on, for example, the Booth algorithm (for example, “Joseph JFCavanagh.
Digital Computer Arithmetic.McGraw-Hill, New York,
1985). The plurality of partial products obtained by the partial product generator 31 are input to the partial product converter 32, where they are subtracted or added to be combined into two partial products and output to the carry propagate type adder 33. . In carry propagate adder 33, addition processing is performed on the input partial product, and the result is stored in product register 4.

FIG. 7 is a diagram showing a configuration example of this carry propagate type adder. The carry propagate adder includes a plurality of full adders 33-1 to 33-3 as shown in FIG.
33-n (FA1 to FAn) and full adder 33-i
The carry obtained in step S1 is sequentially propagated to the full adder 33-i + 1 in the next stage, and the sum sn from the full adder 33-n in the final stage.
And carry out carry out is obtained.

[0007]

However, in the above-described conventional arithmetic circuit, since the carry propagator type adder 33 for propagating the carry output to the next higher order full adder is used in the multiplier 3, There is a problem that the operation speed is slow.

In order to solve this problem, it is conceivable to apply a carry look-ahead type adder or a carry select type adder, which operates faster than the carry propagate type adder 33, but these adders are used. ,
The circuit scale is large and it is not possible to obtain a sufficiently satisfactory operating speed.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an arithmetic circuit capable of improving the operating speed and preventing an increase in circuit scale.

[0010]

In order to achieve the above object, the arithmetic circuit of the present invention obtains a partial product of an accumulator and a given multiplier and multiplicand, and obtains a sum of the partial products to obtain a first and a second product. A partial product generator that generates a second partial product; a first product register that holds the first partial product;
The second product register that holds the second partial product and the data held in the first product register, the second product register, and the accumulator are added to obtain the first and second partial sums. It has a carry-save adder to be obtained and an arithmetic-logical operation unit for performing an arithmetic-logical operation based on the first and second partial sums by the carry-save adder and holding the arithmetic operation result in the accumulator.

Further, the arithmetic circuit of the present invention has a function selection for selecting whether to perform the product-sum operation processing or the arithmetic logic operation processing according to the input of the selection signal in the input stage of the carry save type operation unit. It has a circuit.

[0012]

According to the arithmetic circuit of the present invention, the partial product generator obtains the partial product of the given multiplier and multiplicand,
Then, the obtained partial products are summed to generate first and second partial products, and the first and second partial products are stored in the first product register and the second product register.
The partial products stored in the first and second product registers are read by the carry-save adder. The carry-save adder performs a carry-save addition process on the read partial product and the data held in the accumulator to obtain the first and second partial sums. The first and second partial sums are input to an arithmetic logic operation unit, where a predetermined arithmetic logic operation is performed, and the arithmetic operation result is stored in an accumulator. The data stored in the accumulator is input to the carry-save adder and used for the arithmetic processing in the next cycle.

Further, according to the present invention, whether to perform the product-sum operation processing or the arithmetic logic operation processing is selected according to the input level of the selection signal input to the function selection circuit. The carry-save adder or the arithmetic logic operation unit performs the operation processing according to the function selection.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of an arithmetic circuit according to the present invention, and the same components as those in FIGS. That is, 1 is a multiplier storage register, 2 is a multiplicand storage register,
3a is a multiplier, 31 is a partial product generator, 32 is a partial product converter, 34L is a first product register, 34R is a second product register, 35 is a carry-save adder with three inputs and two outputs,
Reference numeral 5 is a 2-input 1-output arithmetic logic unit (ALU / adder), and 6 is an accumulator.

The multiplier 3a uses a carry-save adder 35 with three inputs and two outputs instead of the carry propagate adder 33 of the multiplier 3 shown in FIG.
_1, the first product register 34L and a second product register 34R are respectively provided between the two inputs of the partial product terms 32 and carry save type adder 35 which outputs the PP _2. The remaining 1 of the carry save adder 35
The output of the accumulator 6 is connected to the input, and the two outputs of the carry-save adder 35 are connected to the two inputs of the arithmetic and logic unit 5, respectively.

The first product register 34L is a partial product converter.
The partial product PP of the value PL obtained in 32 ₁Hold. Second
The product register 34R of is the value obtained by the partial product converter 32.
Partial product of PR PP₂Hold.

The carry-save adder 35 adds the data held in the first product register 34L, the second product register 34R, and the accumulator 6 in a carry-preserved form, and adds the data to the first and second parts. The sums PS ₁ and PS ₂ are obtained and output to the arithmetic and logic unit 5.

FIG. 2 is a diagram showing a configuration example of the carry-save adder 35, in which 35-1 to 35-n (FA1 to 35-n are shown.
FAn) indicates a full adder. The carry-save adder 35 has three inputs xn, yn, z as shown in FIG.
Unlike the carry propagate type adder shown in FIG. 7, the carry is not propagated to the upper side, but the carry is saved (SAVE) without being sent to the upper side and added when adding. The full adders 35-1 to 35-n output sum outputs S _{1 to} Sn and carry outputs C _{1 to} Cn.

Next, the operation of the above configuration will be described. M
When the AC operation is started, the multiplier M _i is stored in the multiplier storage register 1 and the multiplicand N _i is stored in the multiplicand storage register 2. The multiplier M stored in the multiplier storage register 1 in the partial product generator 31 of the multiplier 3a
_i and the partial product of the multiplicand N _i stored in the multiplicand storage register 2, for example determined based on the Booth algorithm. The plurality of partial products obtained by the partial product generator 31 are input to the partial product converter 32, where they are subtracted or added to be combined into _two partial products PP ₁ and PP ₂ , and the partial product PP ₁ is the first partial product PP ₁ . , And the partial product PP ₂ is stored in the second product register 34R.

First and second product registers 34R, 34
The partial product of the values PL _i and PR _i held in L is read by the carry-save adder 35. Further, the carry-save adder 35 receives the value A _i-1 obtained by the arithmetic and logic unit 5 in the MAC operation one cycle before and held in the accumulator 6. The carry-save adder 35 performs addition processing on the three inputs to generate the first and second partial sums PS ₁ , P 2.
S ₂ is calculated and output to the arithmetic and logic unit 5.

In the arithmetic logic operation unit 5, an arithmetic logic operation is performed based on the input first and second partial sums PS ₁ and PS ₂ , and the operation result is stored in the accumulator 6. As a result, the value A _{i of the} accumulator 6 becomes (A
_i-1 + P _i ), and the value A _{i of the} accumulator 6 is input to the carry-save adder 35 and used for the MAC operation of the next cycle. The above processing is normally sequentially performed every clock cycle.

As described above, according to this embodiment,
Accumulator 6, partial product generator 31 and partial product converter for calculating partial products of given multipliers and multiplicands, and for summing partial products to generate first and second partial products PP ₁ and PP ₂ . 32, and a first holding a _first partial product PP 1
Product register 34L, a second product register 34R that holds the _second partial product PP ₂ , and a first product register 34L,
The data held in the second product register 34R and the accumulator 6 are added, and the first and second partial sums P are added.
A carry-save adder 35 for obtaining S ₁ and PS ₂ ,
Since the carry-save adder 35 performs the arithmetic operation based on the first and second partial sums PS ₁ and PS ₂ and the arithmetic logic operation unit 5 for holding the arithmetic operation result in the accumulator 6, the digital signal is provided. The product-sum operation, which is essential for processing, can be speeded up, and the silicon area in the device can be reduced, thus preventing an increase in circuit scale. Further, the same instruction as that of the conventional circuit can be used as it is, and a DSP operable with a high speed clock can be easily realized.

FIG. 3 is a circuit diagram showing another configuration example of the main part of the arithmetic circuit according to the present invention. It should be noted that this configuration shows a configuration corresponding to i bits. In this circuit, a function selection circuit 36i is provided in front of the input of the full adder 35-i of the carry save type adder, and a normal arithmetic logic operation process is performed according to the input level of the selection circuit sel to the function selection circuit 36i. It is configured to switch between carry-save type addition processing.

The full adder 35-i is a sum generation circuit 351.
(Sum) and carry generation circuit 352 (carry). The sum generation circuit 351 has 3 inputs x
The exclusive OR of i ′, yi ′, and zi ′ is calculated, and the result is output as the sum output si. Carry generation circuit 352
Is (xi ′ · yi ′) + (xi ′ · zi ′) + (y
i ′ · zi ′) is obtained and output as a carry output ci.

The function selection circuit 36i is a 2-input OR circuit 3
61, two-input AND circuits 362 and 363, and an inverter 364. One input of the OR circuit 361 is connected to the input line of the data xi, and the other input is connected to the output of the inverter 364. The output of the OR circuit 361 is connected to the input xi ′ of the carry generation circuit 352 of the full adder 35-i. AND circuit 3
One input of 62 and 363 and the input of the inverter 364 are connected to the input line of the selection signal sel. The other input of the AND circuit 362 is connected to the input line of the data yi, and the midpoint of the connection is connected to the input yi ′ of the carry generation circuit 352 of the full adder 35-i. The output of the AND circuit 362 is connected to the input yi ′ of the sum generation circuit 351. The other input of the AND circuit 363 is connected to the input line of the data zi, and its output is the input zi ′ of the carry generation circuit 352 and the sum generation circuit 3
It is connected to the input zi 'of 51.

In such a circuit configuration, the selection signal s
When el is input to the function selection circuit 36i at low level "0", the sum output si of the full adder becomes si = xi and the carry output ci = yi. That is, when the selection signal sel is low level "0", the arithmetic logic unit (A
An operation equivalent to LU / adder) is performed. On the other hand, the selection signal sel is at the high level “1”.
In this case, an operation equivalent to that of the original carry-save adder described above is performed.

With such a structure, there is an advantage that a more multifunctional and efficient circuit can be realized with a small number of circuit elements.

[0028]

As described above, according to the arithmetic circuit of the present invention, it is possible to speed up the product-sum operation which is indispensable for digital signal processing, and to reduce the silicon area in the device and prevent an increase in the circuit scale. . Further, the same instruction as that of the conventional circuit can be used as it is, and a DSP operable with a high speed clock can be easily realized.

Further, since a function selection circuit for selecting whether to perform product-sum operation processing or arithmetic logic operation processing in accordance with the input of the selection signal is provided in the input stage of the carry-save type operation unit, a small number of circuits are provided. The element has an advantage that a multi-functional and efficient circuit can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an arithmetic circuit according to the present invention.

FIG. 2 is a diagram showing a configuration example of a carry-save adder used in the arithmetic circuit of FIG.

FIG. 3 is a circuit diagram showing another configuration example of the main part of the arithmetic circuit according to the present invention.

FIG. 4 is a block diagram showing a configuration example of an arithmetic circuit having a general MAC structure.

5 is a flow chart illustrating MAC operation based on the circuit of FIG.

6 is a block diagram showing a conventional configuration example of a multiplier used in the arithmetic circuit of FIG.

FIG. 7 is a block diagram showing a configuration example of a carry-provgate adder.

[Explanation of symbols]

1 ... Multiplier storage register 2 ... Multiplicand storage register 3a ... Multiplier 31 ... Partial product generator 32 ... Partial product converter 34L ... First product register 34R ... second product register 35 ... Carry-save adder 351 ... Sum generation circuit 352 ... Carry generation circuit 36i ... Function selection circuit 361 ... OR circuit 362, 363 ... AND circuit 364 ... Inverter 5 ... Arithmetic logic operation unit (ALU / adder) 6 ... Accumulator

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 7/52 G06F 17/10

Claims (2)

(57) [Claims] 1. An accumulator, a partial product generator for obtaining a partial product of a given multiplier and multiplicand, and obtaining a sum of the partial products to generate first and second partial products; A first product register that holds a partial product; a second product register that holds the second partial product; a data stored in the first product register, the second product register, and the accumulator; A carry-save adder for adding and obtaining first and second partial sums, and an arithmetic logic operation based on the first and second partial sums by the carry-save adder, and the arithmetic operation result is the accumulator. An arithmetic circuit having an arithmetic and logic unit to be held by the. 2. A function selection circuit for selecting whether to perform product-sum operation processing or arithmetic logic operation processing in accordance with an input of a selection signal, in the input stage of the carry-save operation unit. Arithmetic circuit.