JP3409425B2 - Imaging signal defect detection and correction apparatus and imaging signal defect detection and correction method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pick-up obtained from an image pick-up section having an image pick-up surface forming section in which a plurality of pixels are arranged in an array based on output signals from each of the plurality of pixels in the image pick-up surface forming section. contained in the signal, and detects a defect portion based on an output signal from a defective pixel in the imaging plane forming unit performs defect correction on the image pickup signal including the defect portion, the imaging signal defect detection and correction unit and an imaging signal defect
The present invention relates to a detection and correction method .

[0002]

2. Description of the Related Art In a solid-state image pickup section used for forming a video camera for forming a video signal, a large number of pixels for photoelectric conversion are formed in a parallel array on a semiconductor substrate, and The image pickup surface forming unit is provided with a charge transfer region formed of a charge coupled device (CCD) or the like for transferring the signal charge obtained in each pixel.
It is not easy for the image pickup surface forming unit in such a solid-state image pickup unit to have all of a very large number of pixels properly function in the manufacturing process thereof. It is likely that defective pixels will be included due to abnormal operation.
Further, even after the solid-state imaging unit is actually used, there is a possibility that the defective pixels may be partially included due to electrostatic breakdown or the like.

When a solid-state image pickup section having an image pickup plane forming section including defective pixels is used, the pixel forms an output signal from each pixel in the image pickup plane forming section. Sampling and reading are performed according to the selected reading column of a large number of parallel columns, and the output signal from the defective pixel is mixed as a noise component in the image pickup signal sequentially obtained by this, and image pickup is performed. Since the defective portion of the signal is formed, in the signal processing circuit portion which is supplied with the image pickup signal from the solid-state image pickup portion and forms the image pickup output signal based on the signal, the defective portion of the image pickup signal caused by the defective pixel is detected. Treatment, that is, defect correction is required to be performed.

Therefore, in the image pickup surface forming section provided in the solid-state image pickup section, a defective pixel included in the image pickup surface forming section is detected at a stage in which each pixel is in a proper operating state during its manufacturing process. A test for specifying the position is performed, and the position of the defective pixel found in the test in the imaging surface forming unit specifies, for example, each of parallel rows formed by a large number of pixels on the imaging surface forming unit. Read only stored as represented by vertical address data and horizontal address data identifying each of the pixels in each of the parallel columns.
It has been proposed that a memory (ROM) be prepared and a ROM containing defective pixel data be attached to the imaging surface forming unit. In this way, the imaging surface forming unit, which is associated with the ROM having the defective pixel data incorporated therein, can be used as a defective pixel obtained based on the output signal from each of the pixels in the actual use. RO is applied to the imaging signal including the defective portion caused by
Defect correction is performed according to the defective pixel data read from M, whereby the defective portion in the image pickup signal can be removed or reduced.

However, as described above, when the image pickup surface forming section is to be associated with the ROM containing the defective pixel data, each pixel in the manufacturing process is in a state in which it should properly operate. The tests for detecting and locating defective pixels performed in stages will be done under the construction of a very complex and expensive test system. Therefore, a large amount of cost is required to build a test system, and the number of man-hours dedicated to testing using it is considered to be relatively large.
There is a problem in that the manufacturing cost of the imaging surface forming unit will increase.

Further, the defective portion caused by the defective pixel included in the image pickup signal obtained based on the output signal from each pixel in the image pickup surface forming portion provided in the solid-state image pickup portion is read from the ROM. Although the countermeasure to perform the defect correction according to the defective pixel data is effective for the defective pixel generated in the manufacturing process of the image pickup surface forming unit, it can be corrected after the image pickup surface forming unit is actually used. ,
For example, the effect cannot be exerted on a defective pixel caused by electrostatic breakdown or the like.

Therefore, in order to deal with such a problem, prior to the actual image pickup operation in the solid-state image pickup unit, as described in Japanese Patent Application No. 5-307477 previously filed by the applicant of the present application, , Detecting a defective portion based on the output signal from the defective pixel, which is included in the imaging signal formed based on the output signal from each of the plurality of pixels arranged in the imaging surface forming unit, An operation of writing defective address data, which corresponds to the defective pixel causing the detected defective portion of the address data specifying each pixel, to the memory means, and an actual image pickup operation in the solid-state image pickup unit is performed. In response to the defect address data read from the memory means, the defect correction operation control signal is sent to the defect correction section for correcting the defect of the image pickup signal. Imaging signal defect detection and correction apparatus is proposed that is shall. According to such an image pickup signal defect detection and correction device, a complex and expensive test system for detecting and specifying the position of a defective pixel in the image pickup surface formation unit based on the image pickup signal obtained from the solid-state image pickup unit And the like, and including the defective pixels that have occurred after the imaging surface forming unit has been used for actual use, it is performed easily and surely and the result is saved, and after that, the detection is performed. The defective portion of the image pickup signal caused by the defective pixel is corrected appropriately while the timing is set based on the stored result of specifying the position of the defective pixel.

[0008]

As the solid-state image pickup unit, one having one image pickup surface forming unit and one having a plurality of image pickup surface forming units are known. For example, in order to obtain a color video signal for the imaged image, the image light from the imaged image is divided into red light, green light, and blue light using a spectral filter, and the imaged image is divided into a red light image, a green light image, and a red light image. An image is formed by decomposing it into a blue light image, and therefore, there is one that includes three image pickup surface forming units that pick up the red light image, the green light image, and the blue light image, respectively.

In the solid-state image pickup section having such a plurality of image pickup plane forming sections, the respective image pickup plane forming sections are independently configured, and the image pickup signals based on the images projected respectively are individually obtained. To be done. Therefore, when each of the plurality of imaging surface forming units includes a defective pixel, the output signal from the defective pixel is mixed as a noise component in the imaging signal obtained based on the image projected on the defective pixel. , A defective portion of the image pickup signal is to be formed. Therefore, even for a solid-state image pickup unit including a plurality of image pickup surface forming units, it is required to detect a defective portion in the obtained image pickup signal and perform correction on the detected defective portion. For example, the defect detection and correction by the image signal defect detection and correction device as described above is performed for each of the plurality of image pickup signals obtained based on the image projected on each of the plurality of image pickup surface forming units. It can be dealt with by doing.

At this time, the detection of the defective portion in each of the plurality of image pickup signals and the writing of the defective address data corresponding to the detected defective portion into the memory means are performed for each image pickup signal corresponding to each of the plurality of image pickup signals. Although a plurality of dedicated memory means are provided, the number of defective address data written in each memory means is limited to a predetermined maximum number or less due to the limitation of the memory capacity. Then, even if the detection is made, the defective portion for which the corresponding defective address data is not written in the memory means is not corrected.

Normally, the plurality of image pickup surface forming portions have different defective pixel existence states, and therefore,
The detection of the defective portion for each of the image pickup signals obtained on the basis of the image projected on each and the writing of the defective address data corresponding to the detected defective portion into the memory means have mutually different modes. Done. Therefore, for example, in the memory means dedicated to one of the plurality of image pickup signals, the number of defective address data desired to be written exceeds the predetermined maximum number,
It is assumed that there is defective address data that is not written to the memory means, whereas in the other memory means dedicated to another one of the plurality of imaging signals, the defective address that is desired to be written. There is a situation in which the number of data is made less than a predetermined maximum number, so that they are all written and then writable.

Under such a condition, the defect address data corresponding to the defective portion detected in one of the plurality of image pickup signals is used as a special address for another one of the plurality of image pickup signals. Even if the memory means is writable, it cannot be written to other memory means because of the exclusive relationship. Then, although writing is desired, the defective portion corresponding to the defective address data which is not written to the corresponding memory means is a defect corresponding to the defective address data written to the other memory means due to the limitation of the memory capacity. It is possible that there will be a situation of a relatively large scale, which is considered to be larger than the part. Under such a situation, when the plurality of memory means are viewed as a whole, the utilization rate for the memory means is not good, which results in wasteful memory capacity. However, the defect correction may not be sufficiently performed for the data including the defective portion corresponding to the defective address data which is desired to be written but is not written to the corresponding memory means.

In view of the above point, the present invention provides a plurality of image pickups formed on the basis of images respectively projected on a plurality of image pickup plane forming units each having a plurality of pixels arranged in an array. While detecting the defective portion based on the output signal from the defective pixel in the image pickup surface forming unit included in the signal, the defective address for the image pickup surface forming unit corresponding to the detected defective portion is stored in the memory means, and thereafter, Based on the defect address data read from the memory means, the operation of sending the defect correction operation control signal to the defect correction section that performs the defect correction on the image pickup signal is performed by the defect address related to the plurality of image pickup signals. The memory means provided for storing data is efficiently used, and each of the plurality of image pickup signals is written in the corresponding memory means due to the memory capacity limitation. Image signal defect to be performed under the condition that a relatively large-scale defective portion corresponding to the defective address data that is supposed to be left is left uncorrected. An object of the present invention is to provide a detection and correction device and an image pickup signal defect detection and correction method .

[0014]

In order to achieve the above-mentioned object, an image pickup signal defect detecting and correcting apparatus according to the present invention is provided with a plurality of image pickup planes each formed by arranging a plurality of pixels. Defective portion based on the output signal from the defective pixel in the imaging surface forming portion, which is included in the imaging signal from the imaging portion, which has a plurality of portions, and obtains a plurality of imaging signals formed based on the images projected respectively A signal defect detecting section for detecting a signal defect detection section, and when the signal defect detecting section detects a defective section, an identification data forming section for obtaining identification data for identifying the image pickup signal in which the defective section is detected, and a signal defect detecting section
Defect level that detects the level of the defect detected more
In addition to the detection unit, when a defective portion is detected by the signal defect detection unit, the defect of the address data that specifies each pixel in the imaging surface formation unit that is involved in the formation of the imaging signal for which the defective portion is detected The defect address data, which is supposed to correspond to the defective pixel causing the portion, is associated with the identification data from the identification data forming unit , and
The storage of the dress data in the data memory means is
Of the defective part corresponding to
A defect data storage unit is provided for performing the priority order according to the detected level, and is further identified by the identification data based on the defect address data and the identification data read from the data memory means in the defect data storage unit. The defect correction unit for the image pickup signal is provided with a control signal forming unit for transmitting a defect correction operation control signal. In particular, in the example of the image signal defect detection and correction apparatus according to the present invention, defect data storage unit, the storage in the data memory means at Moto made to correspond with the identification data of the defective address data, the defect address data It is assumed that the higher the level detected by the defect level detection unit of the defective portion corresponding to, the higher the level is stored in preference to the other, regardless of the corresponding identification data. It

Further, the image pickup signal defect detection and correction method according to the present invention has a plurality of image pickup plane forming portions each of which is formed by arranging a plurality of pixels in an array, and an image projected on each of them. A first step of detecting a defective portion based on an output signal from a defective pixel in the image pickup surface forming portion, which is included in the image pickup signal from the image pickup portion from which a plurality of image pickup signals formed based on When a defective portion is detected in the step, in addition to the second step of obtaining identification data specifying the image pickup signal in which the defective portion is detected, when the defective portion is detected in the first step, the defective portion is detected. Of the address data that specifies each pixel in the imaging surface formation section related to the formation of the image pickup signal for which the defect signal is detected, the defective pixel corresponding to the defective pixel that causes the defective portion. Les data, at the foot in correspondence with the identification data obtained by the second step, the defect address decoding
The storage of the data in the data memory means is
According to the priority according to the level of the defective part corresponding to
And a third step which is performed according to the defect address data and the identification data read from the data memory means, and sends the defect correction operation control signal to the defect correction section for the image pickup signal specified by the identification data. Fourth
Including steps. Particularly, in the example of the imaging signal defect detection and correction method according to the present invention, the storage in the data memory means under the correspondence with the identification data of the defect address data in the third step corresponds to the defect address data. The higher the level of the defective portion to be stored, the higher the level of the defective portion to be stored, the higher the level of the defective portion to be stored, regardless of the corresponding identification data.

[0016]

In the image signal defect detection and correction apparatus and the image signal defect detection and correction method according to the present invention thus configured, in the signal defect detection section or in the first step, a plurality of image plane formation sections are formed. A defective portion is detected for each of the plurality of image pickup signals formed based on the projected image, and when the defective portion is detected, the defective portion is detected in the identification data forming unit or the second step. Identification data for identifying the image pickup signal is formed, and the defective address data in the image pickup plane forming section relating to the formation of the image pickup signal in which the defective portion is detected in the defect data storage section or the third step is the identification data. And stored in the data memory means. Then, at that time, the storage in the data memory means in correspondence with the identification data of the defective address data is performed at the level of the defective portion corresponding to the defective address data.
According to the corresponding priority order, for example, the higher the level of the defective portion corresponding to the defective address data, the higher the priority of the other items. As a result, the memory capacity of the data memory means is wasted in the data memory means in the order of the defective address data and the identification data corresponding thereto, for example, in the order of the level of the defective portion corresponding to the defective address data. The data memory means is efficiently used.

Then, the defect address data read from the data memory means is discriminated as to which of the plurality of image pickup signals, based on the corresponding identification data, and is used for defect correction of the corresponding image pickup signals. .
Therefore, with respect to each of the plurality of imaging signals, it is possible to avoid a situation in which a relatively large-scale defective portion corresponding to defective address data that is not written in the data memory means is left uncorrected. Will be planned.

[0018]

1 is a block diagram of an image pickup signal defect detection and correction apparatus according to the present invention.
1 illustrates a video camera with a solid-state imager in which an example of a trough detection and correction method is implemented .

In FIG. 1, a large number of pixels, each of which performs photoelectric conversion, are formed and arranged in a large number of parallel columns, and a charge transfer formed by a CCD for transferring a signal charge obtained in each pixel. Red light image pickup surface forming unit (R-IPD) 10R, green light image pickup surface forming unit (G-IPD) 10G, and blue light image pickup surface forming unit (B-IPD). ) 10B is included in the imaging unit 11. A lens system OL, a diaphragm mechanism IL, an R-IPD. 10R
To the spectral filter FR, G-IPD. 10G
Filter FG which makes green light incident on the lens system OL and the diaphragm mechanism IL, and B-IPD.
10B is provided with an optical system 12 including a spectral filter FB for making blue light incident through the lens system OL and the diaphragm mechanism IL, and the like.
R-IPD. 10R, G-IPD. 10G and B-IP
D. The red light image, the green light image, and the blue light image of the imaged object image are projected on 10B, respectively.

R-IPD. 10R, G-IPD. 10G
And B-IPD. Each of 10B is configured by an interline transfer type image pickup surface forming unit as shown in FIG. 2, for example. In the imaging surface forming unit shown in FIG. 2, a large number of photoelectric conversion element units 15 each of which constitutes an individual pixel are arranged on a semiconductor substrate 13 in parallel rows (horizontal direction (direction of arrow h)). Pixel horizontal columns) are arranged and arranged. The photoelectric conversion element unit 15 forming each of a large number of pixel horizontal columns is
A large number of parallel columns (pixel vertical columns) extending in the vertical direction (direction of arrow v) are also formed, and CCD groups are formed along each pixel vertical column formed by such photoelectric conversion element section 15. The vertical charge transfer unit 16 is arranged. Each vertical charge transfer unit 16 has, for example, a two-phase vertical transfer drive signal φ.
The charge transfer operation is performed by being driven by V1 and φV2.

A charge read gate section 17 is provided between each of the plurality of photoelectric conversion element sections 15 forming each vertical column of pixels and the vertical charge transfer section 16 corresponding to the vertical column. In the charge read gate section 17, the read gate drive signal φ is associated with the photoelectric conversion element section 15 forming an odd-numbered pixel horizontal row (an odd pixel horizontal row).
The charge read state is set by GO, and the charge conversion is performed by the read gate drive signal φGE for the photoelectric conversion element portion 15 forming an even-numbered pixel horizontal column (even pixel horizontal column). It is assumed to be in a state.

One end side of each of the plurality of vertical charge transfer portions 16 is connected to a horizontal charge transfer portion 18 formed by a CCD group and extending in the horizontal direction at the edge of the semiconductor substrate 13. There is. The horizontal charge transfer unit 18 is driven by, for example, two-phase horizontal transfer drive signals φH1 and φH2 to perform a charge transfer operation. Further, the horizontal charge transfer section 18 is provided with a charge output section 19, and an output terminal 20 is derived from the charge output section 19.

As shown in FIG. 2, the R-IPD.
10R, G-IPD. 10G and B-IPD. When the image pickup operation is performed in the image pickup surface forming unit that constitutes each of 10B, first, a predetermined light receiving period is set, and in the light receiving period, the optical system 12 causes the red light image and the green light of the image pickup target to be picked up. An image or blue light image is projected. As a result, in the light receiving period, each of the plurality of photoelectric conversion element units 15 each forming a pixel performs photoelectric conversion according to the red light image, the green light image, or the blue light image of the imaging target, and accumulates charges. To do.

Thereafter, in the first charge read period, the drive signal forming section 25 to the R-IPD.
10R, G-IPD. 10G and B-IPD. By the read gate drive signal φGO supplied to each of 10B,
Each of the charge read gate sections 17 related to the photoelectric conversion element section 15 forming the odd-numbered pixel horizontal column is assumed to be in the charge read state, and the photoelectric conversion corresponding to each of the charge read gate sections 17 taking the charge read state is performed. The charges accumulated in the element unit 15 are read out to the corresponding vertical charge transfer unit 16. Subsequently, in the first charge transfer period subsequent to the first charge read period, the charges read to each vertical charge transfer unit 16 are transferred from the drive signal forming unit 25 to the R− in the image pickup unit 11.
IPD. 10R, G-IPD. 10G and B-IPD.
Two-phase vertical transfer drive signal φ supplied to each of 10B
Each vertical charge transfer unit 1 driven by V1 and φV2
By the charge transfer operation of 6, the portions obtained by the plurality of photoelectric conversion element units 15 forming each odd pixel horizontal column are sequentially addressed,
The charges are transferred toward the horizontal charge transfer unit 18.

In the horizontal charge transfer section 18,
From the drive signal forming unit 25 to the R-IP in the image pickup unit 11
D. 10R, G-IPD. 10G and B-IPD. 10
Two-phase horizontal transfer drive signal φH1 supplied to each B
And a charge transfer operation performed by being driven by φH2, the charges obtained by the plurality of photoelectric conversion element units 15 forming one of the odd pixel horizontal columns are sequentially transferred to the horizontal charge transfer unit 18. Are transferred to the charge output unit 19. In the charge output unit 19, the charges transferred by the horizontal charge transfer unit 18 are sequentially converted into a signal and led to the output terminal 20.

Next, in the second charge reading period following the first charge transfer period, the drive signal forming section 25 to the image pickup section 1
R-IPD. 10R, G-IPD. 10G and B-IPD. By the read gate drive signal φGE supplied to each of the 10B, each of the charge read gate sections 17 related to the photoelectric conversion element section 15 forming the even pixel horizontal column is set to the charge read state, and the charge read state is set. Through each of the charge read gate sections 17, the charges accumulated in the corresponding photoelectric conversion element section 15 are read out to the corresponding vertical charge transfer section 16. Subsequently, in the second charge transfer period subsequent to the second charge read period, the charges read to each vertical charge transfer unit 16 are transferred from the drive signal forming unit 25 to the R-IPD. 10R, G-IPD.
10G and B-IPD. 2 supplied to each of 10B
By the charge transfer operation of each vertical charge transfer unit 16 driven by the phase vertical transfer drive signals φV1 and φV2, the portions obtained by the plurality of photoelectric conversion element units 15 forming each even pixel horizontal column are sequentially, horizontally and horizontally. The charge is transferred toward the charge transfer unit 18.

In the horizontal charge transfer section 18,
From the drive signal forming unit 25 to the R-IP in the image pickup unit 11
D. 10R, G-IPD. 10G and B-IPD. 10
Two-phase horizontal transfer drive signal φH1 supplied to each B
And a charge transfer operation performed by being driven by φH2, the charges obtained by the plurality of photoelectric conversion element units 15 forming one of the even pixel horizontal columns are sequentially transferred to the horizontal charge transfer unit 18. Are transferred to the charge output unit 19. In the charge output unit 19, the charges transferred by the horizontal charge transfer unit 18 are sequentially converted into a signal and led to the output terminal 20.

Hereinafter, the charge read in the first charge read period, the charge transfer in the first charge transfer period, the charge read in the second charge read period, and the charge transfer in the second charge transfer period are sequentially performed. Repeated. Then, at the output terminal 20, the image pickup signal IR, IG, or IB corresponding to the red light image, the green light image, or the blue light image of the image pickup target based on the charges accumulated in the plurality of photoelectric conversion element portions 15 is obtained. . That is, R-IPD. The image pickup signal IR corresponding to the red light image from 10R is G-IPD. 10G
From the image signal IG corresponding to the green light image, and BI
PD. The image pickup signals IB corresponding to the blue light image are obtained from 10B, respectively.

In such a case, the R-IPD. 10R, GI
PD. 10G and B-IPD. In each of the vertical charge transfer units 16 of the charges obtained by the plurality of photoelectric conversion element units 15 forming each of the odd-numbered pixel horizontal columns in the image-forming surface forming unit configuring each of 10B, each vertical charge transfer unit 16 is addressed. The transfer to the horizontal charge transfer unit 18 ends within the odd field period, and the charges obtained by the plurality of photoelectric conversion element units 15 forming each of the even pixel horizontal columns are addressed to one pixel horizontal column. The transfer by each vertical charge transfer unit 16 to the horizontal charge transfer unit 18 is completed within the even field period, and a plurality of photoelectric conversions forming one pixel horizontal column are sequentially transferred to each of the horizontal charge transfer units 18. The two-phase vertical transfer driving is performed so that the supply of the charges obtained by the element unit 15 to the charge output unit 19 by the horizontal charge transfer unit 18 is completed within each line period. Issue φ
V1 and φV2 and two-phase horizontal transfer drive signals φH1 and φH2 are set, respectively. Therefore, R-IPD. 1
0R, G-IPD. 10G and B-IPD. The image pickup signals IR, IG, or IB derived to the output terminals 20 of the image pickup surface forming units forming the respective 10B are for odd field periods, which are formed by a series of line period units. And the even field period will be sequentially repeated.

Therefore, the R-IPD. 10R, G-IP
D. 10G and B-IPD. From 10B, in the odd field period, the imaging signals for the line period based on the charges obtained in the plurality of photoelectric conversion element units 15 forming each of the odd pixel horizontal columns are continuously formed by the number of the odd pixel horizontal columns. The image pickup signals IR, IG, and IB for one field period are obtained respectively, and the lines based on the charges obtained by the plurality of photoelectric conversion element units 15 forming each of the even pixel horizontal columns in the even field period are obtained. The image pickup signals IR, IG, and IB for one field period are formed in which the image pickup signals for the period are consecutively formed by the number of even-numbered pixel horizontal columns.

The drive signal forming section 25 has a vertical clock signal CLV, a horizontal clock signal CLH, and read command signals CRO and C from the timing signal forming section 26.
RE is supplied to form the read gate drive signal φGO according to the read command signal CRO, the read gate drive signal φGE according to the read command signal CRE, and the two-phase vertical transfer drive signals φV1 and φV2. Are formed based on the vertical clock signal CLV, and the two-phase horizontal transfer drive signals φH1 and φH2 are formed based on the horizontal clock signal CRH. Then, the drive signal forming unit 25 causes the read gate drive signal φG.
O, vertical transfer drive signals φV1 and φV2, and horizontal transfer drive signals φH1 and φH2 according to the read command signal CRO, and read gate drive signal φGE, vertical transfer drive signals φV1 and φV2, and horizontal transfer drive signal φH1
And φH2 in response to the read command signal CRE, respectively, in the R-IPD. 10R, G-IPD. 10
G and B-IPD. Supply to each of 10B.

The timing signal forming section 26 includes a vertical synchronizing signal SV and a horizontal synchronizing signal SH from the synchronizing signal generating section 27.
Is supplied, and further storage command signals CCO and CCE are supplied from the defect detection unit 35 described later, the vertical clock signal CLV is formed based on the horizontal synchronization signal SH, and the horizontal clock signal CLV is generated. The signal CLH is formed as a signal having a frequency significantly higher than that of the horizontal synchronizing signal SH, but synchronized with the horizontal synchronizing signal SH, and the read command signals CRO and CRE are respectively stored in the storage command signal C.
Based on CO and CCE, they are formed to correspond to the odd field period and the even field period, and they are supplied to the drive signal forming unit 25.

3 and 4 show the RI as described above.
PD. 10R, G-IPD. 10G and B-IPD. 1
The states of the image pickup signals IR, IG, and IB respectively obtained from 0B are shown. FIG. 3 mainly shows a state in the odd field period. For example, in the odd field period OF starting from the leading edge portion of the vertical synchronizing signal SV shown in FIG. 3B, as shown in FIG. As shown in D of FIG. 3, each of the odd pixel horizontal columns is formed after the thirteenth counted from the start time of the odd field period OF of the horizontal synchronizing signal SH shown in C of FIG. Imaging signals IR and I formed by a series of imaging signals for a line period based on the charges obtained by the photoelectric conversion element unit 15
G and IB are obtained. The odd number added to each line period in each of the image pickup signals IR, IG, and IB indicates the horizontal charge transfer of the odd-numbered pixel horizontal column in the image pickup surface formation unit where the charge forming the image pickup signal for the line period is obtained. Part 1
Indicates the number from the 8 side. In this example,
The odd field period OF from the time point preceding the start time of the odd field period OF by three line periods
20 from the start of the program until the 17-line period elapses
The period corresponding to the line period is actually the vertical blanking period TBLK.

Similarly, FIG. 4 mainly shows a state in the even field period, and as shown in A of FIG.
In the even field period EF starting from the front edge of the vertical synchronizing signal SV shown in FIG. 4B, for example, as shown in FIG.
14th from the start point of the even field period E-F of the horizontal synchronization signal SH shown in C (having a shift of 0.5 line period compared to the case of the odd field period OF). After that, as shown in D of FIG. 4, an image pickup is formed in which image pickup signals for a line period based on the charges obtained by the photoelectric conversion element units 15 forming each of the even pixel horizontal columns are formed in series. The signals IR, IG and IB are obtained. The even numbers attached to each line period in the image pickup signals IR, IG, and IB indicate the horizontal charge transfer unit 18 of the even-numbered pixel horizontal column in the image pickup plane forming unit where the charges forming the image pickup signal for the line period are obtained. Indicates the number from the side. Note that, also here, a period corresponding to a 20-line period from a time point that precedes the start time of the even field period E-F by 3 line periods to a time period of 17 line periods elapsed from the start time of the even field period E-F. Is actually the vertical blanking period TBLK.

The R-IPD. 10R,
G-IPD. 10G and B-IPD. The imaging signals IR, IG and IB respectively obtained from 10B are
It is supplied to the holding units 30R, 30G and 30B. In the sampling and holding unit 30R, the image pickup signal I
Level sampling for each predetermined short cycle and holding of the sample level are performed on R to obtain a sampling and holding output signal SIR, which is supplied to the analog / digital (A / D) conversion unit 31R. In the A / D converter 31R, the image pickup signal IR is digitized based on the sampling / holding output signal SIR, and the digital image pickup signal DIR corresponding to the image pickup signal IR is obtained from the A / D converter 31R. Then, it is supplied to the defect correction section 32R.

Similarly, the sampling and holding unit 30G
In (1), the sampling and holding output signal SIG is obtained by performing level sampling and holding of the sample level for each predetermined short cycle with respect to the imaging signal IG,
It is supplied to the A / D conversion unit 31G. In the A / D converter 31G, the sampling and holding output signal S
The image pickup signal IG is digitized based on the IG, the digital image pickup signal DIG corresponding to the image pickup signal IG is obtained from the A / D conversion unit 31G, and the digital image pickup signal DIG is supplied to the defect correction unit 32G. Further, in the sampling and holding unit 30B, the sampling and holding output signal SIB is performed by performing level sampling and holding of the sampling level for each predetermined short cycle with respect to the image pickup signal IB.
Is obtained and is supplied to the A / D conversion unit 31B. A
In the / D conversion unit 31B, the image pickup signal IB is digitized based on the sampling and holding output signal SIB, and the A / D conversion unit 31B obtains the digital image pickup signal DIB corresponding to the image pickup signal IB. , And is supplied to the defect correction unit 32B.

The defect correction instruction signals C sent from the defect detection unit 35 are sent to the defect correction units 32R, 32G and 32B.
DR, CDG and CDB are also provided respectively. In the defect correction section 32R, according to the defect correction instruction signal CDR,
R of the image pickup unit 11 included in the digital image pickup signal DIR
-IPD. Of the large number of photoelectric conversion element units 15 in 10R, the one causing the malfunction, that is, the defective portion caused by the defective pixel is corrected,
In the defect correction unit 32G, the G-IPD. Of the image pickup unit 11 included in the digital image pickup signal DIG is received according to the defect correction instruction signal CDG. The defect portion caused by the defective pixel in 10G is corrected, and further, in the defect correction unit 32G, the image pickup unit 11 included in the digital image pickup signal DIB according to the defect correction instruction signal CDB. B-IPD. Correction is made for the defective portion caused by the defective pixel in 10B.

Correction of a defective portion in the digital image pickup signal DIR corresponding to the defect correction instruction signal CDR in the defect correction section 32R, correction of a defective portion in the digital image pickup signal DIG corresponding to the defect correction instruction signal CDG in the defect correction section 32G, and , The digital image pickup signal DIB corresponding to the defect correction instruction signal CDB in the defect correction section 32B
For the correction of the defective portion in (1), a defect correction method for an image pickup signal obtained from the image pickup unit that has already been proposed is appropriately adopted. Then, the digital image pickup signal DRC, which is obtained by performing the defect correction according to the defective portion included in the digital image pickup signal DIR from the defect correction unit 32R, to the digital image pickup signal DIG from the defect correction unit 32G. Digital imaging signal DGC obtained by performing defect correction according to the defect portion included therein
However, a digital image pickup signal DBC obtained by further performing defect correction on the digital image pickup signal DIB according to the defect portion included therein by the defect correction section 32B,
They are sent out respectively.

The digital image pickup signal DRC obtained from the defect correction unit 32R, the digital image pickup signal DGC obtained from the defect correction unit 32G, and the digital image pickup signal DBC obtained from the defect correction unit 32B are supplied to the signal processing unit 33. . In the signal processing unit 33, various processes for each of the digital image pickup signals DRC, DGC, and DBC, and the digital image pickup signal DR on which various processes are performed
Synthesis of C, DGC and DBC, digital imaging signal DR
Various processes are performed on the signal obtained by combining C, DGC, and DBC, and the R-IP in the imaging unit 11 is performed.
D. 10R, G-IPD. 10G and B-IPD. 10
A video signal DV based on the image pickup signals IR, IG, and IB respectively obtained from B is formed, and this is led to the output terminal 34.

The defect detector 35 includes an A / D converter 31R.
Digital image pickup signal DIR from A / D converter 31G
Digital imaging signal DIG from A / D converter 31B
From the timing signal forming unit 26, the vertical direction clock signal CLV from the timing signal forming unit 26, the horizontal direction clock signal CRH, the read command signal CRO and the read command signal CRE, and the vertical synchronizing signal SV from the synchronizing signal generating unit 27.
The horizontal synchronizing signal SH, the reset signal CRS and the defect detection command signal CST from the control unit 36 are supplied. Then, the defect detection unit 35 determines that the digital image pickup signal DIR is R-IPD. 10R includes a defective portion caused by a defective pixel, the digital imaging signal DIG is G-IPD. Or when the digital imaging signal DIB contains a defective portion caused by a defective pixel in 10G
PD. When the defective portion caused by the defective pixel in 10B is included, the defective portion in the digital imaging signal DIR, DIG or DIB is detected, and the R-IP which is the cause of the detected defective portion is detected.
D. 10R, G-IPD. 10G or B-IPD.
10B, the defective pixel in R-IPD. 10R, G-
IPD. 10G or B-IPD. The defective image data DIR in which the defective portion is detected is specified by the vertical address AV and the horizontal address AH relating to 10B, and defective address data representing the vertical address AV and the horizontal address AH that specify the defective pixel, respectively. , DIG or DIB in correspondence with the identification data for specifying the DIG or DIB, and an appropriate timing is set based on the operation of storing in the built-in memory section and the defective address data and the identification data stored in the built-in memory section. Defect correction instruction signals CDR, CDG and C
The operation of forming DB and supplying them to the defect correction units 32R, 32G, and 32B is performed.

R-IPD. 10R, G-IPD. 10G
And B-IPD. 10B, the vertical address AV and the horizontal address AH are the vertical addresses AV and R-IPD. 10R, G-IPD. 10G and B-IPD. 10B is an address that specifies each of a large number of pixel horizontal columns in each of
H is R-IPD. 10R, G-IPD. 10G and B
-IPD. It is assumed that the address specifies the position of each pixel in each pixel horizontal column in each of 10B. Therefore, the address represented by the defective address data is R-IPD. 10R, G-IPD. 10G and B-
IPD. 10B includes a vertical address AV that specifies the pixel horizontal column to which the defective pixel belongs, and a horizontal address AH that specifies the position of the defective pixel in the pixel horizontal column specified by the vertical address AV. To be done.

Further, the defect detecting section 35 supplies the storage command signals CCO and CCE to the timing signal forming section 26 through such an operation, and detects a defective portion in the digital image pickup signal DIR, DIG or DIB. The R-IPD. 10R, G-IPD. 10G or B
-IPD. When the operation of storing the defective address data specifying the defective pixel in 10B in association with the identification data in the built-in memory unit is completed, the detection end signal CE is output.
To the control unit 36.

The control unit 36 controls the defect detector 35 to
A defective portion in the digital imaging signal DIR, DIG or DIB is detected, and the R-IPD. 10R, G-IPD. 10G or B-IPD. A defect detection operation switch 37 is provided which is operated to store the defective address data for specifying the defective pixel in 10B in association with the identification data in the built-in memory section. When the defect detection operation switch 37 is turned on by operating the defect detection operation switch 37, the control unit 36 first supplies the reset signal CRS to the defect detection unit 35, and then the defect detection command signal CST. After that, the defect detection unit 3
Until the detection end signal CE arrives from 5, the defect detection unit 3
5 and the drive signal forming section 25, respectively.

The drive signal forming section 25 includes a control unit 36.
When the defect detection command signal CST from is supplied, the diaphragm mechanism drive signal CI supplied to the diaphragm mechanism IL is caused to cause the diaphragm mechanism IL to take all the diaphragm states. When the diaphragm mechanism IL is in the full diaphragm state,
The R-IPD. 10R, G-IPD.
10G and B-IPD. 10B is maintained in a state where substantially no outside light is incident. After that, the drive signal forming unit 25
Defect detection command signal CS from the control unit 36 for the
When the supply of T is stopped, the drive signal forming unit 25 returns the diaphragm mechanism drive signal CI supplied to the diaphragm mechanism IL to that which causes the diaphragm mechanism IL to assume the state before the supply of the defect detection command signal CST. .

When the reset signal CRS from the control unit 36 is supplied, the defect detecting section 35 responds to the reset signal CRS.
The defective address data and identification data stored in the built-in memory unit are erased to prepare for writing new defective address data and identification data to the built-in memory unit. Then, in response to the defect detection command signal CST coming from the control unit 36, the diaphragm mechanism I
Under the condition that L is in the full aperture state, the defective portion in the digital image pickup signal DIR, DIG or DIB is detected, and the detected defective portion is caused by the R-IPD. 10R, G-IPD. 10G and B-
IPD. The operation of storing the defective address data specifying the defective pixel in 10B in the built-in memory unit in association with the identification data is started.

FIG. 5, FIG. 6 and FIG. 7 show an example of a specific configuration of the defect detecting section 35. In this example, the vertical sync signal SV from the sync signal generator 27 is supplied to the signal input terminal 40 (FIG. 6). The vertical synchronization signal SV is A in FIG.
As shown in FIG. 8, the odd field period OF and the even field period E-F are alternately set by each cycle as shown in FIG. 8B. Further, the vertical direction clock signal CLV and the horizontal direction clock signal CLH from the timing signal forming unit 26 are supplied to the signal input terminals 41 and 42 (FIG. 6), respectively.

The defect detection operation switch 37 provided in the control unit 36 is operated to be turned on, and accordingly, the reset signal CRS and the subsequent defect detection command signal CST are sent from the control unit 36. Then, the defect detection command signal CST is supplied to the signal input terminal 43 (FIG. 6) at the timing as shown in C of FIG. When the defect detection command signal CST is supplied to the signal input terminal 43 as shown in C of FIG. 8, the supply start time of the defect detection command signal CST is the R-IPD. 10R, G-
IPD. 10G and B-IPD. Digital image pickup signals DIR, DIG and DIB based on the image pickup signals IR, IG and IB respectively obtained from 10B are formed, and a video signal DV formed based on the digital image pickup signals DIR, DIG and DIB is output terminal 34. It is assumed to be within the video signal output period TCO, which is the period during which the derived operation is performed. In such a video signal output period TCO, the signal input terminals 44R, 44G and 44B (FIG. 5)
The digital imaging signals DIR, DIG and DIB
As shown in G of FIG. 8, they are supplied respectively.

Each of the digital image pickup signals DIR, DIG, and DIB supplied to the signal input terminals 44R, 44G, and 44B is R-IPD.D in the odd field period OF. 10R, G-IPD. 10G and B-
IPD. An odd line field period signal OLF formed by a series of imaging signals for a line period based on the charges obtained in the photoelectric conversion element unit 15 forming each odd pixel horizontal column in each of 10B is formed as an even line field. In the period EF, the R-IPD. 10R, G-
IPD. 10G and B-IPD. An even line field period signal ELF is formed by a series of imaging signals for a line period based on the charges obtained in the photoelectric conversion element unit 15 forming each of the even pixel horizontal columns in each of 10B.

Further, before the defect detection command signal CST is supplied during the video signal output period TCO, the accumulation command signal generation unit 45 to which the vertical synchronizing signal SV is supplied through the signal input terminal 40 is supplied through the signal input terminal 43. The defect detection command signal CST is not supplied, so that the accumulation command signal CCO obtained from the accumulation command signal generation unit 45 is obtained.
And CCE are as shown in D and E of FIG. 8, respectively.
Each of them has a period which is twice as long as that of the vertical synchronizing signal SV and is a pulse signal which appears alternately in synchronization with the vertical synchronizing signal SV.

When the defect detection command signal CST is supplied to the storage command signal generation unit 45 through the signal input terminal 43, the storage command signal generation unit 45 thereafter starts supplying the defect detection command signal CST. The storage command signal CCO is provided as a pulse signal synchronized with the third vertical synchronization signal SV.
Is generated, the storage command signal CCO is not generated until a preset time, for example, a period TCGO corresponding to an n field period (n ≧ 6) has elapsed, and then the period T
When CGO elapses, the accumulation command signal CCO has a cycle that is twice as long as that of the vertical synchronization signal SV.
The storage command signal CCE is generated as a pulse signal synchronized with V, and immediately before the start of supply of the defect detection command signal CST, as a pulse signal synchronized with the vertical synchronization signal SV.
After generation of the storage command signal CCE, a storage command signal CCE is not generated until a preset period TCGE corresponding to the n-field period elapses, and when the period TCGE elapses thereafter, the storage command signal CCE is Vertical sync signal SV
, And after a period corresponding to 6 field periods, the storage command signal CCE has a period twice that of the vertical synchronization signal SV and then the vertical synchronization signal SV is generated again. It is generated as a pulse signal synchronized with.

As shown in D and E of FIG. 8, the period T
The storage command signal CCO that does not appear in CGO and the storage command signal CCE that does not appear in the period TCGE are supplied to the memory write control signal generation unit 46 and the timing signal formation unit 2
6 is supplied. The timing signal forming unit 26 outputs the read command signals CRO and CRE to the storage command signal CCO, respectively.
And a pulse train signal generated in synchronization with CCE. Therefore, within the period TCGO, the R-IPD. 10
R, G-IPD. 10G and B-IPD. The read gate drive signal φGO is not supplied to each of 10B,
-IPD. 10R, G-IPD. 10G and B-IP
D. The charges obtained by the photoelectric conversion element units 15 forming each of the odd-numbered pixel horizontal columns in each of 10B are not read out to the vertical charge transfer unit 16 and, in the period TCGE, the charges are not read from the drive signal formation unit 25. The R-IPD. 10R, G-IPD. 10G and B-IP
D. The read gate drive signal φGE is not supplied to each of the R-IPD. 10R, G-IPD. 10
G and B-IPD. The charges obtained by the photoelectric conversion element units 15 forming the even-numbered pixel horizontal columns in each of the pixels 10B are not read out to the vertical charge transfer units 16.

Thus, in the period TCGO, the R-IPD. 10R, G-IPD. 10G and B-
IPD. The photoelectric conversion element portions 15 forming each of the odd-numbered pixel horizontal columns in each of 10B are placed in the charge accumulation state,
In the period TCGE, the R-IPD. 10R,
G-IPD. 10G and B-IPD. Photoelectric conversion element unit 1 forming each of the even pixel horizontal columns in each of 10B.
5 will be in the charge accumulation state, but during the period TCG
In the period including both O and the period TCGE,
Since the diaphragm mechanism IL arranged in front of the image pickup unit 11 is assumed to be in the full diaphragm state, the R-IPD. 10R, G
-IPD. 10G and B-IPD. External light is not substantially incident on each of 10B, and no charge is accumulated by the external light in the photoelectric conversion element section 15.

When the end time of the period TCGO arrives, the storage command signal generator 45 outputs the storage command signal CCO.
Is generated as a pulse signal that appears in synchronism with the vertical synchronizing signal SV, which is generated by the timing signal forming unit 26.
Is supplied to. As a result, the timing signal forming unit 26
Is the read command signal CR at the end of the period TCGO.
O is sent as a pulse train signal that is issued in synchronization with the storage command signal CCO. As a result, the drive signal forming unit 25
From the R-IPD. 10R, G-IP
D. 10G and B-IPD. Read gate drive signal φGO, vertical transfer drive signals φV1 and φV to 10B, respectively.
2, and the supply of the horizontal transfer drive signals φH1 and φH2 is started at the end of the period TCGO, and R-I
PD. 10R, G-IPD. 10G and B-IPD. 1
Vertical charge transfer unit 16 of charges obtained in photoelectric conversion element unit 15 forming each of odd-numbered pixel horizontal columns in each of 0B
To the vertical charge transfer unit 16 and the horizontal charge transfer unit 18 to transfer the read charges to
It starts at the end of the period TCGO.

Similarly, when the end point of the period TCGE arrives, the accumulation command signal generator 45 outputs the accumulation command signal CCE.
Is generated as a pulse signal that appears in synchronism with the vertical synchronizing signal SV, which is generated by the timing signal forming unit 26.
Is supplied to. As a result, the timing signal forming unit 26
Is the read command signal CR at the end of the period TCGE.
E is sent as a pulse train signal that is issued in synchronization with the storage command signal CCE. As a result, the drive signal forming unit 25
From the R-IPD. 10R, G-IP
D. 10G and B-IPD. Read gate drive signal φGE, vertical transfer drive signals φV1 and φV to 10B, respectively.
2, and the supply of the horizontal transfer drive signals φH1 and φH2 is started at the end of the period TCGE, and R-I
PD. 10R, G-IPD. 10G and B-IPD. 1
Vertical charge transfer unit 16 of charges obtained by photoelectric conversion element unit 15 forming each of the even pixel horizontal columns in each of 0B
To the vertical charge transfer unit 16 and the horizontal charge transfer unit 18 to transfer the read charges to
It starts at the end of the period TCGE.

In such a case, R-IPD. 10R, G
-IPD. 10G and B-IPD. In each of 10B, the charge obtained in the photoelectric conversion element unit 15 is read to the vertical charge transfer unit 16, and the read charge is transferred by the vertical charge transfer unit 16 and the horizontal charge transfer unit 18 by R -IPD. 10R, G-IPD. 10G and B-
IPD. It also includes reading and transfer of charges from the regions that do not directly contribute to the formation of the imaging signals IR, IG, and IB in each of 10B, and is performed over a period longer than the normal one field period. Thereby, R-I
PD. 10R, G-IPD. 10G and B-IPD. 1
From 0B, the image pickup signal IR indicating the charge state of the photoelectric conversion element unit 15 forming each of the odd-numbered pixel horizontal columns when the period TCGO elapses under the condition that the outside light is not substantially incident, IG and IB are obtained respectively, and accordingly, digital image pickup signals DIR, DIG and DIB based on the image pickup signals IR, IG and IB at that time are input to the signal input terminals 44R, 44G and 44B, respectively.
Are supplied in the period TDDO, which is a period longer than one field period starting from the end point of the period TCGO, as shown in G of FIG. Also, in the same way,
R-IPD. 10R, G-IPD. 10G and B-IP
D. From 10B, the photoelectric conversion element unit 1 forming each of the even pixel horizontal columns when the period TCGE elapses under the condition that the outside light does not substantially enter from 10B.
The image pickup signals IR, IG, and IB representing the charge state of No. 5 are obtained, and accordingly, the signal input terminals 44R and 44 are obtained.
G and 44B have image pickup signals IR, IG and I at that time.
The digital image pickup signals DIR, DIG and DIB based on B are supplied in the period TDDE, which is a period longer than one field period starting from the end point of the period TCGE, as shown in G of FIG.

From the memory write control signal generator 46 to which the accumulation command signals CCO and CCE issued from the accumulation command signal generator 45 are supplied, the accumulation command signal CCE supplied at the end of the period TCGE and the period TCG
Depending on the storage command signal CCO supplied at the end of O, as shown in F of FIG. 8, over the two field periods from the end of the period TCGE, and the period TC.
Over the two-field period from the end of GO,
The memory write control signal CWC having a high level is sent out and supplied to the control terminals of the respective data memory units 47A, 47B, 47C and 47D in which defective data described later is stored. Data memory units 47A, 47
In each of B, 47C and 47D, the memory write control signal CWC supplied from the memory write control signal generator 46 is
It is possible to write data only when it takes a high level,
At other times, the data can be read or the data can be erased. Therefore, the signal input terminal 44
Digital image pickup signal D to R, 44G and 44B respectively
When IR, DIG, and DIB are supplied in the period TDDE and the period TDDO as shown in G of FIG. 8, the data memory units 47A, 47B, 47 are used.
Each of C and 47D is placed in a state where data can be written.

The digital image pickup signal DI supplied to the signal input terminal 44R in the periods TDDE and TDDO.
The black level of R is fixed at the clamp portion 50R,
Further, in the blanking unit 51R, the R-IPD.
A portion other than the portion obtained on the basis of the charges from the photoelectric conversion element portion 15 forming each pixel horizontal column in 10R is blanked, and it is supplied to the level comparing portion 52R as a digital image pickup signal DIR '. . Also, the period T
The digital imaging signal DIG supplied to the signal input terminal 44G in the DDE and the period TDDO is the clamp unit 5
0G, the black level is fixed, and the blanking unit 51G further sets the G-IPD. A portion other than the portion obtained on the basis of the charges from the photoelectric conversion element portion 15 forming each pixel horizontal column in 10G is blanked, and it is supplied to the level comparison portion 52G as a digital image pickup signal DIG '. . Furthermore, the period TDDE and the period T
The black level of the digital image pickup signal DIB supplied to the signal input terminal 44B in DDO is fixed in the clamp section 50B, and further, in the blanking section 51B, the G-IPD. A portion other than a portion obtained on the basis of charges from the photoelectric conversion element portion 15 forming each pixel horizontal column in 10B is blanked, and a digital image pickup signal DIB ′ is supplied to the level comparison portion 52B. .

Such digital image pickup signals DIR ', DI
G ′ and DIB ′ are R-IPD. 10R, G-IPD. 10G and BI
PD. Since each of 10B is based on the image pickup signals IR, IG, and IB obtained under the condition that the outside light is not substantially incident, each of the R-IPD. 10
R, G-IPD. 10G and B-IPD. The level in each of the pixels of 10B, that is, the photoelectric conversion element section 15 is supposed to be low under the proper operation. In other words, the digital imaging signals DIR ', DIG' and DI
In each of B ′, if there is a portion that takes a relatively large level, that portion is R-IPD. 10R, G-IP
D. 10G or B-IPD. This is a defective portion due to the defective pixel in 10B.

Reference level data DX representing a preset reference level from the reference level generating section 53 is supplied to each of the level comparing sections 52R, 52G and 52B. Then, in the level comparing section 52R, the level of the digital image pickup signal DIR 'is compared with the reference level represented by the reference level data DX, and when the level of the digital image pickup signal DIR' is below the reference level from the level comparing section 52R. When the level of the digital image pickup signal DIR 'exceeds the reference level, the level comparison data DDR representing the high level is obtained. Therefore, when the digital image pickup signal DIR 'is appropriate and has a relatively small level, level comparison data DDR representing a low level is obtained, and the digital image pickup signal DIR' takes a relatively large level. In the case where the defective portion is included, the level comparison data DDR representing a high level corresponding to the defective portion.
Therefore, the defective portion included in the digital image pickup signal DIR ′ is detected by the level comparison data DDR indicating a high level.

In the level comparing section 52G, the level of the digital image pickup signal DIG 'and the reference level data D
The reference level represented by X is compared, and the level comparison unit 5
From 2G, level comparison data DDG that represents a low level when the level of the digital imaging signal DIG ′ is equal to or lower than the reference level and a high level that represents when the level of the digital imaging signal DIG ′ exceeds the reference level is obtained. Therefore, when the digital image pickup signal DIG 'is proper and has a relatively small level, level comparison data DDG representing a low level is obtained, and the digital image pickup signal DIG' takes a relatively large level. In the case of including a defective portion defined as, the level comparison data DDG representing the high level is obtained corresponding to the defective portion, and the digital image pickup signal DI is obtained.
The defective portion included in G ′ is detected by the level comparison data DDG representing a high level.

Further, the level comparing section 52B compares the level of the digital image pickup signal DIB 'with the reference level represented by the reference level data DX, and the level comparing section 52B shows that the level of the digital image pickup signal DIB' is equal to or lower than the reference level. Level comparison data DDB representing a low level at a certain time and a high level at a level of the digital image pickup signal DIB ′ exceeding the reference level are obtained. Therefore, when the digital image pickup signal DIB 'is proper and has a relatively small level,
Level comparison data DDB representing the low level is obtained,
When the digital image pickup signal DIB ′ includes a defective portion which is assumed to have a relatively large level, the level comparison data DDB representing a high level is obtained corresponding to the defective portion, Digital imaging signal D
The defective portion included in IB ′ is the level comparison data DDB.
Is detected as being high level.

The level comparison data DDR obtained from the level comparison unit 52R, the level comparison data DDG obtained from the level comparison unit 52G, and the level comparison data DDB obtained from the level comparison unit 52B are supplied to the OR circuit 55. , And is supplied to the identification data forming unit 77 through the signal input terminals 54R, 54G and 54B (FIG. 6), respectively.

Blanking units 51R, 51G and 51B
The digital image pickup signals DIR ′, DIG ′ and DIB ′ obtained from the above are also supplied to the level data forming units 60R, 60G and 60B, respectively. Level data forming unit 60R
, Level data DER representing the level of the digital image pickup signal DIR 'is formed, and in the level data forming unit 60G, the digital image pickup signal DI is formed.
Level data DEG representing the level of G'is formed, and further, level data DEB representing the level of the digital image pickup signal DIB 'is formed in the level data forming section 60B. Then, the level data DER, DEG, and DEB obtained from the level data forming units 60R, 60G, and 60B are supplied to the adding unit 61.
It is supplied to each of the gate sections 63A, 63B, 63C and 63D, and the level data comparison sections 56A, 56 are also provided.
It is supplied to one of the comparison input terminals of each of B, 56C and 56D.

In the digital image pickup signals DIR ', DIG' and DIB ', since the defective portions contained in each take a high level, the level data DER, DEG and
The DEB represents a relatively high level corresponding to the defective portion included in each of the digital image pickup signals DIR ', DIG' and DIB '.

The level data DLA stored in the level data memory unit 65A is connected to the other of the comparison input terminals of the level data comparison unit 56A.
The level data comparison unit 56 is read from A and supplied.
The level data DLB stored in the level data memory unit 65B is read from the level data memory unit 65B and supplied to the other of the comparison input terminals of B, and the other of the comparison input terminals of the level data comparison unit 56C is supplied to the other. , The level data D stored in the level data memory unit 65C
LC is read from the level data memory unit 65C and supplied, and the level data DLD stored in the level data memory unit 65D is supplied to the other comparison input terminal of the level data comparison unit 56D. It is read out from 65D and supplied.

Further, the level data comparison units 56A, 56
Output data DDH obtained from the OR circuit 55 is supplied to the control terminals of B, 56C and 56D, respectively. The output data DDH from the OR circuit 55 represents a high level when at least one of the level comparison data DDR, DDG and DDB obtained from the level comparison units 52R, 52G and 52B represents a high level, and Comparison data DDR, DDG and DDB
Represents a low level when is all a low level. Therefore, the output data DD from the OR circuit 55
H is a digital image pickup signal DIR ', DIG' and DI
When a defective portion included in any of B'is detected, it indicates a high level. Then, each of the level data comparison units 56A, 56B, 56C, and 56D, when the output data DDH from the OR circuit 55 represents a high level, that is, the digital image pickup signal DI.
When a defective portion included in any one of R ′, DIG ′, and DIB ′ is detected, the level comparison operation state is assumed.

In the level data comparison unit 56A, when the level comparison operation state is taken in accordance with the output data DDH from the OR circuit 55 which represents the high level, the level data DE supplied through the addition unit 61.
The level represented by each of R, DEG, and DEB is compared with the level represented by the level data DLA read from the level data memory unit 65A. And
From the level data comparison unit 56A, the level data DER,
When the level represented by either DEG or DEB is higher than the level represented by the level data DLA, a comparison output signal CLA which takes a high level and otherwise takes a low level is obtained.

Similarly, in the level data comparison unit 56B, when the level comparison operation state is taken in accordance with the output data DDH from the OR circuit 55 which represents the high level, it is supplied through the addition unit 61. The level represented by each of the level data DER, DEG, and DEB is compared with the level represented by the level data DLB read from the level data memory unit 65B.
A comparison output signal from the level data comparison unit 56B that takes a high level when the level represented by any of the level data DER, DEG, and DEB is higher than the level represented by the level data DLB, and takes a low level otherwise. CLB is obtained.

Further, in the level data comparison unit 56C, when the level comparison operation state is taken according to the output data DDH from the OR circuit 55 which is expressed as a high level, the level supplied through the addition unit 61. The level represented by each of the data DER, DEG, and DEB is compared with the level represented by the level data DLC read from the level data memory unit 65C.
A comparison output signal from the level data comparison unit 56C that takes a high level when the level represented by any of the level data DER, DEG, and DEB is higher than the level represented by the level data DLC, and takes a low level otherwise. CLC is obtained.

Further, in the level data comparing section 56D, when the level comparing operation state is taken in accordance with the output data DDH from the OR circuit 55 which represents the high level, the level supplied through the adding section 61. The level represented by each of the data DER, DEG, and DEB is compared with the level represented by the level data DLD read from the level data memory unit 65D.
A comparison output signal from the level data comparison unit 56D that takes a high level when the level represented by any of the level data DER, DEG, and DEB is higher than the level represented by the level data DLD, and takes a low level otherwise. CLD is obtained.

The comparison output signal CLA obtained from the level data comparison unit 56A is supplied to the AND circuit 62A through the inverter 61A. Also, the level data comparison unit 5
The comparison output signal CLB obtained from 6B is the AND circuit 6
2A, and also to the AND circuit 62B through the inverter 61B.
The comparison output signal CLC obtained from C is the AND circuit 62.
B is supplied to the AND circuit 62C through the inverter 61C and the level data comparison unit 56D.
The comparison output signal CLD obtained from the
Is supplied to. Output signals CLB ′, CLC ′ and CLD ′ are obtained from the AND circuits 62A, 62B and 63C.

Under the circumstances, the level data comparison unit 56
When the level comparison operation state is taken in each of A, 56B, 56C, and 56D, and the comparison output signal CLA obtained from the level data comparison unit 56A is set to the high level, the comparison output signal CLA which takes the high level
Is supplied to the control end of the gate unit 63A and the control end of the gate unit 66A, is also supplied to the control end of the gate unit 66B as the control signal CP through the adder 67, and is further supplied to the control signal CQ through the adder 68. As gate 6
It is supplied to the control end of 6C, and gate parts 63A, 66A,
Each of 66B and 66C is turned on. Thereby, the level data DE obtained from the adding unit 61 at that time
Any of R, DEG, and DEB is stored in the level data memory unit 65A as updated level data DLA through the gate unit 63A, and at the same time, the level data DLA previously stored in the level data memory unit 65A is stored in the level data memory unit 65A. , The level data DLB stored in the level data memory unit 65B as the updated level data DLB through the gate unit 66A and the addition unit 64B, and the level data DLB previously stored in the level data memory unit 65B.
Of the level data memory unit 6 as updated level data DLC through the gate unit 66B and the addition unit 64C.
The level data DLC stored in the level data memory unit 65C is stored in the level data memory unit 65D as updated level data DLD through the gate unit 66C and the addition unit 64D.

Level data comparison units 56A, 56B, 56
When the level comparison operation state is set in each of C and 56D and the output signal CLB ′ obtained from the AND circuit 62A is set to the high level, that is, the comparison output signal which takes the low level from the level data comparison section 56A. When CLA is obtained and the comparison output signal CLB having a high level is obtained from the level data comparison unit 56B, the output signal CLB ′ having a high level is supplied to the control end of the gate unit 63B and the addition unit 67 is also provided. Is supplied to the control end of the gate section 66B as a control signal CP through the addition section 68, and is further supplied to the control end of the gate section 66C as a control signal CQ via the addition section 68 to the gate sections 63B and 66B.
And 66C are turned on. As a result, the level data DER, D obtained from the adder 61 at that time
Either EG or DEB is stored in the level data memory unit 65B as updated level data DLB through the gate unit 63B and the addition unit 64B, and at the same time, the level data previously stored in the level data memory unit 65B. The DLB is stored in the level data memory unit 65C as updated level data DLC through the gate unit 66B and the addition unit 64C, and the level data DLC previously stored in the level data memory unit 65C is changed to the gate unit 66C. Then, it is stored in the level data memory unit 65D as updated level data DLD through the addition unit 64D.

Level data comparison units 56A, 56B, 56
When the level comparison operation state is set in each of C and 56D, and the output signal CLC ′ obtained from the AND circuit 62B is set to the high level, that is, the comparison output signal which takes the low level from the level data comparison unit 56B. When CLB is obtained and the comparison output signal CLC having a high level is obtained from the level data comparison unit 56C, the output signal CLC ′ having a high level is supplied to the control terminal of the gate unit 63C and the addition unit 68 is also provided. Is supplied to the control end of the gate section 66C as a control signal CQ through
Each of the gate portions 63C and 66C is turned on.
As a result, any one of the level data DER, DEG, and DEB obtained from the addition unit 61 at that time is stored in the level data memory unit 65C as updated level data DLC through the gate unit 63C and the addition unit 64C. Until then, the level data memory unit 65
The level data DLC stored in C is transferred to the gate unit 6
6C and the addition unit 64D, it is stored in the level data memory unit 65D as updated level data DLD.

Further, the level data comparison units 56A, 56
An output signal C obtained from the AND circuit 62C when the level comparison operation state is set in each of B, 56C and 56D.
When LD 'takes a high level, that is, the level data comparing section 56C obtains a low level comparison output signal CLC and the level data comparing section 56D obtains a high level comparison output signal CLD. At that time, the output signal CLD ′ having the high level is supplied to the control end of the gate section 63D, and the gate section 63D is turned on. As a result, any one of the level data DER, DEG, and DEB obtained from the adding unit 61 at that time is passed through the gate unit 63D and the adding unit 64D as the updated level data DLD to the level data memory unit 65.
Stored in D.

The level data comparison units 56A, 56
As a result of the level comparison operation state in each of B, 56C and 56D, a comparison output signal CLA obtained from the level data comparison unit 56A, an output signal CLB ′ obtained from the AND circuit 62A, an output signal obtained from the AND circuit 62B. When both CLC 'and the output signal CLD' obtained from the AND circuit 62C are low level, the level data memory unit of the level data DER, DEG or DEB obtained from the adding unit 61 at that time It is not stored in any of 65A, 65B, 65C and 65D.

By doing so, the period TDD
E and the period TDDO, the digital imaging signal DI
A defective portion included in any one of R ', DIG', and DIB 'is detected, and output data DDH from the OR circuit 55 is detected.
Is taken to have a high level, level data DER, D representing the level of the detected defective portion.
Either EG or DEB is the level data memory unit 6
5A as level data DLA, level data memory section 65B as level data DLB, level data memory section 65C as level data DLC, or
The state where the level data memory unit 65D stores the level data DLD, or the level data memory unit 6
It is in a state where it is not stored in any of 5A, 65B, 65C and 65D. As a result, level data DLA to DLD representing the levels of the defective portions detected in the digital imaging signals DIR ', DIG', and DIB 'are stored in the level data memory units 65A, 65B, 65C, and 65D, respectively. The higher the level represented, the higher the priority, and the level represented by the level data DLA ≧ the level represented by the level data DLB ≧
The data is stored in such a manner that the level represented by the level data DLC ≧ the level represented by the level data DLD is established.

Further, at this time, the vertical clock signal CLV through the signal input terminal 41 is supplied to the vertical address counter (V-address counter) 70, and
Horizontal clock signal CLH through the signal input terminal 42
Is a horizontal address counter (H-address counter)
71. Further, the V-address counter 70
Of the read command signals CRO and C, which are supplied to the signal input terminals 72 and 73, respectively, which are formed by the timing signal forming section 26 based on the storage command signals CCO and CCE.
RE is supplied as a reset signal through the adder 74, and the vertical clock signal CLV is supplied to the H-address counter 71 as a reset signal.

As a result, the V-address counter 70
The vertical direction clock signal CL is set in each of the odd field period and the even field period while the count value is reset each time the read command signals CRO and CRE arrive.
V is counted and count data DAV is sent out. Also, H-
The address counter 71 has a vertical clock signal CLV.
, The horizontal direction clock signal CLH is counted and count data DAH is transmitted. Therefore, the content of the count data DAV obtained from the V-address counter 70 is the R-IPD.
10R, G-IPD. 10G and B-IPD. The contents of the count data DAH that changes in synchronization with the charge transfer by the vertical charge transfer unit 16 in each of 10B and that is obtained from the H-address counter 71 are the R-IP of the image pickup unit 11.
D. 10R, G-IPD. 10G and B-IPD. 10
It is supposed to change in synchronization with the charge transfer by the horizontal charge transfer section 18 in each of B.

Therefore, the content of the count data DAV obtained from the V-address counter 70 is the R-IPD. 10
R, G-IPD. 10G and B-IPD. When the image pickup signals IR, IG, and IB are obtained from 10B, respectively, R-I
PD. 10R, G-IPD. 10G and B-IPD. 1
Image signal I obtained at each time of 0B
It represents a vertical address AV that identifies a pixel that has provided a charge for forming R, IG, or IB, that is, a pixel horizontal column to which the photoelectric conversion element unit 15 belongs, and is obtained from the H-address counter 71. The content of the count data DAH is R-IPD. 10R, G-IPD. 1
0G and B-IPD. When the image pickup signals IR, IG, and IB are respectively obtained from 10B, R-IPD. 10R, G-
IPD. 10G and B-IPD. In each of the pixels 10B, the pixel that has provided the charge determined to form the image pickup signal IR, IG, or IB obtained at that time, that is, the position of the photoelectric conversion element unit 15 in the pixel horizontal column to which it belongs is specified. Horizontal address AH.

Therefore, during the period TDDE and the period TDDO, the level comparison data D from the level comparing section 52R is obtained.
When DR represents a high level and a defective portion included in the digital image pickup signal DIR 'is detected, the vertical address AV represented by the count data DAV obtained from the V-address counter 70 at that time is represented.
Is the R-IPD. 10R represents a pixel horizontal column to which the defective pixel belongs, and the horizontal address AH represented by the count data DAH obtained from the H-address counter 71 at that time.
Is the R-IPD. It represents the position of the defective pixel in 10R in the pixel horizontal column to which it belongs. Therefore, in such a case, the count data DAV and the count data DAH are not included in the R-IPD. The defective address data for 10R is constructed.

Similarly, during the period TDDE and the period TDDO, the level comparison data D from the level comparison section 52G is obtained.
When DG is represented as a high level and a defective portion included in the digital image pickup signal DIG 'is detected, the vertical address AV represented by the count data DAV obtained from the V-address counter 70 at that time is represented.
Of the G-IPD. It represents the horizontal row of pixels to which the defective pixel in 10G belongs, and the horizontal address AH represented by the count data DAH obtained from the H-address counter 71 at that time.
Of the G-IPD. It shows the position of the defective pixel in 10G in the horizontal pixel column to which it belongs. Therefore, in such a case, the count data DAV and the count data DAH are not included in the G-IPD. The defective address data for 10G is constructed.

Further, during the period TDDE and the period TDDO, the level comparison data D from the level comparison unit 52B is obtained.
When DB is assumed to represent a high level and a defective portion included in the digital image pickup signal DIB 'is detected, the vertical address AV represented by the count data DAV obtained from the V-address counter 70 at that time is represented.
Of the B-IPD. 10B represents a pixel horizontal column to which the defective pixel belongs, and the horizontal address AH represented by the count data DAH obtained from the H-address counter 71 at that time.
Of the B-IPD. It represents the position of the defective pixel in 10B in the horizontal pixel row to which it belongs. Therefore, in such a case, the count data DAV and the count data DAH are not included in the B-IPD. It constitutes defective address data for 10B. And
Count data DA obtained from the V-address counter 70
The count data DAH obtained from the V and H-address counter 71 is supplied to the data synthesizing unit 76.

The level comparison data D from the level comparison section 52R is supplied through the signal input terminals 54R, 54G and 54B.
DR, level comparison data DD from the level comparison unit 52G
In the identification data forming unit 77 to which the G and level comparison data DDB from the level comparing unit 52B is supplied,
Identification data DID corresponding to each level of the level comparison data DDR, DDG, and DDB is formed. This identification data DID is the level comparison data DDR.
Is set to a high level, that is, when a defective portion included in the digital image pickup signal DIR 'is detected, the digital image pickup signal DIR' is represented, and the level comparison data DDG takes a high level. When the defective portion included in the digital image pickup signal DIG ′ is detected, it represents the digital image pickup signal DIG ′, and when the level comparison data DDB has a high level, that is, , Digital imaging signal D
When a defective portion included in IB 'is detected, it represents a digital image pickup signal DIB'. And
Identification data DID obtained from the identification data forming unit 77
Are supplied to the data synthesizing unit 76.

From the data synthesizer 76, the count data DAV obtained from the V-address counter 70, the count data DAH obtained from the H-address counter 71, and
Synthesis data DZ obtained by synthesizing the identification data DID obtained from the identification data forming unit 77 is obtained, and the synthesis data DZ is the gate units 80A, 80B, 80C and 8
It is supplied to 0D. Further, the addition unit 6 is connected to the signal input terminal 86.
8 is supplied with the control signal CQ, and the signal input terminal 87 is supplied with the control signal CP from the adder 67.
Further, the comparison output signal CLA from the level data comparison unit 56A is supplied to the signal input terminal 88, and further the output signal CLB ′ from the AND circuit 62A and the output signal from the AND circuit 62B are supplied to the signal input terminals 89, 90 and 91. CL
C'and the output signal CLD 'from the AND circuit 62C are respectively supplied.

Under such circumstances, the period TDDE and the period TD
In DO, the level data comparison units 56A, 56B, 5
When the level comparison operation state is taken in each of 6C and 56D and the comparison output signal CLA obtained from the level data comparison unit 56A is set to the high level, the comparison output signal CLA having the high level is input to the signal input. Through the terminal 88, the control end of the gate unit 80A and the gate unit 8
2A, is supplied to the control end of the gate portion 82B as a control signal CP through the signal input terminal 87, and is further supplied as a control signal CQ to the signal input terminal 8
It is supplied to the control end of the gate portion 82C through 6, and each of the gate portions 80A, 82A, 82B and 82C is turned on. Thereby, the combined data DZ obtained from the data combining unit 76 at that time is passed through the gate unit 80A,
Data memory unit 47 as updated defect data DZA
The defect data DZA stored in the data memory unit 47A until then is stored in the data memory unit 47B as updated defect data DZB through the gate unit 82A and the addition unit 81B. The defect data DZB previously stored in the data memory unit 47B is stored in the data memory unit 47C as updated defect data DZC through the gate unit 82B and the addition unit 81C, and further stored in the data memory unit 47C until then. The defect data DZC that has been stored is stored in the data memory unit 47D as updated defect data DZD through the gate unit 82C and the addition unit 81D.

Level data comparison units 56A, 56B, 56
When the level comparison operation state is set in each of C and 56D and the output signal CLB ′ obtained from the AND circuit 62A is set to the high level, that is, the comparison output signal which takes the low level from the level data comparison section 56A. When the CLA is obtained and the comparison output signal CLB having the high level is obtained from the level data comparison unit 56B, the output signal CLB ′ having the high level is output from the signal input terminal 89.
Through the signal input terminal 87 as a control signal CP to the control end of the gate unit 80B, and the control signal CQ.
Is supplied to the control end of the gate portion 82C through the signal input terminal 86, and each of the gate portions 80B, 82B and 82C is turned on. As a result, the combined data DZ obtained from the data combining unit 76 at that time becomes the gate unit 8
0B and the addition unit 81B, the updated defect data D
The defect data DZB stored in the data memory unit 47B as ZB and stored in the data memory unit 47B up to that time are stored in the gate unit 82B and the addition unit 81C.
Via the gate unit 82C and the addition unit 81D, the defect data DZC stored in the data memory unit 47C as the updated defect data DZC via the gate unit 82C and the addition unit 81D. Is stored in the data memory unit 47D as

Level data comparison units 56A, 56B, 56
When the level comparison operation state is set in each of C and 56D and the output signal CLC ′ obtained from the AND circuit 62B is set to a high level, that is, the comparison output signal which takes a low level from the level data comparison unit 56B. When CLB is obtained and the comparison output signal CLC having a high level is obtained from the level data comparison unit 56C, the output signal CLC ′ having a high level is output from the signal input terminal 90.
Through the signal input terminal 86 as a control signal CQ to the control end of the gate unit 82C, and the gate units 80C and 82C are turned on. As a result, the combined data DZ obtained from the data combining unit 76 at that time is stored in the data memory unit 47C as updated defect data DZC through the gate unit 80C and the addition unit 81C,
At the same time, the defect data DZC previously stored in the data memory unit 47C is stored in the data memory unit 47D as updated defect data DZD through the gate unit 82C and the addition unit 81D.

Further, the level data comparison units 56A, 56
An output signal C obtained from the AND circuit 62C when the level comparison operation state is set in each of B, 56C and 56D.
When LD 'takes a high level, that is, the level data comparing section 56C obtains a low level comparison output signal CLC and the level data comparing section 56D obtains a high level comparison output signal CLD. Sometimes, the output signal CLD ′ having the high level is supplied to the control end of the gate section 80D through the signal input terminal 91. As a result, the combined data DZ obtained from the data combining unit 76 at that time becomes the gate unit 80D and the adding unit 81D.
Through, and is stored in the data memory unit 47D as updated defect data DZD.

The level data comparison units 56A, 56
As a result of the level comparison operation state in each of B, 56C and 56D, a comparison output signal CLA obtained from the level data comparison unit 56A, an output signal CLB ′ obtained from the AND circuit 62A, an output signal obtained from the AND circuit 62B. When both CLC ′ and the output signal CLD ′ obtained from the AND circuit 62C are low level, the synthesized data DZ obtained from the data synthesizing unit 76 at that time is the data memory units 47A and 47B. , 47
It is not stored in either C or 47D.

By doing so, the period TDD
E and the period TDDO, the digital imaging signal DI
A defective portion included in any of R ′, DIG ′, and DIB ′ is detected, and the level comparison data DDR from the level comparison unit 52R, the level comparison data DDG from the level comparison unit 52G, and the level comparison data from the level comparison unit 52B are detected. When any one of the level comparison data DDB is set to a high level, the R-IPD. 10R, G-IPD. 10G or B-
IPD. The synthetic data DZ including the defective address data for 10B and the identification data DID corresponding thereto is stored in the data memory unit 47A as the defective data DZA.
As the defect data DZB in the data memory unit 47B, as the defect data DZC in the data memory unit 47C,
Alternatively, the state of being stored as defective data DZD in the data memory unit 47D, or the data memory unit 47
The data is not stored in any of A, 47B, 47C and 47D. As a result, the data memory unit 4
7A, 47B, 47C, and 47D, defect data DZA to DZD including defect address data and identification data DID corresponding thereto are assigned to the R-IPD. 10R, GI
PD. 10G or B-IPD. Digital image pickup signals DIR 'and DIG' due to defective pixels in 10B
Alternatively, the higher the level of the defect portion included in DIB ′ is, the higher the priority is, and the level of the defect portion corresponding to the defect data DZA ≧ the level of the defect portion corresponding to the defect data DZB ≧ the defect corresponding to the defect data DZC The level of the part ≧ the level of the defective part corresponding to the defect data DZD is satisfied and stored.

Under these circumstances, the memory write control signal generator 46, the data memory units 47A, 47B, 47C and 47 are used.
A defective data storage unit is configured by a portion including D, the gate portions 80A, 80B, 80C and 80D, the gate portions 82A, 82B, 82C and 82D, and the like.

Next, when the period TDDE and the period TDDO elapse, the detection end signal generator 8 to which the memory write control signal CWC from the memory write control signal generator 46 is supplied.
3 to 3, the detection end signal C formed in response to the trailing edge of the memory write control signal CWC as shown by H in FIG.
E is obtained, and the detection end signal CE is output from the control unit 36.
Is supplied to. As a result, the control unit 36 has the configuration shown in FIG.
As indicated by C, the transmission of the defect detection command signal CST is stopped at a time point after the leading edge of the detection end signal CE. Then, at the leading edge of the detection end signal CE, the defect detection unit 35 detects a defect, that is, detects a defective portion in the digital image pickup signal DIR ′, DIG ′ or DIB ′, and determines the cause of the detected defective portion. R-IPD. 10R, G-IPD. 10G or B-IPD. The defect address data for specifying the defective pixel in 10B is made to correspond to the identification data DID representing the digital image pickup signal DIR ', DIG' or DIB 'in which the defective portion is detected, and the defect data DZA,
The operation of storing the data as DZB, DZC or DZD in the data memory units 47A, 47B, 47C and 47D is completed, and thereafter, for example, the process returns to the video signal output period TCO.

In the defect detecting section 35 for which the defect detecting operation has been completed, in the subsequent video signal output period TCO,
Defect data DZA, DZB, DZ stored therein from the data memory units 47A, 47B, 47C and 47D.
C and DZD are read out respectively, and through the adding section 84,
Signal supply terminal 93 (FIG. 7) as read defect data DZZ
Is supplied to. Then, the read defect data DZZ via the signal supply terminal 93 is supplied to the movable contact 95A in the identification data discriminating unit 94 and the switch 95.

In the identification data discriminating section 94, the read defect data DZZ, that is, the data memory sections 47A, 47.
When any one of the defect data DZA, DZB, DZC and DZD read out from any of B, 47C and 47D is supplied, the identification data DID included therein.
Are digital imaging signals DIR ', DIG' and DI
It is determined which one of B ′ corresponds to, and a determination output signal DD representing the determination result is formed. This discrimination output signal DD is supplied to the control end of the switch 95, whereby the switch 95 discriminates the discrimination output signal DD from the identification data D included in the read defect data DZZ.
When the ID represents that it corresponds to the digital image pickup signal DIR ', the movable contact 95A is the selection contact 95.
It is connected to R and the discrimination output signal DD is the read defect data D.
When the identification data DID included in ZZ corresponds to the digital image pickup signal DIG ', the movable contact 95A is connected to the selection contact 95G, and the determination output signal DD is included in the read defect data DZZ. When the identification data DID indicates that it corresponds to the digital image pickup signal DIB ′, the movable contact 95A is connected to the selection contact 95B.

The identification data DID is the digital image pickup signal D.
When the switch 95 has its movable contact 95A connected to the selection contact 95R, the read defect data DZZ is supplied to the data separation unit 96R through the switch 95. When the identification data DID corresponds to the digital image pickup signal DIG ′ and the movable contact 95A of the switch 95 is connected to the selection contact 95G, the read defect data DZZ is transmitted through the switch 95. It is supplied to the data separation unit 96G. Further, the identification data DID corresponds to the digital image pickup signal DIB ′,
When the switch 95 has its movable contact 95A connected to the selection contact 95B, the read defect data DZ
Z is supplied to the data separation unit 96B through the switch 95.

In the data separation unit 96R, the R-IPD. Count data DAV and DAH forming defective address data for 10R are separated and read out as read count data DAVR and DAHR. Then, the data separation unit 96R
Read count data DAVR and D obtained separately from
The AHR is supplied to and latched in the vertical address comparison unit (V-address comparison unit) 97R and the horizontal address comparison unit (H-address comparison unit) 98R. Similarly, in the data separation unit 96G, the read defect data D
G-IPD. Count data DAV and DAH forming defective address data for 10G
Is read out as separated read count data DAVG and DAHG, and read count data DAVG and DAHG obtained by being separated from the data separation unit 96G are supplied to the V-address comparison unit 97G and H-address comparison unit 98G, respectively. Latched. Furthermore, the data separation unit 96
In case of B, B− included in read defect data DZZ
IPD. The count data DAV and DAH forming the defective address data for 10B are read count data DA.
Read count data D separated and extracted as VB and DAHB and separated from the data separation unit 96B
AVB and DAHB are supplied to and latched by the V-address comparison unit 97B and H-address comparison unit 98B, respectively.

V-address comparison units 97R, 97G and 9
The count data DAV from the V-address counter 70 is supplied to each of 7B through the signal supply terminal 100. Then, the vertical direction address data AV represented by the count data DAV from the V-address counter 70 is V-
Read count data D latched in the address comparison unit 97R
When the vertical address AV represented by AVR matches, a comparison output signal CVR having a high level is obtained from the V-address comparison unit 97R and supplied to one input terminal of the AND circuit 99R. In addition, the V-address counter 7
Vertical address data AV represented by the count data DAV from 0 is vertical address A represented by the read count data DAVG latched in the V-address comparison unit 97G.
When it matches with V, a comparison output signal CVG having a high level is obtained from the V-address comparison unit 97G and is supplied to one input terminal of the AND circuit 99G. Further, the vertical address data AV represented by the count data DAV from the V-address counter 70 is the V-address comparison unit 97.
When the read count data DAVB latched in B coincides with the vertical address AV represented, the V-address comparison unit 97B obtains a high level comparison output signal CVB, which is applied to one input terminal of the AND circuit 99B. Supplied.

On the other hand, H-address comparison units 98R and 98G
, 98B, the count data DAH from the H-address counter 71 is supplied through the signal supply terminal 101. Then, horizontal address data AH represented by the count data DAH from the H-address counter 71.
Is equal to the horizontal address AH represented by the read count data DAHR latched in the H-address comparison unit 98R, the H-address comparison unit 98R obtains the comparison output signal CHR having a high level, and the AND circuit 99R. Is supplied to the other input terminal of the. When the horizontal address data AH represented by the count data DAH from the H-address counter 71 matches the horizontal address AH represented by the read count data DAHG latched by the H-address comparison unit 98G, the H-address comparison unit A comparison output signal CHG having a high level is obtained from 98G and is supplied to the other input terminal of the AND circuit 99G. further,
When the horizontal address data AH represented by the count data DAH from the H-address counter 71 matches the horizontal address AH represented by the read count data DAHB latched by the H-address comparison unit 98B, the H-address comparison unit 98B outputs , Comparison output signal CH that takes a high level
B is obtained and supplied to the other input terminal of the AND circuit 99B.

The comparison output signal C is output from the AND circuit 99R.
When both the VR and the comparison output signal CHR have a high level, the defect correction instruction signal CDR is obtained and supplied to the defect correction section 32R. Similarly, the AND circuit 99G outputs the comparison output signal CVG and the comparison output signal CH.
When both G and G have a high level, a defect correction instruction signal CDG is obtained and supplied to the defect correction section 32G. Further, when both the comparison output signal CVB and the comparison output signal CHB have a high level, the AND circuit 99B obtains the defect correction instruction signal CDB, which is supplied to the defect correction section 32B.

Under these circumstances, the control signal forming section is composed of various circuit block sections from the identification data discriminating section 94 to the AND circuits 99R, 99G and 99B.

In the above example, the digital image pickup signals DIR ', DIG' or DI generated by the defect detecting section 35 are used.
B ', the defective portion of the image pickup unit 11 which is the cause of the detected defective portion is detected. 10R, G
-IPD. 10G or B-IPD. The defective address data for specifying the defective pixel in 10B is converted into digital image pickup signals DIR 'and DIG' in which the defective portion is detected.
Alternatively, the data memory units 47A, 47B, 47C and 47D are associated with identification data DID representing DIB '.
The operation of storing the image in the R-IPD. 10R, G-IPD. 1
0G and B-IPD. Each of 10B is performed under the condition that outside light is not substantially incident, and the R-IP
D. 10R, G-IPD. 10G or B-IPD.
In 10B, detection is performed on a defective pixel that causes a malfunction in which a relatively large amount of charge is stored and transmitted even without receiving external light, and correction of a defective portion of an image pickup signal caused by the defective pixel is performed. However, the present invention is not limited to such an example. For example, the defect detecting section 35 detects a defective portion in the digital image pickup signal DIR ′, DIG ′ or DIB ′, and causes the detected defective portion. R-IPD. 1
0R, G-IPD. 10G or B-IPD. 10B
Defect address data for specifying the defective pixel in the digital image pickup signal DIR ', in which the defective portion is detected,
Identification data DID representing DIG 'or DIB'
The operation of storing in the data memory units 47A, 47B, 47C, and 47D in association with the R-IPD.
10R, G-IPD. 10G and B-IPD. R-
IPD. 10R, G-IPD. 10G or B-IP
D. In 10B, it may be possible to detect a defective pixel that causes a malfunction in which an appropriate amount of electric charge is not accumulated even when receiving external light and to correct a defective portion of an image pickup signal caused by the defective pixel.

[0103]

As is apparent from the above description, in the image pickup signal defect detection and correction apparatus and the image pickup signal defect detection and correction method according to the present invention, images projected on a plurality of image pickup plane forming portions are respectively projected. A defective portion is detected for each of a plurality of image pickup signals formed based on the defective portion, and when the defective portion is detected, identification data for identifying the image pickup signal for which the defective portion is detected is formed and the defective portion is formed. The defective address data in the imaging surface forming portion relating to the formation of the detected imaging signal is stored in the data memory means in association with the identification data. At that time, the defective address data is associated with the identification data of the defective address data. lack of storage in the data memory means, corresponding to the defective address data
It is assumed that the priority order according to the level of the defective portion , for example, the higher the level of the defective portion corresponding to the defective address data, the higher the priority of the other portions. As a result, the memory capacity of the data memory means is wasted in the data memory means in the order of the defective address data and the identification data corresponding thereto, for example, in the order of the level of the defective portion corresponding to the defective address data. The data memory means is efficiently used.

Then, the defect address data read from the data memory means is discriminated as to which of the plurality of image pickup signals, based on the corresponding identification data, and is used for the defect correction of the corresponding image pickup signals. Therefore, with respect to each of the plurality of image pickup signals, it is possible to avoid a situation in which a relatively large-scale defective portion corresponding to defective address data that is not written in the data memory means is left uncorrected. However, it will be effectively achieved.

[Brief description of drawings]

FIG. 1 shows a method for detecting and correcting an image signal defect according to the present invention .
1 is a block configuration diagram showing an example of an image pickup signal defect detection and correction device according to the present invention in which an example is implemented, together with an image pickup section, an optical system, and the like to which the image pickup signal defect detection and correction device is applied.

FIG. 2 is a schematic configuration diagram provided for explaining an imaging surface forming unit in an imaging unit to which the example shown in FIG. 1 is applied.

FIG. 3 is a time chart used to explain the operation of the imaging unit to which the example of FIG. 1 is applied.

FIG. 4 is a time chart used to explain the operation of the imaging unit to which the example of FIG. 1 is applied.

5 is a block configuration diagram showing a part of a specific configuration example of a defect detection unit in the example shown in FIG. 1. FIG.

6 is a block configuration diagram showing a part of a specific configuration example of a defect detection unit in the example shown in FIG. 1. FIG.

FIG. 7 is a block configuration diagram showing a part of a specific configuration example of a defect detection unit in the example shown in FIG.

FIG. 8 is a time chart used for explaining the operation of a specific configuration example of the defect detection unit shown in FIGS. 5, 6 and 7.

[Explanation of symbols]

10R Red light image pickup surface forming unit (R-IPD) 10G Green light image pickup surface forming unit (G-IPD) 10B Blue light image pickup surface forming unit (B-IPD) 11 Image pickup unit 12 Optical system 13 Semiconductor Substrate 15 Photoelectric conversion element section 16 Vertical charge transfer section 17 Charge read gate section 18 Horizontal charge transfer section 19 Charge output section 20 Output terminal 25 Drive signal forming section 26 Timing signal forming section 27 Sync signal generating sections 30R, 30G, 30B Sampling / Hold section 31R, 31G, 31B A / D conversion section 32R, 32G, 32B Defect correction section 33 Signal processing section 35 Defect detection section 36 Control unit 45 Storage command signal generation section 46 Memory write control signal generation section 47A, 47B, 47C , 47D Data memory sections 52R, 52G, 52B Level comparing section 53 Reference level generating sections 56A, 56B, 56C 56D level data comparing unit 60R. 60G. 60B Level data forming section 61A, 61B, 61C Inverter 62A, 62B, 62C, 99R, 99G, 99B
AND circuits 63A, 63B, 63C, 63D, 66A, 66B, 6
6C, 80A, 80B, 80C, 80D, 82A, 82
B, 82C Gate section 65A, 65B, 65C, 65D Level data memory section 70 V-address counter 71 H-address counter 77 Identification data forming section 94 Identification data determining section 95 Switch 97R, 97G, 97B V-address comparing section 98R, 98G, 98B H-address comparison unit

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/335 H04N 9/07-9/09

Claims (14)

(57) [Claims] 1. A plurality of image pickup surface forming portions each having a plurality of pixels arranged in an array, and a plurality of image pickup surface forming portions formed based on images projected on the plurality of image pickup surface forming portions, respectively. And a signal defect detection unit that detects a defective portion based on an output signal from a defective pixel in the image pickup surface formation unit included in the image pickup signal from the image pickup unit that obtains the image pickup signal of When a portion is detected, an identification data forming unit that obtains identification data that specifies the image pickup signal in which the defective portion is detected, and the level of the defective portion detected by the signal defect detection unit
When the defect portion is detected by the defect level detection unit for detecting the defect level and the signal defect detection unit, each pixel in the imaging surface formation unit related to the formation of the imaging signal in which the defect portion is detected is specified. of the address data, a defective address data to correspond to a defective pixel which forms the cause of the defect, in the foot in correspondence with the identification data from the identification data forming unit, the upper
Storing the defective address data in the data memory means,
The defect of the defective portion corresponding to the defective address data
Priority according to the level detected by the level detector
A defect data storage section, and a defect correction section for a defect correction section for an image pickup signal specified by the identification data based on the defect address data and the identification data read from the data memory means in the defect data storage section. An image pickup signal defect detection and correction device comprising: a control signal forming unit that sends out a control signal. 2. A defect data storage unit, the defect address data
Of the defective address data.
The defect level detector of the corresponding defective portion of the data
The higher the level detected, the corresponding identification data
Stored in preference to others, regardless of data
Imaging signal defect detection and correction apparatus according to claim 1, wherein the forming shall become Rukoto. 3. The defective data storage section is provided with defective address data.
Identification data and stored in the data memory means at Moto that associates a preset number of defective address data is rated for
Performed as delivered and have the preset number of defects
The address data was detected by the defect level detector.
The preset number of levels above which the level is greater than the others
3. The image signal defect detection and correction apparatus according to claim 2 , wherein the defect portions correspond to the defect portions, respectively . 4. The defect level detecting section comprises a signal defect detecting section.
Level data indicating the level of the defective part detected
And a level data forming unit for forming
Store the level data formed by the section in the memory means
And a level data storage section for
Level data and levels newly created by the data forming unit
The level stored in the memory means in the data storage unit
The level newly created by comparison with the
The feature is to detect the level of the defective part represented by the data.
The image signal defect detection and correction device according to claim 2 or 3, which is a characteristic . 5. A level data recording in a defect level detecting section .
The storage unit presets the storage of the level data in the memory means.
The row is assumed to store a fixed number of level data.
If the preset number of level data is
The level indicated by each of the specified number of level data is other
Level data is higher than the level
The imaging signal defect detection and correction device according to claim 4, wherein 6. A signal defect detection section is provided in a plurality of image pickup sections.
It is formed based on the images projected on the imaging surface forming unit.
Detection of defective parts included in multiple image signals.
Even if the outside light does not substantially enter the imaging surface forming part
6. The method according to claim 1, wherein
An image pickup signal defect detection and correction device according to any one of 1 . 7. A signal defect detection unit for a red primary color signal, green
Included in the plurality of imaging signal formed on the basis of the image it is respectively projected on the three imaging surface forming part which is for the primary color signal and a blue primary color signal, s husband three imaging surface forming part above
The defective part based on the output signal from the defective pixel in
Imaging signals as claimed in any one of claims 1 to 6, characterized in that it is intended to defect detection and correction system. 8. A plurality of pixels each arranged in an array.
A plurality of an imaging plane formed portion which is as the imaging surface of the plurality of
A plurality of images formed on the basis of the images respectively projected on the forming unit
Included in the image pickup signal from the image pickup unit from which the image pickup signal of
The output signal from the defective pixel in the imaging surface formation section is
A first step of detecting a defective portion based on the signal, and the defective portion being detected in the first step .
The identification of the imaging signal for which the defective portion has been detected.
The defective portion was detected in the second step of obtaining different data and the first step.
At this time, regarding the formation of the image pickup signal in which the defective portion is detected,
Address for identifying each pixel in the imaging surface forming unit
Defective pixel that causes the above-mentioned defective portion
The defective address data that is supposed to correspond to
Based on the identification data obtained in step 2
The defective address data to the data memory means.
Check the defective part corresponding to the above defective address data.
A third step performed according to the priority order according to the bell, and the defect address read from the data memory means.
Based on the identification data and the identification data.
Defect correction unit for the image signal specified by
And a fourth step of transmitting a work control signal, and a method of detecting and correcting a defect in an imaging signal.
Law . 9. A defective address data in the third step.
Data memory means in correspondence with the identification data of the data
The priority of storage in the defective address data
The higher the level of the corresponding defective part of the
Regardless of the corresponding identification data, it takes precedence over others
Contracts characterized by
An image pickup signal defect detection and correction method according to claim 8. 10. A preset number of defective address data stored in the data memory means in correspondence with the identification data of the defective address data in the third step.
To store the number of
Compare the defective address data with other defect levels.
Responding to each of the above preset number of large defects
Imaging signal defect detection and correction method according to claim 9, wherein the forming shall be. 11. The third step corresponds to the first step.
Level data indicating the level of the defective part detected by
And the fifth step of forming the
Storing the formed level data in the memory means.
6 steps, and in the fifth step above
The level data created in
And comparison with the level data stored in the memory means
Shows the newly created level data
10. The level of the defective portion is detected.
Or 10 imaging signal defect detection and correction method according. 12. The level data in the sixth step
The storage in the memory means stores the preset number of level data.
Data is stored, and the above preset number
Of the level data of the preset number of level data
The level represented by each of the
The image signal defect detection and correction method according to claim 11 , wherein the level is higher than the level . 13. A plurality of image pickup units in the first step
Are formed on the basis of the images projected on the respective image pickup surface forming units.
The detection of a defective part included in a plurality of image pickup signals
When the outside light is not substantially incident on the multiple imaging surface formation parts
The process according to claim 8 to claim 12, characterized in that
An image pickup signal defect detection and correction method according to any one of claims. 14. A red primary color signal in the first step.
, For the green primary color signal and for the blue primary color signal
It is formed based on the images projected on the imaging surface forming unit.
The three image pickup surface forming units included in the plurality of image pickup signals
Defects based on output signals from defective pixels in each of
The minute is detected, and the minute is detected.
An image pickup signal defect detection and correction method according to any one of 1 .