JP3408948B2 - High voltage generation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use as a voltage generating circuit arranged in an electrically programmable erasable non-volatile semiconductor memory device such as an EEPROM or a flash EEPROM, or as a substrate bias generating device. The present invention relates to a voltage generation circuit.

[0002]

2. Description of the Related Art EEPROM and flash EEPROM
A non-volatile semiconductor memory device that is electrically writable and erasable, for example, a negative voltage is applied to the gate electrode to increase reliability when electrons are extracted (erased) from the floating gate of the memory cell. Alternatively, a positive voltage is applied to the drain diffusion layer to extract electrons from the floating gate to the diffusion layer.

The potential difference between the control gate / floating gate / diffusion layer required when erasing a memory cell is
Although it depends on the amount of overlap between the floating gate and the diffusion layer and the oxide film thickness, 12 to 18 V is required. Normally, erasing of a memory cell is realized by applying a positive voltage of about 5V to the diffusion layer and a negative voltage of about -10 to -15V to the control gate. The reason why the voltage applied to the diffusion layer is low is that the breakdown voltage between the diffusion layer and the well is low, and the decrease in reliability due to the band-to-band tunneling phenomenon is prevented.

It is necessary when writing and erasing a memory cell,
A charge pump circuit (boost circuit) is used to generate a high voltage higher than the power supply voltage. In particular, in a charge pump circuit that generates a negative voltage, as shown in FIG. 1, a plurality of P-channel MOS (hereinafter referred to as PMOS)
Transistor 21 is connected in series and each PMO
The gate of the S transistor 21 is connected to the source of the PMOS transistor 21, and the low voltage Vss (GND) is supplied to the source of the PMOS transistor 21 at one end.
One end of the capacitance 22 is connected to the source of each PMOS transistor 21, and complementary clock signals φ1 and φ2 are alternately supplied to the adjacent capacitances at the other end of each capacitance 22. The negative high voltage −Vpp is obtained from the final drain end of the 21st column.

In the charge pump circuit using such a PMOS transistor, when the voltage is transferred to the next stage,
Boosting loss corresponding to the threshold voltage occurs. In order to reduce this loss, it is necessary to newly prepare a PMOS transistor having a low threshold voltage. However, in the MOS transistor of the half-micron generation or later, the well concentration is increasing, and the source voltage rises like a charge pump circuit, and in a circuit in which the substrate bias is applied relatively, The step-up loss due to the rise of the threshold value due to the bias effect becomes larger as the number of stages increases, and it becomes impossible to raise the output voltage to the voltage required for writing or erasing the memory cell. At the same time, the junction breakdown voltage between the source / drain diffusion layer and the well is also lowered, so that the breakdown voltage does not reach the voltage required for writing or erasing the memory cell. These two problems are major problems because the electric field required for erasing does not change even when the device becomes smaller, and the required voltage cannot be lowered so much.

Several methods have been proposed as methods for solving the boosting loss due to the substrate bias effect.
As one method, the voltage applied to the gate is
There is one that applies a voltage higher than c to prevent the boosting loss (Japanese Patent Laid-Open No. 5-28785). With this method, boost loss due to the substrate bias effect can be prevented, but in order to generate the voltage to be applied to the gate, it is necessary to have a pump circuit different from the original charge pump circuit, which increases the chip area. Bring

Another method has been proposed in which the voltage applied to the gate is increased to boost the voltage without receiving the substrate bias effect, as in the prior art (Japanese Patent Laid-Open No. 3-86065). This method is configured to prevent the substrate bias effect by connecting the source and the gate portion of the boosting MOS transistor through a capacitor and adding the potential of the latter stage to the reference clock potential by adding it. However, even in this method, it is necessary to provide a capacitor for boosting the gate bias in each stage, and it is necessary to provide a transistor in each stage for disconnecting the potential between the clock signal and the gate portion. Increasing is inevitable.

As another method for solving this step-up loss, as an element used in the charge pump circuit, a MOS is used.
A device using a PN diode instead of a transistor has been proposed. However, this charge pump circuit has a parasitic npn bipolar transistor in the vertical direction, and when this is used for boosting a positive voltage, the PN diode does not receive the substrate bias effect and thus can be boosted without any problem, but it is negative. When it is used for boosting the voltage, it is used in such a voltage relationship that the parasitic bipolar transistor is turned on, and there is a problem that the rectifying action is impaired. Therefore, it is not suitable for boosting the negative voltage. There is also a method of canceling the substrate bias effect by applying the same bias as the source voltage to the well, but in boosting a negative voltage, P
As with the N diode type charge pump circuit, parasitic np
Since the n-bipolar transistor operates and the rectifying operation cannot be performed, this is also not suitable for boosting a negative voltage.

By the way, in the conventional semiconductor memory device, one charge pump circuit is generally designed and mounted for one required voltage condition. However, in a flash memory, a positive high voltage during writing and a negative high voltage during erasing are required as a voltage applied to the control gate during writing and erasing of the flash memory. A charge pump circuit is provided. As shown in FIGS. 1 and 3, the charge pump circuit requires a capacitive element for pumping up at each stage, and the capacitive element requires a large area. Greatly affect the increase of.

[0010]

SUMMARY OF THE INVENTION In order to solve the above problems, a first object of the present invention is to perform boosting without receiving boosting loss due to the substrate bias effect, and to change the circuit operation method. It is an object of the present invention to provide a high voltage generating circuit that can obtain a necessary negative voltage without doing so.

A second object of the present invention is to prevent an increase in the chip area by realizing positive and negative two types of high voltage used for writing and erasing the flash memory with a high voltage by one type of charge pump circuit. .

[0012]

According to the present invention, there is provided a booster circuit having a charge pump circuit for generating a positive high voltage, and an oscillator circuit having a ring oscillator using a voltage output from the booster circuit as a power source. A capacitive element that receives an oscillation signal of the oscillation circuit at one end of the electrode and a rectifying element that is connected to the other end of the electrode of the capacitive element and that generates a negative voltage, and outputs the other end of the capacitive element It is a high voltage generation circuit that outputs a negative high voltage as an end.

By using a configuration for converting a positive high voltage into a negative high voltage, a boosting loss and a breakdown voltage due to a substrate bias effect in a method of directly generating a negative high voltage using a charge pump circuit in which a PMOS transistor is arranged. You can avoid the problem of negative high voltage.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION As a booster circuit for a high voltage generation circuit, a P-type P-type formed in an N-type well in a P-type silicon substrate.
An N-channel MOS transistor (hereinafter referred to as NMOS) formed in the well is provided as a boosting element so that the source electrode of the NMOS transistor and the P-well formed in the transistor have the same voltage. A connected charge pump circuit, or a P-type well formed in an N-type well in a P-type silicon substrate,
It is preferable to use a charge pump circuit provided with a PN diode formed by a PN junction with an N type diffusion layer formed in the P type well as a boosting element. As a result, a high voltage can be received between wells having a higher tolerance, and a negative high voltage can be generated without receiving the substrate bias effect.

As a rectifying element of the high voltage generating circuit, a P of an N type well and a P type well formed in the N type well are formed.
PN diode formed by N junction or P
It is preferable to use a PN diode formed by a PN junction between the type well and the N type well formed in the P type well. As a result, the generated high voltage is received between the wells / wells having higher tolerance, so that a higher voltage can be handled. By providing a switching circuit that selects the output of the high negative voltage of the high voltage generating circuit and the output of the high positive voltage of the booster circuit, there are two types of high voltage generating circuits for obtaining the high positive and negative voltages. Since it is not necessary and only one type is required, the chip area can be reduced.

[0016]

1 is a block diagram of a negative high voltage generating circuit according to an embodiment of the present invention. A positive voltage charge pump circuit 1 connected to a control circuit (not shown), a ring oscillator 2 that uses the voltage output from the positive voltage charge pump circuit 1 as a power source, and a capacitive element that receives an oscillation signal of the ring oscillator 2 at one end of an electrode. 3 and a rectifying element 4 which is connected to the other end of the electrode of the capacitive element 3 and converts into a negative voltage are sequentially connected.

When the memory cell erasing signal is sent to the control circuit, the signal from the control circuit activates the clock circuit in the positive voltage charge pump circuit 1, and the oscillation signal is used as the clock frequency for the positive voltage charge pump circuit 1. Applied to the
In the positive voltage charge pump circuit 1, the power source is pumped up step by step according to the clock frequency and rises to a predetermined voltage. By applying this voltage as the power source of the ring oscillator 2, the ring oscillator 2 starts oscillating. At this time, the output power supply of the ring oscillator 2 oscillates between the positive reference voltage Vss and the positive high voltage Vpp (more accurately, lower than the threshold voltage of the inverter in the ring oscillator 2). This oscillating voltage is connected to one end of the capacitive element 3, a voltage corresponding to the oscillating voltage is output from the other end of the capacitive element 3, and a negative high voltage is output by adding the rectifying element 4 to this terminal side. . At this time, the negative high voltage has an oscillating waveform, and the effective voltage application time is reduced. However, in the flash memory, erasing is usually performed in a long time of 100 milliseconds to several seconds. In practice, it does not matter.

Next, each of the circuits 1 to 4 in the embodiment will be described with reference to specific examples. FIG. 3 shows an example of the positive voltage charge pump circuit 1. A plurality of NMOS transistors 41 formed in a P-type well formed in an N-type well in a P-type silicon substrate are connected in series, and the gate and source of each NMOS transistor 41 are respectively NMOS transistors 41. Are connected to the P-type well. One end of the capacitance 42 is connected to the source of each NMOS transistor 41, and each capacitance 4
The other end of 2 has a clock signal φ1, which is complementarily input,
φ2 is configured to be alternately supplied to the adjacent capacitors. The NMOS transistor 41 at one end that is the input end
Is supplied with the power supply voltage Vcc from the final drain end of the row of NMOS transistors 41 and has a positive high voltage Vp.
It is configured to obtain p.

An NMOS transistor 41 at one end on the input side
The power supply voltage Vcc is supplied to the source of the source and the source and the gate have the same voltage, so that the channel becomes conductive and the source and the drain have the same voltage. When the clock signal φ1 switches from low to high, the NMO of the input stage
In the S transistor 41, the drain voltage is pushed up by the capacitor 42, the PN junction at the drain is in a reverse bias state, and the NMOS transistor 41 is turned off.
The drain voltage pushed up by the NMOS transistor 41 at the input stage becomes the source voltage of the NMOS transistor 41 at the next stage. Then, the complementary input clock signals φ1 and φ2 are added to the pump-up capacitance 42, so that the voltage on the source side of each NMOS transistor 41 rises according to the clock signals φ1 and φ2. The voltage rises each time the stages are stacked, and a positive high voltage Vpp is obtained from the final drain end of the row of NMOS transistors 41.

Since the source and gate of each NMOS transistor 41 are set to have the same voltage as the P-type well of the NMOS transistor 41, the substrate bias effect does not occur. The drain voltage is higher than the source voltage
The voltage corresponding to the threshold voltage of the NMOS transistor 41 drops, but since the substrate bias effect which is the cause of the threshold voltage rise is prevented, the source voltage rises. It is constant in the subsequent stages. Since the threshold value of the MOS transistor is a low value of around 0.5 V, the boost loss is very small. Further, this threshold voltage can be controlled relatively easily in the channel doping process at the time of manufacturing, and it is possible to bring this value close to 0V. However, when the voltage is set to 0 V or less (complete depletion), the conductive state is always established, and the rectifying function cannot be maintained.

As another charge pump circuit for generating a positive voltage, there is a charge pump circuit using a diode using a PN junction. In the PN junction, a transmission loss of about 0.68V occurs between the junctions, but since it is structurally unaffected by the substrate bias effect, it is possible to boost the voltage to a higher voltage. Further, in manufacturing the PN junction, since the N-type diffusion layer for the P-type well can be used as it is, it is not necessary to design a dedicated manufacturing process. Also,
Although a pump-up capacitance is indispensable in the charge pump circuit, the oxide film of the MOS device as shown in FIG. 3 may be used, or the structure between wiring materials such as polysilicon or metal is used. Capacity may be used. If the speed of data erasing does not matter, the junction capacitance can be used.

FIG. 4 shows a portion including a ring oscillator, a capacitive element and a rectifying element in the embodiment, which is a negative voltage for converting a positive high voltage Vpp produced by the charge pump circuit into a negative high voltage −Vpp. It is a circuit diagram of a generator. The ring oscillator 35 is for oscillating the high voltage Vpp generated by the charge pump circuit with the reference voltage Vss. In the ring oscillator 35, P
MOS transistor 35a and NMOS transistor 35
An oscillator circuit is configured by connecting an odd number of stages in which one inverter is configured by connecting b in series.
One end 31a of the capacitor 31 is connected to the output side terminal of the ring oscillator 35, and the diode 33 is connected to the ground terminal Vss at the other end 31b of the capacitor 31.

Since the ring oscillator 35 only produces an oscillation voltage, it is not necessary to lengthen the gate width of each MOS transistor used, and it is sufficient if the number of stages can achieve stable oscillation. In the embodiment, 5 stages are used. I was able to achieve that goal. Of course, even if there are three stages, there is no problem if the oscillation is stable, and it is advantageous in terms of circuit area. If a suitable resistance value is obtained, a resistance element such as a well resistance or a polysilicon resistance may be used instead of the PMOS transistor 35a.

Explaining the circuit operation of FIG. 4, the ring oscillator 35 starts to oscillate by itself when the voltage Vpp from the charge pump circuit is applied. Ring oscillator 3
The oscillating voltage oscillated from 5 is sent to one end 31 a of the capacitor 31. Then, a voltage corresponding to the oscillation voltage is generated from the other end 31b of the capacitor 31. Capacitance 31 and diode 3
3, the voltage at the other end 31b of the capacitor 31 becomes the reference value Vss.
When the voltage becomes higher than the voltage Vss through the diode 33, the voltage at the one end 31a of the capacitor 31 decreases from Vpp to Vss. The voltage at the other end 31b of the voltage drops to a negative voltage (about -Vpp). At this time, a reverse bias is applied to the diode 33, and V
The voltage of the other end 31b that has dropped below ss does not change. Next, the voltage on the one end 31a side of the capacitor 31 is again Vp.
When the voltage rises to p, the voltage of the capacitor 31b of the capacitor 31 rises from a negative voltage to 0V because the capacitor 31 stores the charge amount. Thereafter, by repeating this, the oscillation voltage of the reference voltage Vss and the negative voltage of about − (Vpp−threshold voltage) is obtained from the one end 31b which is the output end of the capacitor 31. FIG. 5 shows an example of a waveform diagram obtained at this time. A high voltage is applied to the diode 33. Diode 33
It is preferable to use a triple well structure as shown in FIG. 6 and use a portion of the rectifying element to which a high voltage is applied between the well 33p and the well 33n in order to use a higher voltage. With such a structure, it is possible to handle a high voltage even in a low voltage device of the half micron generation or later.

FIG. 7 shows another example of the rectifying element. Capacity 3
The PMOS transistor 34 is connected to the ground terminal at the wiring of the other end 31b of 1. The operation is the same as that of the diode 33 in FIG. As long as the breakdown voltage is maintained, the PMOS transistor 34 can be used in this way.

FIG. 8 is a block diagram of a voltage generating circuit according to another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. A positive voltage charge pump circuit 1 connected to a control circuit (not shown), a ring oscillator 2 that uses the voltage output from the positive voltage charge pump circuit 1 as a power source, and a capacitive element that receives an oscillation signal of the ring oscillator 2 at one end of an electrode. 3, a rectifying element 4 connected to the other end of the electrode of the capacitive element 3, and a switching circuit 5 for switching between the output of the positive voltage charge pump 1 and the output of the rectifying element 4 for output. There is.

When the signal for erasing the memory cell is sent to the control circuit, the signal from the control circuit activates the clock circuit in the positive voltage charge pump circuit 1 and, in response to the oscillation signal, the positive voltage charge pump circuit. Within 1, the voltage rises to a predetermined voltage. When a positive voltage is required, the switching circuit 5 directly outputs the positive high voltage generated in the positive voltage charge pump circuit 1. When a negative voltage is required, the switching circuit 5 outputs the voltage via the rectifying element 4. For the switching circuit 5, for example, an inverter circuit as shown in FIG. 9 is used.

As shown in FIG. 8, the output of the positive voltage of the positive voltage charge pump circuit 1 included in the high voltage generating circuit and the output of the negative voltage via the rectifying element 4 can be switched and output. By adding a switching circuit 5 that can be done,
It is possible to generate positive and negative high voltage with one charge pump circuit. The portion corresponding to the charge pump circuit for generating a negative voltage of the conventional technology corresponds to the ring oscillator 2, the capacitor 3 and the rectifying element 4 of the present invention, but the ring oscillator 2 is much smaller than the charge pump circuit.
Since only one each of the capacitive element 3 and the rectifying element 4 is required, the area is much smaller than that of preparing a charge pump circuit for generating a negative voltage.

[0029]

According to the present invention, by using the structure for converting a positive high voltage into a negative high voltage, the problem of the charge pump circuit in which the PMOS transistor for directly generating the negative high voltage is arranged can be avoided. Can generate high voltage. That
At this time, a P-type silicon substrate is used as the booster circuit of the high voltage generation circuit.
Formed in the P-type well formed in the N-type well in the plate
Equipped with a built-in NMOS transistor as a boost element,
Source electrode of NMOS transistor and its transition
The same voltage will be applied to the P-type well formed in the star
Connected to the charge pump circuit or P-type
P-type well formed in N-type well in recon substrate
And PN contact with the N type diffusion layer formed in the P type well.
The PN diode formed by
If the charge pump circuit provided in the
Can be received between wells with high tolerance,
To generate negative high voltage without being affected by substrate bias effect
Negative voltage generation circuit with a large voltage margin.
Can be provided. In addition, as a rectifying element of the high voltage generation circuit
The N-type well and the P-type well formed in the N-type well.
PN diode formed by PN junction with
Alternatively, a P-type well and a P-type well formed in the P-type well
PN diode formed by PN junction with N-type well
If a high voltage is used, the generated high voltage
Since it is received between the well and the well, it is possible to handle higher voltage.
it can. In addition, the high-voltage generation circuit must be equipped with a switching circuit that can select between a high-voltage negative output and a high-voltage positive output.
For example, one charge pump circuit can generate high positive and negative voltages. A portion corresponding to a conventional charge pump circuit that generates a negative voltage corresponds to the ring oscillator, the capacitive element, and the rectifying element of the voltage generation circuit in the present invention, but the ring oscillator is very small compared to the charge pump circuit, Moreover, since only one capacitive element and one rectifying element are required, the area required is much smaller than when a charge pump circuit that generates a negative voltage is prepared, and the chip area can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional charge pump circuit using a PMOS transistor.

FIG. 2 is a block diagram showing an embodiment of a negative high voltage generator according to the present invention.

FIG. 3 is a circuit diagram showing an example of a charge pump circuit using an NMOS transistor of the booster circuit of the embodiment.

FIG. 4 is a circuit diagram showing an example of a configuration diagram of a negative high voltage generation unit including a ring oscillator, a capacitive element, and a rectifying element in the embodiment.

FIG. 5 is a diagram showing an example of voltage waveforms before and after the capacitance according to the embodiment.

FIG. 6 is a cross-sectional view showing an example of the structure of a PN diode used for the rectifying element of the same example.

FIG. 7 is a circuit configuration diagram showing an example of a rectifying element of the same example.

FIG. 8 is a block diagram showing another embodiment of the high voltage generator according to the present invention.

FIG. 9 is a circuit diagram showing an inverter of an example of a switching circuit of the same embodiment.

[Explanation of symbols] 1 Positive voltage charge pump 2,35 ring oscillator 3 capacitive elements 4 Rectifying element 5 switching circuit 31, 42 capacity 33 diode 41 NMOS transistor φ1, φ2 clock signal

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 16/30 G11C 11/4074 G11C 11/413

Claims (4)

(57) [Claims] 1. A positive high voltage provided with a charge pump circuit.
And a voltage output from the voltage boosting circuit.
An oscillation circuit equipped with a ring oscillator that uses pressure as a power source;
A capacitive element that receives an oscillation signal of the oscillation circuit at one end of an electrode
Is connected to the other end of the electrode of the capacitive element and generates a negative voltage.
And a rectifying element for producing the other end of the capacitive element.
It is a high voltage generation circuit that outputs a negative high voltage as an output terminal.
Thus, the charge pump circuit of the boosting circuit includes an N-channel MOS transistor formed in a P-type well formed in an N-type well in a P-type silicon substrate as a boosting element, and the N-channel MOS transistor is formed. Source electrode and the P-type well in which the transistor is formed are connected so as to have the same voltage .
High-voltage generation circuit that. 2. A positive high voltage provided with a charge pump circuit.
And a voltage output from the voltage boosting circuit.
An oscillation circuit equipped with a ring oscillator that uses pressure as a power source;
A capacitive element that receives an oscillation signal of the oscillation circuit at one end of an electrode
Is connected to the other end of the electrode of the capacitive element and generates a negative voltage.
And a rectifying element for producing the other end of the capacitive element.
It is a high voltage generation circuit that outputs a negative high voltage as an output terminal.
, The charge pump circuit of the step-up circuit includes a P-type well formed in N-type well in the P-type silicon substrate, the P
This provided with a PN diode formed by the PN junction between the N-type diffusion layer formed in the mold well as boosting element
And a high voltage generation circuit. 3. A positive high voltage provided with a charge pump circuit.
And a voltage output from the voltage boosting circuit.
An oscillation circuit equipped with a ring oscillator that uses pressure as a power source;
A capacitive element that receives an oscillation signal of the oscillation circuit at one end of an electrode
Is connected to the other end of the electrode of the capacitive element and generates a negative voltage.
And a rectifying element for producing the other end of the capacitive element.
It is a high voltage generation circuit that outputs a negative high voltage as an output terminal.
The rectifying element is formed by a PN diode formed by a PN junction between an N-type well and a P-type well formed in the N-type well, or a P-type well and the P-type well. A high voltage generation circuit characterized by using a PN diode formed by a PN junction with an N-type well. 4. A switching circuit for selecting between a negative high voltage output of the high voltage generating circuit according to claim 1 and a positive high voltage output of the boosting circuit. Characteristic high voltage generation circuit.