JP3408172B2 - Chip size package and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a chip size package and a method for manufacturing the same. A chip size package is also called a CSP and is a generic term for packages that are equal to or slightly larger than the chip size, and are packages intended for high-density mounting. The present invention relates to a technique for improving the reliability of a chip size package.

[0002]

2. Description of the Related Art Conventionally, BGA (Ba
ll Grid Array), a structure with a plurality of solder balls arranged in a plane, called a fine pitch BGA.
A structure in which the G outer shape is close to the chip size is known.

Recently, there is a wafer CSP described in "Nikkei Microdevice", August 1998, pp. 44-71. This wafer CSP is basically a CSP in which wiring and array pads are formed in a wafer process (pre-process) before dicing of chips.
With this technology, it is expected that the wafer process and the package process (post-process) will be integrated and the package cost can be significantly reduced. There are two types of wafer CSP, a sealing resin type and a rewiring type. The encapsulation resin type has a structure in which the surface is covered with encapsulation resin, similar to the conventional package, in which columnar terminals (metal posts) are formed on the wiring layer on the chip surface, and the surrounding area is covered with encapsulation resin. It is a solidifying structure. When the package is mounted on the printed circuit board, the stress generated by the difference in thermal expansion from the printed circuit board is concentrated on the metal posts. It is generally known that the longer the metal post is, the more the stress is dispersed.

On the other hand, the rewiring type has a structure in which rewiring is formed without using a sealing resin, as shown in FIG. An Al electrode 52, a wiring layer 53, and an insulating layer 54 are laminated on the surface of the chip 51, a metal post 55 is formed on the wiring layer 53, and a solder bump 56 is formed thereon. The wiring layer 53 is used as a rewiring for arranging the solder bumps 56 on the chip in a predetermined array.

The sealing resin type has a metal post of 100μ
High reliability can be obtained by lengthening the length to about m and reinforcing it with a sealing resin. However, the process of forming the sealing resin needs to be carried out by using a mold in a later step, which complicates the process. On the other hand, the rewiring type has an advantage that the process is relatively simple and most of the steps can be performed by a wafer process. However, it is necessary to relieve stress and improve reliability by some method.

[0006]

In order to secure the reliability of the rewiring type CSP, it is considered effective to lengthen the metal post 55 like the sealing resin type CSP. For that purpose, it is necessary to form the insulating layer 54 as thick as possible.

Therefore, it is conceivable to use a polyimide layer as the insulating layer 54. As is well known, polyimide is a liquid substance containing an organic solvent, and like the photoresist material, there are positive type and negative type, and they are patterned by exposure and development. A polyimide layer is formed as the insulating film 54, and a portion where a metal post is to be formed is selectively exposed and developed to form an opening.

However, the thickness of the positive polyimide is limited to 5 μm to 7 μm, and if it is 10 μm, the sensitivity of exposure and development is poor and it is not practical. Negative polyimide has better sensitivity than this, but it is used for exclusive developer (MNP
(System) is used, the limit is 20 μm to 25 μm. Therefore, the length of the metal post 55 formed in the opening of the insulating layer 54 is limited to 20 μm to 25 μm, and it is difficult to ensure reliability.

[0009]

The chip size package and the manufacturing method thereof according to the present invention have been made in view of the above problems, and the insulating layer is formed of at least two polyimide layers. As a result, the insulating layer can be formed thick, and the columnar terminals formed in the openings of this insulating layer can be lengthened.

Further, the two polyimide layers are preferably formed by using a negative polyimide. This allows
It is possible to expose and develop a thicker film than a positive polyimide.

Particularly, the second polyimide layer (second polyimide layer) is also filled in the opening of the first polyimide layer, and the film thickness of this portion becomes thick due to the step. If a negative polyimide is used, it is sufficient to expose except this portion, which is advantageous in terms of exposure and development.

Furthermore, it is preferable that the end of the second opening in the polyimide layer is located outside the end of the first opening. As a result, a hardened layer can be reliably formed on the second polyimide layer and defective resolution can be prevented.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 1, a semiconductor substrate 1 (wafer) on which an LSI having Al electrode pads 2 is formed is prepared, and the surface of the semiconductor substrate 1 is covered with a passivation film 3 such as a SiN film.

The Al electrode pad 2 is a pad for external connection of the LSI. The passivation film 3 on the surface is removed by etching, and a barrier metal 4 is formed on the entire surface. The barrier metal 4 is a barrier that is interposed between a wiring layer to be formed later and the Al electrode pad 2 to protect the Al electrode pad 2, and is formed by sputtering chromium (Cr), titanium (Ti), or the like.

Next, the wiring layer 6 connected to the Al electrode pad 2 is formed. The wiring layer 6 needs to be formed to a thickness of about 5 μm in order to secure the mechanical strength, and it is suitable to form it by a plating method. As shown in FIG. 2, a photoresist layer 5 is formed on the barrier metal 4 in a region except the region where the wiring layer 6 is formed.

Then, the barrier metal 4 is used as an electrode for plating, and the wiring layer 6 made of a Cu plating layer is formed on the barrier metal 4 not covered with the photoresist layer 5. After that, the photoresist layer 5 is removed, and etching is further performed using the wiring layer 6 as a mask to remove unnecessary portions of the barrier metal 4.

Next, as shown in FIG. 3, a first polyimide layer 7 is applied on the entire surface, and exposed and developed to form a first opening 8 in the first polyimide layer 7 on the wiring layer 6. To do.
As the first polyimide layer 7, it is preferable to use negative polyimide having high sensitivity. The maximum film thickness is 20
μm to 25 μm. The opening diameter of the first opening 8 is 5
About 0 μm is preferable.

After the development, the first polyimide layer may be baked at a temperature of about 200 ° C. This is to prevent mixing with the second polyimide layer formed in the next step.

Next, as shown in FIG. 4, a second polyimide layer 9 is applied on the entire surface. This second polyimide layer 9
Also, it is preferable to use a negative polyimide. The film thickness is 20 μm to 2 at maximum as in the first polyimide layer 7.
It is 5 μm. The first opening 8 is filled with a second polyimide layer 9.

Next, as shown in FIG. 5, the second opening 9 is formed on the first opening 8 by exposing and developing the second polyimide layer 9. The second opening 10 is formed at a position where it overlaps the first opening 8 in plan view, the polyimide with which the first opening 8 is filled is also removed, and the surface of the wiring layer 6 is exposed.

When a negative polyimide is used as the second polyimide layer, the exposed area is the area excluding the second opening 10. Then, after the development, the second polyimide layer 9 cured by the exposure remains in the exposed area, and the polyimide in the area to be the second opening 10 is removed by the action of the developing solution. As described above, by using the negative polyimide, it is not necessary to expose the thick polyimide layer filled in the first opening 8 (recess) to the underlying layer, and the original film thickness applied on the flat portion is eliminated. It suffices to expose the polyimide layer having Thereby, the thick second polyimide layer 9 having a thickness of 20 μm to 25 μm is formed.
The second opening 10 can also be formed by applying.

Further, it is preferable that the end of the second opening 10 is located outside of the end of the first opening 8 so as to be separated therefrom. That is, the photomask is designed so that Δ (Δ> 0) in FIG. 5 occurs. As a result, the cured layer can be reliably formed over the entire polyimide by exposure, and defective resolution of the polyimide can be prevented.

Next, as shown in FIG. 6, a seed layer 11 (plating electrode layer) for plating is formed on the entire surface. This seed layer serves as an electrode during plating, and Cu
Can be formed by sputtering. Then, the photoresist layer 12 is formed on the seed layer 11. The photoresist layer 12 is processed by the photolithography method so as to have openings on the first and second openings 8 and 10.

Next, as shown in FIG. 7, a metal post 1 as a columnar terminal made of Cu by electrolytic plating is used.
3, the barrier layer 14, and the solder bumps 15 are sequentially formed.
As the barrier layer 14, a Pt-based metal such as A is used in consideration of the barrier property against the solder bump containing Pb and Sn.
It is preferable to use a laminated film of u and Ni. The solder bumps 15 may be formed by electrolytic plating instead of
Balls may be mounted on the barrier layer 14 using the SMT technique.

Finally, as shown in FIG. 8, the photoresist layer 12 is removed, and unnecessary portions of the seed layer 11 are removed by etching using the solder bumps 15 as a mask. Here, instead of using the solder bumps 15 as a mask, a mask made of photoresist may be used.

Then, the semiconductor substrate 1 is divided into chips along a scribe line by a dicing process to complete a chip size package.

The above-described embodiment is a wafer CSP.
However, the present invention is characterized in that the steps of applying, exposing, and developing a polyimide layer as an insulating layer are repeated twice or more, and can be applied to other CSPs.

[0029]

According to the present invention, when the insulating layer of the chip size package is formed of the polyimide layer, the polyimide layer can be formed thick by applying the polyimide layer twice.

Particularly, by using the negative polyimide, it is possible to form a thick polyimide layer having a thickness of 40 μm to 50 μm. As a result, the metal posts are also 40 μm to 5 μm.
It can be formed as long as 0 μm, and even in a chip size package that does not use a sealing resin, the stress applied to the metal post can be relaxed, and the reliability can be improved.

[Brief description of drawings]

FIG. 1 is a first cross-sectional view showing a chip size package and a manufacturing method thereof according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 3 is a third cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 4 is a fourth cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 5 is a fifth cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 6 is a sixth cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 7 is a seventh cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 8 is an eighth cross-sectional view showing the chip size package and the manufacturing method thereof according to the embodiment of the present invention.

FIG. 9 is a sectional view showing a chip size package according to a conventional example.

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/60 H01L 23/12 501

Claims (5)

(57) [Claims] 1. A wiring layer connected to a metal electrode pad and extending to the chip surface, an insulating layer made of polyimide for covering the chip surface including the wiring layer, and an insulating layer formed on the wiring layer. In a chip size package including an opening and a columnar terminal formed in the opening,
The insulating layer comprises at least two polyimide layers ,
The opening in contact with the wiring layer, the other insulating layer above
Chip size package characterized by being smaller than the opening to be formed . 2. A wiring layer connected to a metal electrode pad and extending to the chip surface, an insulating layer made of polyimide for covering the chip surface including the wiring layer, and an insulating layer formed on the wiring layer. In a method of manufacturing a chip size package including an opening and a columnar terminal formed in the opening , a step of forming a first polyimide layer on the entire surface after forming the wiring layer , and then baking . Exposing and developing the first polyimide layer to form a first opening in the first polyimide layer on the wiring layer; and forming a second polyimide layer on the entire surface including the first opening. And a step of exposing and developing the second polyimide layer to form a second opening on the first opening.
And a step of forming columnar terminals so as to fill the first and second openings. 3. The method of manufacturing a chip size package according to claim 2, wherein the first and second polyimide layers are made of a negative polyimide. 4. The method of manufacturing a chip size package according to claim 2, wherein the end of the second opening is located outside the end of the first opening. 5. A wiring layer connected to a metal electrode pad and extending to the chip surface, an insulating layer made of polyimide covering the chip surface including the wiring layer, and an insulating layer formed on the wiring layer. In a method of manufacturing a chip size package including an opening and a columnar terminal formed in the opening, a first polyimide layer is formed on the entire surface after forming the metal electrode pad and the wiring layer on a semiconductor substrate. Forming and then baking ; exposing and developing the first polyimide layer to provide a first opening in the first polyimide layer on the wiring layer; and including the first opening. A step of forming a second polyimide layer on the entire surface,
Exposing and developing the second polyimide layer to form a second opening on the first opening; and forming columnar terminals to fill the first and second openings. When,
A method for manufacturing a chip size package, comprising: forming solder bumps on the columnar terminals; and dividing the semiconductor substrate into chips.