JP3407232B2 - Semiconductor memory device and operation method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of operating the same, and more particularly to a dynamic random access type semiconductor memory device capable of multi-valued storage composed of a one-transistor memory cell that does not require a capacitor for charge storage. And an operating method thereof.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device, a semiconductor device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) has been used. In particular, a semiconductor memory device using a MISFET as a switching element. Is often used.

Of these, a typical DRAM memory cell is composed of one MISFET as a switching element and one capacitor for accumulating electric charge. The electric charge is accumulated in the capacitor and the potential of the bit line is changed. In the high state and the state where there is no charge and the bit line potential is low,
The respective states are stored in "0" and "1".

In recent years, as the integration degree of semiconductor memory devices has been improved, it has been required to reduce the two-dimensional area of the capacitor together with the switching element. The potential that can be held decreases. Then, the difference in height of the bit line potential becomes small, so that it becomes difficult to read the stored data.
Further, there is a problem that it becomes weak against a soft error caused by α ray or the like.

In order to solve such a problem, a stack type capacitor, a fin type capacitor, a trench type capacitor, etc. have been developed in which the area of the capacitor is increased three-dimensionally to increase the accumulated charge amount of the capacitor. Furthermore, a capacitor using an insulating film having a high dielectric constant has been developed in order to increase the dielectric constant and increase the amount of accumulated charges.

However, as miniaturization progresses further, when a three-dimensional capacitor is used, the step difference of the element becomes large and it becomes difficult to flatten the surface, and the stress applied to the capacitor becomes large, which causes the influence of dielectric breakdown. There is a problem that the manufacturing yield is lowered and the reliability is lowered. On the other hand, when an insulating film having a high dielectric constant is used, there is a problem that the leak current increases as the insulating film becomes thinner.

Therefore, the present applicant has made the following various proposals in order to solve such a problem. The first proposal (Japanese Unexamined Patent Publication No. 54-5635) discloses an SOS (Silicon on Sapphire) which is isolated.
e) n-channel MISF formed in the island region of the structure
The present invention relates to a semiconductor memory device that stores data using only ET.

This semiconductor memory device uses a charge pump phenomenon in which a positive voltage is applied to the gate to generate a channel, and then the positive voltage is rapidly cut off to inject electrons flowing in the channel into the semiconductor substrate. The charge is written and held only by the MISFET, and by reading the change in the channel conductance of the semiconductor substrate,
The held data is read out.

The second proposal (Japanese Patent Laid-Open No. 56-1506).
3) is a modification of the first proposal, in which a low impurity concentration silicon layer is epitaxially grown on a sapphire substrate through a high impurity concentration silicon layer, and a source / drain region is formed in the low impurity concentration silicon layer. As compared with the first proposal, the number of crystal defects in the low impurity concentration silicon layer in which the source / drain regions are provided is reduced, so that the lifetime of the injected charges becomes longer and the refresh operation can be reduced. it can.

Further, a third proposal (Japanese Patent Laid-Open No. 6-1638)
No. 95) is SOI (Silicon on In).
A n-channel type MISFET having a slater structure is used, a polycrystalline silicon layer is embedded in a buried oxide film separating a semiconductor supporting substrate and a semiconductor layer, and a drain is formed in the polycrystalline silicon layer acting as a floating gate. -Injects electrons generated by avalanche breakdown, and changes the threshold voltage of the MISFET depending on the presence or absence of accumulated charges.

The third proposal is not intended to constitute a memory cell of a semiconductor memory device, but in principle, it can be used as an EPROM or EEPROM type semiconductor memory device.

[0012]

However, in the case of the first and second proposals, since the accumulated charge is of the same conductivity type as the conductivity type of the source / drain regions, the source / drain In a storage region of opposite conductivity type to the region,
Since it recombines with holes, which are the majority carriers in this accumulation region, and disappears, the charge retention time is as short as about 100 μsec, and there is a problem that frequent refresh operations are required.
In order to prolong the holding time, it was necessary to cool to liquid nitrogen temperature before use.

The third proposal is EPROM or E
Since it has an EPROM-like structure, when it is used as a semiconductor memory device, it is necessary to erase data by ultraviolet irradiation or heating, or to electrically erase by applying a high voltage. Longer, or
There is a problem that requires high voltage.

Therefore, the present invention provides a single MISFE.
When forming a memory cell using only T, the charge retention time is lengthened without cooling to the liquid nitrogen temperature, and
The purpose of the present invention is to significantly reduce the erase time and to enable multi-value storage.

[0015]

FIG. 1 is an explanatory view of a principle structure of a memory cell which constitutes a semiconductor memory device of the present invention. With reference to FIG. 1, means for solving the problem of the present invention is shown. Will be explained. 1A is a cross-sectional view of the memory cell, FIG. 1B is an equivalent circuit of the memory cell of FIG. 1A, and FIG. 1C is of the equivalent circuit of FIG. 7 is a characteristic curve showing a V _d -I _d characteristic of a memory cell.

Referring to FIG. 1A, according to the present invention, in a semiconductor memory device, a thickness 0 is provided on a supporting substrate 1 with an insulating film 2 interposed therebetween, and is completely electrically insulated and separated from an adjacent region. 1. One MISFET is provided in each of the plurality of semiconductor island regions 3 having a size of 1 μm or more, and the charge 12 for storing data, which is composed of charges of the opposite conductivity type to the source / drain regions 7 and 8 of the MISFET, is M.
It is characterized by accumulating in an electrically floating region 11 between the source / drain regions 7 and 8 of the ISFET.

See FIG. 1B. Further, according to the present invention, a thickness of 0.1 μm or more, which is provided on the support substrate 1 via the insulating film 2 and is completely electrically isolated from the adjacent region, is provided. A plurality of semiconductor island regions 3 are each provided with one n-channel type MISFET, and M
The MISF charges 12 for storing data, which are charges of the opposite conductivity type to the source / drain regions 7 and 8 of the ISFET, are provided.
In the operation method of the semiconductor memory device in which the electric charge is accumulated in the electrically floating region 11 between the source / drain regions 7 and 8 of the ET, in the bit line 14 with respect to the source region 7 connected to the hold line 13, A voltage is applied so that the voltage of the connected drain region 8 becomes positive, and
Data is written by selectively applying to the gate electrode 6 connected to the word line 15 a potential such that the surface of the channel region 9 is inverted into n-type.

Further, the present invention is characterized in that in the method of operating a semiconductor memory device, data writing is performed with a positive potential applied to the supporting substrate 1. Further, the present invention is
The method of operating a semiconductor memory device is characterized in that the positive potential applied to the word line 15 has two or more values.

Further, according to the present invention, in the method of operating a semiconductor memory device, a voltage is applied so that the bit line 14 and the hold line 13 have a positive potential with respect to the region 11 in which they are electrically floating at the same potential. In addition, the word line 15 is characterized in that a voltage is applied to the electrically floating region 11 so as to be zero or a positive potential to hold data.

Further, the present invention is characterized in that in the method of operating a semiconductor memory device, data is held by applying a potential of zero or the same polarity to the support substrate 1 at the same cycle as the hold line 13.

Further, according to the present invention, in the method of operating a semiconductor memory device, a voltage is applied to the hold line 13 so that the bit line 14 has a positive potential and the word line 15 is electrically floating. Data is read by applying a voltage to 11 so as to be zero or a negative potential.

Further, the present invention is characterized in that, in the method of operating a semiconductor memory device, all of the hold line 13, the bit line 14 and the word line 15 are set to zero potential to erase data.

[0023]

Next, the operation of the present invention will be described with reference to FIG. FIG. 1A: Thicknesses of a plurality of semiconductor island-shaped regions 3 provided on a reference support substrate 1 with an insulating film 2 serving as an isolation insulating film interposed therebetween and completely electrically insulated and separated from adjacent regions. Is 0.1 μm or more, and when one MISFET is provided in each of the semiconductor island regions 3, the depletion layer 10 generated in the channel region 9 between the source / drain regions 7 and 8 of the MISFET does not reach the electric field. A region 11 that is electrically floating is formed. By accumulating a charge 12 for storing data, which is composed of a charge having a conductivity type opposite to that of the source / drain regions 7 and 8 of the MISFET, in the electrically floating region 11.
Data can be stored for a long time with only one MISFET.

A voltage is applied to the source region 7 connected to the hold line 13 so that the voltage of the drain region 8 connected to the bit line 14 becomes positive, and the source region 7 is connected to the word line 15. Electrons (e ⁻ ) are generated in the drain region 8 by selectively applying a potential such that the surface of the channel region 9 is inverted to the n-type to the existing gate electrode 6.
Traveling toward the side, collision ionization occurs in the vicinity of the drain region 8 to form an electron-hole pair.

Electrons having high mobility in the electron-hole pairs are generated by the gate electric field and the drain electric field.
However, holes (e ⁺ ) 12 having a low mobility do not escape to the source region 7 but remain in the electrically floating region 11 beyond the depletion layer 10 generated in the channel region 9. Thus, the data will be written.

Further, by writing data in a state where a positive potential is applied to the supporting substrate 1, holes 12 are written at the time of writing.
Can be moved away from the supporting substrate interface with many interface states by the Coulomb repulsive force.
Can be prevented from decreasing due to the interface state. Further, by setting the positive potential applied to the word line 15 to have two or more values, multi-value storage becomes possible.

Further, a voltage is applied so that the bit line 14 and the hold line 13 have the same potential and a positive potential with respect to the electrically floating region 11 which is a charge storage region, and the source region 7 and the drain region. By increasing the potential barrier of the holes 12 to the holes 12, the accumulated holes 12 are prevented from diffusing into the n ⁺ type source / drain regions 7 and 8 and disappearing by recombination, and at the same time, the word line A voltage is applied to the electrically floating region 11 so as to be zero or a positive potential, whereby the accumulated holes 12 are prevented from diffusing and disappearing at the interface of the gate insulating film, and are retained. The time can be lengthened.

Further, by applying a potential of zero or the same polarity as the hold line 13 to the supporting substrate 1, the accumulated holes 12 can be kept away from the supporting substrate interface having many interface states. Further, the holding time can be extended.

In addition, the bit line 1 with respect to the hold line 13
When a voltage is applied so that 4 has a positive potential, and a voltage is applied with respect to the electrically floating region 11 of the word line 15 to zero or a negative potential, holes 12 are accumulated and the channel region is accumulated. The potential barrier of the source region 7 to the source region 7 is lowered and positive feedback is applied, and the source region 7 is the emitter, the channel region 9 is the base, and the drain region 8 is
A horizontal npn bipolar transistor having a collector as a transistor operates, and data can be read by detecting a collector current flowing by this Bip operation.

In this case, the collector current I _d (I _C ) is
The hole current amount I _B is represented by h _FE times the hole current amount I _B.
Depends on the concentration of accumulated holes. Although this value of _{h FE (≡I C / I B} ) is several tens to several hundreds, the base region, i.e., depending on the length and the impurity concentration of the channel region, the collector current I _d (I _C ) Depends on the drain voltage and the gate voltage.

See FIG. 1C. FIG. 1C shows the V _d -I _d characteristic, in which the holes generated by impact ionization increase as the drain voltage V _d increases, and the channel. The Bip operation is started when the potential of the region decreases. In this case, if the gate voltage V _g is low, the carrier concentration in the inversion layer is low, so the probability of impact ionization is reduced, and the amount of holes generated is reduced, so that the collector current I _d (I _C ) is also limited and reduced. .

Further, by setting all of the hold line 13, the bit line 14, and the word line 15 to zero potential,
Data can be erased by causing the holes 12 to flow as diffusion currents in the source / drain regions 7 and 8 which are n ⁺ -type regions and disappear by recombination.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A SIMOX (Separatio) which is a first embodiment of a method of manufacturing a semiconductor memory device according to the present invention.
A manufacturing process using the n by IMplanted OXygen) method will be described with reference to FIGS. 2 to 4. 3 and 4 show the state of the wafer in FIG.
This is an enlarged partial area corresponding to one memory cell.

Referring to FIG. 2A, first, the boron concentration is 1.35 × 10 ¹⁵ cm ⁻³ and the thickness is 6
By implanting oxygen ions 17 into a silicon semiconductor substrate 16 of 00 μm at an acceleration voltage of 200 KeV with a dose amount of 1.8 × 10 ¹⁸ cm ⁻² , an ion implantation layer 18 is formed at a position of 0.4 μm in depth. To do.

Next, referring to FIG. 2B, the substrate temperature is set to 1 in an argon gas atmosphere.
By performing heat treatment at 320 ° C. for 6 hours, the implanted oxygen ions 17 and Si are combined to form a SiO ₂ layer 19 having a thickness of 0.4 μm and a silicon semiconductor layer 20 having a thickness of 0.3 μm. Then, an SOI structure is formed.

Next, as shown in FIG. 3C, a pad oxide film 21 of 50 Å is formed on the surface of the silicon semiconductor layer 20 by thermal oxidation, and then a Si ₃ N ₄ film 22 of 0.1 μm is deposited by the CVD method. , 60 KeV using the resist mask 23 formed by applying and patterning a resist layer as a mask
The B ions 24 are ion-implanted at a dose amount of 5 × 10 ¹³ cm ^-2 with the acceleration voltage of.

Next, as shown in FIG. 3D, the Si ₃ N ₄ film 22 is etched using a resist mask to form a selective oxidation mask, the resist mask is removed, and then wet oxidation at 1000 ° C. is performed. A 0.6 μm element isolation oxide film 25 is formed by thermal oxidation in an atmosphere. In this case, a part of the injected B is deposited on the interface between the element isolation oxide film 25 and the silicon semiconductor layer 20 and becomes a channel stopper (not shown).

Next, after removing the selective oxidation mask and the pad oxide film, a gate oxide film 26 of 50Å is formed by thermal oxidation, and then 25 KeV for controlling the threshold V _th.
The B ions 27 are ion-implanted at a dose amount of 1.5 × 10 ¹² cm ⁻² at the acceleration voltage of.

Next, referring to FIG. 4 (f), 0.2 μm thick polycrystalline silicon is deposited,
After doping P to 1 × 10 ²⁰ cm ⁻³ , the polycrystalline silicon is patterned using a resist mask (not shown) having a predetermined pattern as a mask to form the gate electrode 28.
To form.

See FIG. 4 (g). Then, after removing the resist mask, 20 KeV
5 × 10 at accelerating voltage ¹⁵cm^-2As ion with a dose of
29 ion-implanted, nitrogen atmosphere at 800 ℃ 20 minutes
Activated As ions by heat treatment during
Source / drain regions 30 and 31 are formed.

Finally, refer to FIG. 4 (h). Finally, PSG (phosphosilicate glass) film 3
2 is deposited to form a contact hole in the PSG film 32, and then an aluminum layer is vapor-deposited on the entire surface and then patterned to form source / drain electrodes 33 and 34 and a wiring layer (not shown) connected thereto. Then, the memory cell is completed.

In a conventional DRAM, MISFET
When the area occupied by the capacitor is 1, the area occupied by the capacitor is about 0.5, and the area occupied by the entire memory cell is required to be 1.5, whereas the semiconductor memory device of the present invention has one area. Since only one MISFET can form one memory cell, its occupied area is 1, and the storage density is improved by 1.5 times.

Next, the manufacturing process of the second embodiment of the present invention using the substrate bonding method will be described with reference to FIG. See FIG. 5A. First, the boron concentration is 1.35 × 10 ¹⁵ cm ⁻³ and the thickness is 6
The first silicon semiconductor substrate 35 of 00 μm is wet O
_By heat-treating at a substrate temperature of 1100 ° C. for 1 hour in ₂ atmospheres, the surface of Si with a thickness of 0.6 μm is
An O ₂ film 36 is formed.

Next, referring to FIG. 5B, the second silicon semiconductor substrate 37 and the first silicon semiconductor substrate 35 having a boron concentration of 1.35 × 10 ¹⁵ cm ⁻³ and a thickness of 600 μm are superposed on each other, 50gcm ^-2
Under the weight of, the two are naturally joined by Van der Waals force, and in a dry O ₂ atmosphere, 1
By heat treatment at a substrate temperature of 100 ° C. for 2 hours,
Stick both.

Next, referring to FIG. 5C, the surface of the first silicon semiconductor substrate 35 is ground and then polished to reduce the thickness of the first silicon semiconductor substrate 35 to 0.5 μm. Then, through the same steps as those in FIGS. 3C to 4H,
A memory cell basically similar to the structure shown in (h) is completed.

Next, with reference to FIG. 6, a manufacturing process of the third embodiment of the present invention using another substrate bonding method will be described. See FIG. 6A. First, the boron concentration is 1.00 × 10 ¹⁹ cm ⁻³ (specific resistance:
0.01 Ω · cm) and a thickness of 600 μm on the surface of the high impurity concentration silicon semiconductor substrate 38, the boron concentration is 1.3
A low impurity concentration silicon semiconductor layer 39 of 5 × 10 ¹⁵ cm ⁻³ (specific resistance: 10 Ω · cm) is epitaxially grown to 0.3 μm.

Next, referring to FIG. 6B, a 0.5 μm SiO ₂ film 41 is formed on the surface, the impurity concentration is 1.35 × 10 ¹⁵ cm ⁻³ , and the thickness is 600 μm.
m of the silicon semiconductor substrate 40 and the high-impurity concentration silicon semiconductor substrate 38 are superposed on each other, and the two are naturally joined by Van der Waals force while applying a weight of about 50 gcm ⁻² , and the two are subjected to 1000 in a dry O ₂ atmosphere. ℃
The two are pasted together by heat treatment at the substrate temperature of 1 hour.

Next, referring to FIG. 6C, the surface of the high impurity concentration silicon semiconductor substrate 38 having the low impurity concentration silicon semiconductor layer 39 formed thereon is ground to 2
After the thickness of 00μm, HF and HNO ₃ high impurity concentration silicon semiconductor substrate 3 using an etching solution consisting of
Only 8 is selectively removed by etching to leave the low impurity concentration silicon semiconductor layer 39 having a thickness of 0.3 μm. Then, through the same steps as in FIGS. 3C to 4H,
A memory cell basically similar to the structure shown in FIG. 4H is completed.

Although the thickness of the silicon layer is described as 0.3 μm or 0.5 μm in each of the above-mentioned embodiments, this thickness does not depend on the source / source when the memory cell is formed.
It suffices that the thickness is not less than 0.1 μm, that is, the thickness at which an electrically floating region that is not covered by the depletion layer 10 generated in the channel region between the drain regions is formed.

The thickness of the isolation insulating film (19 in FIG. 2, 36 in FIG. 5, 41 in FIG. 6) is 0.4 μm to 0.
Although 6 μm is adopted, it is not limited to these numerical values. Further, the thickness of the gate insulating film and the gate electrode is described as 50 Å and 0.2 μm, but the thickness is not limited to these values, and 45 Å to 55 Å respectively.
And 0.18 to 0.22, and the concentration of P doped in the polycrystalline silicon that becomes the gate electrode is 2
It may be × 10 ²⁰ cm ^-3 or less.

The B concentration in the channel region is 6 × 10 ^16.
cm ^{−3 to} 6 × 10 ¹⁷ cm ⁻³ , preferably 3.3 × 10 ¹⁷
cm ⁻³ , the depth of the source / drain region is 0.15 μm or less, preferably 0.1 μm,
The impurity concentration of the source / drain region is 6 × 10 ^{19 to} 5
× 10 ²⁰ cm ^-3, preferably may be a 3.3 × 10 ²⁰ cm ^-3, further, the channel length may be at 0.15μm or more.

Next, with reference to FIG. 7, the most basic first embodiment of the operation method of the semiconductor memory device using the n-channel type MISFET of the present invention will be described. See FIG. 7A. FIG. 7A is connected to each drain region at the time of writing data, holding data, reading data, and erasing data in the semiconductor memory device of the present invention. Bit line,
The voltage (operation pulse) applied to the word line connected to the gate electrode and the hold line connected to the source region is shown, and the operation pulse in the state of “0” for accumulating and holding holes is shown in the upper stage. The lower part shows the operation pulse in the state of "1" in which holes are not accumulated.

First, at the time of data writing, a positive voltage (3V in the case of the figure) is applied to the bit line and word line of the memory cell in which "0" data is written, the hold line is set to 0V, and the MISFET is turned on. By doing so, impact ionization occurs near the drain, and the electrons in the electron-hole pairs generated by impact ionization escape to the gate electrode and drain region, thereby accumulating holes in the electrically floating region in the semiconductor layer. To do. The MISFET may be turned off by applying a voltage of 0 V to the word line of the memory cell in which the data of "1" is written, that is, the memory cell in which holes are not accumulated, so that the inversion layer is not generated. .

Next, at the time of holding data, the potential of the word line of each memory cell is set to 0V, and a positive voltage (3V in the case of the figure) is applied to the bit line and the hold line of each memory cell.
Is applied to increase the potential barrier of the source / drain region against holes to prevent the holes from diffusing into the source / drain regions. In this case, the lifetime of the holes strongly depends on the crystallinity of the pn junction surface or the Si / SiO ₂ interface, but it is estimated to be about 2 to 10 msec. Therefore, the refresh time is 2 to 4 mse.
A value of about c is required by design.

Next, at the time of reading data, with the potential of the word line and the hold line of each memory cell set to 0V,
Positive voltage (3V in the figure) on the bit line of each memory cell
Is applied. In this case, since the potential barrier of the channel region of the memory cell is lower than that of the source region due to accumulated holes, a positive voltage is applied to the bit line to form a potential gradient between the source and drain. Causes electrons to flow from the source region toward the drain region. In this case, the potential of the word line may be negative.

This drain current is not a normal MIS operation flowing through the inversion layer on the channel surface but a current component due to the Bip operation flowing in the silicon semiconductor substrate, and the drain current is accumulated holes. Proportional to concentration. On the other hand, in the memory cell in which holes are not accumulated, the Bip operation does not occur, and the drain current does not flow because the word line is 0 V and the MISFET remains in the OFF state. Therefore, this difference in current is detected. By directly reading with the circuit, "0" or "1" can be read.

The current can be detected by the amount of drain potential fluctuation. That is, when a current flows through the drain, a counter electromotive force proportional to the amount of current flowing through the bit line is generated, and this back electromotive force temporarily lowers the potential of the drain. Is also good. This method is effective for power saving of the device, but the detection accuracy is inferior to the former method of directly detecting the current amount.

Next, at the time of erasing data, the potentials of the bit line, the word line, and the hold line of each memory cell are all set to 0 V, so that the accumulated holes are n ⁺ type source / drain regions. Flows in by diffusion into and disappears by recombining with electrons. The erasing time in this case is determined from the hole moving speed (4.3 × 10 ⁷ cm / sec) and the channel length (0.15 μm = 0.15 × 10 ⁻⁴ cm).
It is estimated to be about 0.35 psec.

Although the above description of the operation has been made with 1 bit / cell of "0" and "1", the semiconductor memory device of the present invention is capable of multilevel storage.
This multi-valued storage method itself is known in principle, and data other than “0” or “1” can be stored by setting the charge storage state to three or more. By setting four charge storage states, it is possible to store twice as many bits as the conventional one.

7B and 7C. FIG. 7B shows a normal 1-bit / cell storage system. FIG. 7C shows a 2-bit / cell multi-value storage system. To explain. When storing 8-bit data (11100100 in the figure),
As shown in (b), the conventional 1-bit / cell storage method required 8 cells, but in the 2-bit / cell multi-value storage method, 4 cells are sufficient because each cell stores 2 bits. Therefore, the degree of integration is simply increased by a factor of two, but if the presence or absence of a capacitor is taken into consideration, the degree of integration is improved by a factor of three.

As described above, the multi-valued storage method is an attractive method for an ultra-high density memory because the storage density can be improved without miniaturizing the elements, but a method of accumulating charges by a conventional capacitor is used. Since the capacitance is extremely small, the difference between the stored amounts of four or more stored charges is too small,
Since it is difficult to accurately detect the difference, it has not been put into practical use.

However, in the memory cell constituting the semiconductor memory device of the present invention, the amount of holes accumulated depends on the gate voltage level applied as shown in FIG. By selecting and applying one of these levels, multi-value storage becomes possible, and since the drain current (collector current) is detected during data reading, the difference in the accumulated charge amount is Even if it is small, it is amplified by _hFE (several tens to several hundreds) times and detected, so that a highly accurate detection circuit is not required, and reading of multi-valued storage can be easily performed.

Next, with reference to FIGS. 8 to 9, second to fifth embodiments of the method of operating a semiconductor memory device using the n-channel type MISFET of the present invention will be described. 8 to 9 are similar to FIG. 7A, the bit line, the word line, and the hold during data writing, data holding, data reading, and data erasing. It shows the voltage (operating pulse) applied to the line,
The upper row shows the operation pulse in the state of "0" for accumulating / holding holes, and the lower row shows the operation pulse in the state of "1" for not accumulating holes.

See FIG. 8A. FIG. 8A is an explanatory diagram of the second embodiment relating to the operation method of the semiconductor memory device. Compared with the first embodiment, a positive voltage ( In the case of the figure, it is different only in that 3 V is applied, and when writing other data,
Since the driving pulse at the time of reading the data and at the time of erasing the data is the same as that of the first embodiment, only the data holding will be described.

When holding data, a positive voltage (3 V in the case of the figure) is applied to the bit line and the hold line of each memory cell in the same manner as in the first embodiment, and the source / drain region for holes is held. The potential barrier is increased to prevent it from diffusing into the source / drain regions, and by applying a voltage of 3 V to the word line, holes diffuse to the gate oxide film interface and disappear due to the interface state or the like. Since this is prevented, the charge retention time is improved as compared with the first embodiment.

Next, referring to FIG. 8B, a third embodiment of the method of operating the semiconductor memory device will be described with reference to FIG. 8B. This third embodiment is the first embodiment. Compared with, the point at which a positive voltage (10 V in the case of the figure) is applied to the supporting substrate during data retention, that is,
The only difference is that a voltage is applied to the support substrate at the same period as the hold line, and the drive pulse for writing other data, reading data, and erasing data is the same as the first embodiment. Since it is the same as the example, only the data retention will be described.

When data is held, a positive voltage (3 V in the figure) is applied to the bit line and the hold line of each memory cell as in the first embodiment, and the source / drain regions for holes are The potential barrier is increased to prevent it from diffusing into the source / drain regions, and by applying a voltage of 10 V to the supporting substrate, holes diffuse to the interface of the isolation oxide film and disappear due to the interface state or the like. Since this is prevented, the charge retention time is improved as compared with the first embodiment, and substantially the same effect is obtained when compared with the second embodiment.

The voltage applied to the support substrate may be the same as the voltage applied to the bit line or the hold line, but since the thickness of the isolation oxide film is as thick as 0.4 to 0.6 μm, the electric field is weakened. In order to prevent the diffusion of holes more effectively, it is preferable to apply a voltage of about + 10V.

Next, referring to FIG. 9A, a fourth embodiment relating to the operation method of the semiconductor memory device will be described. This fourth embodiment is the second embodiment. Compared with, the point at which a positive voltage (10 V in the case of the figure) is applied to the supporting substrate during data retention, that is,
The only difference is that a voltage is applied to the support substrate at the same cycle as the hold line, and the drive pulse for writing other data, reading data, and erasing data is the same as that of the second embodiment. Since it is the same as the example, only the data retention will be described.

When data is held, a positive voltage (3 V in the case of the figure) is applied to all of the word line, bit line and hold line of each memory cell, as in the second embodiment.
Prevents holes from diffusing into the source / drain regions by increasing the potential barrier of the source / drain regions against holes, and preventing holes from annihilating due to the interface states and the like. In addition, by applying a voltage of 10 V to the supporting substrate, holes are prevented from diffusing to the interface of the isolation oxide film and disappearing due to the interface state, etc. Therefore, compared with the second and third embodiments. The charge retention time is further improved.

Next, referring to FIG. 9B, a fifth embodiment of the method of operating the semiconductor memory device will be described with reference to FIG. 9B. This fifth embodiment is the fourth embodiment. Compared with the above, the only difference is that a positive voltage (10 V in the figure) is applied to the supporting substrate at the time of writing data.
Also, since the driving pulse at the time of erasing data is the same as that of the fourth embodiment, only the data writing will be described. In addition, the potential of the supporting substrate in the drawing is shown by overlapping with the drive pulse of the word line.

At the time of writing data, as in the first to fourth embodiments, a positive voltage (3 V in the case shown) is applied to the bit line and the word line of the memory cell to which the data of "0" is written. , The hold line is set to 0 V, and the MISFET is turned on to cause collision ionization in the vicinity of the drain, and electrons in the electron-hole pair generated by the collision ionization are released to the gate electrode and the drain region, so that holes are semiconductor. Accumulates in electrically floating areas of the layer.

In this case, by continuously applying a positive voltage (10 V in the figure) to the supporting substrate from writing to holding, holes are separated from the interface of the isolation insulating film by Coulomb repulsion, and writing and holding are performed. It is possible to prevent the holes from disappearing due to the interface state during the momentary switching operation between and. Since holes are not accumulated in the memory cell in which the data of "1" is written, even if a positive voltage is applied to the supporting substrate, no particular effect is produced.

In each of the above embodiments of the semiconductor device and the method of operating the same, the n-type MISFET is described, but in principle, only the speed becomes slower, and the p-type MISFET is used. In that case, the accumulated charges become electrons, and the voltage applied to each signal line has a polarity opposite to that of the voltage applied in each of the above embodiments.

[0075]

According to the present invention, a MISF having an SOI structure is provided.
Since the charge of the opposite conductivity type to the source / drain region is stored in the electrically floating region of the memory cell composed of ET, the capacitor is not required and the charge is stored and read by the Bip operation. Since multi-value storage is possible, the degree of integration can be significantly improved as compared with the conventional semiconductor memory device composed of one transistor and one capacitor, and the accumulated charge has a conductivity opposite to that of the source / drain regions. In this mode, by applying an appropriate potential to the support substrate in its operation to prevent the accumulated charges from disappearing due to recombination, the charge retention is improved as compared with the conventional semiconductor memory device including only one transistor. The time can be lengthened and the refresh time can be lengthened, and the erase time can be significantly shortened.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a principle configuration of a memory cell that constitutes a semiconductor memory device of the present invention.

FIG. 2 is an explanatory view of a manufacturing process up to the middle of the first embodiment of the method of manufacturing a semiconductor memory device according to the present invention.

FIG. 3 is an explanatory diagram of the manufacturing process up to the middle of FIG. 2 and subsequent steps of the first embodiment of the method of manufacturing a semiconductor memory device according to the present invention.

FIG. 4 is an explanatory diagram of the manufacturing process after FIG. 3 of the first embodiment of the method of manufacturing a semiconductor memory device according to the present invention.

FIG. 5 is an explanatory view of the manufacturing process up to the middle of the second embodiment of the method of manufacturing a semiconductor memory device according to the present invention.

FIG. 6 is an explanatory view of a manufacturing process up to the middle of the third embodiment of the method of manufacturing a semiconductor memory device according to the present invention.

FIG. 7 is an explanatory diagram of a first embodiment of an operating method of a semiconductor memory device of the present invention.

FIG. 8 is an explanatory diagram of second and third embodiments of the method of operating the semiconductor memory device of the present invention.

FIG. 9 is an explanatory diagram of fourth and fifth embodiments of the method of operating the semiconductor memory device of the present invention.

[Explanation of symbols]

1 Support Substrate 2 Insulating Film 3 Semiconductor Island Region 4 Element Isolation Insulating Film 5 Gate Insulating Film 6 Gate Electrode 7 Source Region 8 Drain Region 9 Channel Region 10 Depletion Layer 11 Electrically Floating Region 12 Hole 13 Hold Line 14 bit line 15 word line 16 silicon semiconductor substrate 17 oxygen ion 18 ion implantation layer 19 SiO ₂ layer 20 silicon semiconductor layer 21 pad oxide film 22 Si ₃ N ₄ film 23 resist mask 24 B ion 25 selective oxide film 26 gate oxide film 27 B ion 28 Gate electrode 29 As ion 30 Source region 31 Drain region 32 PSG film 33 Source electrode 34 Drain electrode 35 First silicon semiconductor substrate 36 SiO ₂ film 37 Second silicon semiconductor substrate 38 High impurity concentration silicon semiconductor substrate 39 Low Impurity Concentration Silicon Semiconductor Layer 40 Silicon Semiconductor Body substrate 41 SiO ₂ film

Claims (8)

(57) [Claims] 1. A support substrate is provided via an insulating film,
In addition, one MISFET is provided in each of a plurality of semiconductor island-shaped regions having a thickness of 0.1 μm or more, which is completely electrically insulated from the adjacent region, and has a conductivity type opposite to that of the source / drain regions of the MISFET. A semiconductor memory device characterized in that charges for storing data, which are charges, are accumulated in an electrically floating region between the source and drain regions of the MISFET. 2. Provided on a supporting substrate via an insulating film,
Further, one n-channel type MISFET is provided in each of a plurality of semiconductor island-shaped regions having a thickness of 0.1 μm or more, which are completely electrically insulated from the adjacent regions, and the MIS is provided.
Charges for data storage composed of charges of opposite conductivity type to the source / drain region of the FET are added to the source / drain region of the MISFET.
In a method of operating a semiconductor memory device, wherein the electric charge is accumulated in an electrically floating region between drain regions, at least the source region connected to a hold line at the time of writing data is connected to a bit line. Data is written by applying a voltage so that the voltage of the drain region becomes positive and selectively applying a potential such that the surface of the channel region is inverted to n-type to the gate electrode connected to the word line. A method of operating a semiconductor memory device, comprising: 3. The method of operating a semiconductor memory device according to claim 2, wherein data writing is performed while a positive potential is applied to the supporting substrate. 4. The method of operating a semiconductor memory device according to claim 2, wherein the positive potential applied to the word line has two or more values. 5. A voltage is applied so that the bit line and the hold line have the same potential and a positive potential with respect to the electrically floating region, and the word line has the electrically floating region. The data is retained by applying a voltage to zero or a positive potential with respect to the data.
5. The method for operating the semiconductor memory device according to any one of items 4 to 4. 6. The method of operating a semiconductor memory device according to claim 5, wherein data is held by applying a potential of zero or the same polarity to the supporting substrate at the same cycle as that of the hold line. 7. A voltage is applied to the hold line so that the bit line has a positive potential, and the word line has a zero potential or a negative potential with respect to the electrically floating region. 7. The method of operating a semiconductor memory device according to claim 2, wherein data is read by applying a voltage. 8. The semiconductor memory device according to claim 2, wherein the hold line, the bit line and the word line are all set to zero potential to erase data. How it works.