JP2002124586A - Semiconductor memory device, circuit and method for reading the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide practically sufficient charge holding ability while providing the volatile operation of high speed/low voltage or the like by making the film thickness of a tunnel insulating film <=3 nm. SOLUTION: A tunnel insulating film 104 is made <=3 nm. Besides, both a distance x1 between the gate electrode side terminal part of a source area 102 and the source area 102 side terminal part of a gate electrode and a distance x2 between the gate electrode side terminal part of a drain area 103 and the drain area 103 side terminal part of the gate electrode is made into 1 to 20 nm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor volatile memory having a floating gate, a driving method thereof, a signal charge reading method, and a signal charge reading circuit.

[0002]

2. Description of the Related Art As a background art of the present invention, FIG. 6A shows an example of a typical memory element (flash memory) conventionally used. On a semiconductor substrate 301 made of p-type silicon, a tunneling insulating film 307 made of a silicon oxide film of about 7 nm is formed. On top of this, P is 10 ¹⁹ -10 ²¹ cm ^-3
A floating gate 305 made of lightly doped polysilicon is formed. A block insulating film 306 made of a silicon oxide film of about several tens nm is formed thereon, and a control gate 307 made of polysilicon doped with P by about 10 ¹⁹ to 10 ²¹ cm ^-3 is formed thereon. The entire structure is covered with a passivation insulating film 309 made of a silicon oxide film. As on the surface of the semiconductor substrate 301, As
There are a source region 302 and a drain 303 doped about 10 ¹⁹ to 10 ²¹ cm ^-3 , and a part thereof is a floating gate 3
05 overlaps. The source region 302 and the drain 303 are contacted by an electrode 308 made of metal. Although not shown in this cross-sectional view, the control gate 307 is also contacted by the electrode 308.

FIG. 6B shows a semiconductor substrate 30 shown in FIG.
1 is an electron energy distribution in a CC ′ section of FIG. Further, A and B in FIG. 6 (b) are AA ′ line and BB ′ in FIG. 6 (a).
The position of the intersection between the line and the semiconductor surface is shown.

Next, electron energy distributions along the line AA 'and the line BB' are shown in FIGS. 7 (a1) and 7 (b1). Figures 7 (a1) and (b)
1) is the distribution in the thermal equilibrium state at V _C = 0V. In these figures, regions 1, 2, 3, 4, and 5 are a control gate 307, a block insulating film 306, and a floating gate 30 respectively.
5, corresponding to the tunneling insulating film 304 and the semiconductor substrate 301. Since the control gate 307, the floating gate 305, and the source region 302 are formed of n-type silicon, the energy distribution at the point B is substantially constant from the region 1 to the region 5. On the other hand, at the point A, since the region 5 is p-type silicon, the energy of the region 5 is higher than that of the regions 1, 2, and 3 by the built-in potential.

The signal charge is written by hot electron injection at a channel or drain end or by a semiconductor substrate.
Fowler-Nordheim from 301 to floating gate 305
(FN) tunneling injection is used. Here, the case of FN tunneling injection, which is generally widely used, is considered.

When writing signal charges, the source region 302
Then, the drain 303 is grounded, and a positive voltage is applied to the control gate 307 with respect to the substrate (FIGS. 7 (a2) and (b2)). At the point A, since the substrate surface is inverted, electrons are supplied from the source region 302 and the drain 303 to the point A. When the electric field strength in the tunneling insulating film becomes 10 MV / cm or more, the electrons supplied to the point A
It is injected into the floating gate 305 by N tunneling. At the end of the desired charge injection, the control gate voltage is
The voltage is returned to 0V, and the state shown in FIGS. 7 (a3) and (b3) is established. In this case, the tunneling insulating film has a sufficiently large thickness of about 7 nm, so that the direct tunneling probability is negligibly small. For this reason, the signal charges accumulated in the floating gate 305 do not leak to the semiconductor substrate 301. When the signal charge is accumulated in the floating gate 305, the threshold voltage (V _th ) of the transistor increases. Therefore, high-speed, non-destructive reading of the signal charge can be easily performed by a known method.

The erasure of signal charges by FN tunneling is performed as follows. The source region 302 and the drain 303 are grounded, and a negative voltage is applied to the control gate 307. As in the case of writing the signal charge, when the electric field strength in the tunneling insulating film becomes 10 MV / cm or more, the signal charge is written out to the semiconductor substrate 301 by FN tunneling, and the memory contents are erased.

As described above, in the flash memory, the floating gate 305 is completely covered by the thick tunneling insulating film 304 having a large potential barrier, the block insulating film 306, and the passivation insulating film 309. Charge is floating gate 305
Completely trapped inside. For this reason, flash memories have a charge retention capacity of 10 years or more.

In a flash memory, when the thickness of a tunneling insulating film is reduced to 7 nm or less, a leak current increases with time due to repeated application of an electric field of 10 MV / cm or more during writing / erasing, which may cause a serious problem in reliability. There is. Therefore, the thickness of the tunneling insulating film of the flash memory is generally set to about 7 nm or more. This makes it possible for the floating gate to hold charge for a long period of time.

[0010]

As described above, an example of a nonvolatile memory has been described as background art of the present invention. Here, if the thickness of the tunneling insulating film in the nonvolatile memory is 3 nm or less, the probability of direct tunneling increases,
It will function as a high-performance volatile memory. A memory having a tunneling insulating film thickness of 7 nm or more described in the section of the prior art uses Fowler-Nordheim (FN) tunneling, whereas a memory having a film thickness of 3 nm or less can directly use tunneling. .

The volatile memory having such a structure enables signals to be transferred to the floating gate 305 at high speed and at a low voltage, and is advantageous from the viewpoint of suppressing a short channel effect and miniaturizing elements. . That is, the storage node
A semiconductor memory in which a (floating gate) is arranged immediately below a control gate can have a smaller cell area than a DRAM, and achieve volatile operation at high speed and low voltage by making the tunnel insulating film 3 nm or less. Can be. However, when a volatile memory is configured by reducing the thickness of the tunnel insulating film as described above, the charge retention ability is significantly reduced. This point will be described with reference to FIGS. 7 (a3) and (b3) described above. In the figure, when the thickness of the tunnel insulating film is 3 nm or less, the potential rise of the floating gate 305 is observed due to the writing of the signal charge. Cannot flow into the semiconductor substrate 301. Although depending on the signal charge amount, there is generally a time constant of about 100 msec to 100 sec.
On the other hand, at the point B, since no built-in potential exists, the signal charge quickly flows into the source region (or the drain), and the stored signal is lost.

The present invention has been made in view of the above circumstances, and realizes high-speed, low-voltage volatile operation and the like while maintaining sufficient charge retention for practical use by setting the thickness of the tunnel insulating film to 3 nm or less. The challenge is to realize the ability.

[0013]

According to the present invention, a semiconductor substrate, a source region and a drain region formed separately from each other near the surface of the semiconductor substrate, and And a gate electrode formed by stacking a floating gate, a block insulating film, and a control gate in this order on the semiconductor substrate with a tunneling insulating film interposed therebetween, and located under the gate electrode. A semiconductor memory device is provided, wherein the thickness of the tunneling insulating film is 3 nm or less, and the source region and the drain region are formed so as not to include a region immediately below the gate electrode.

According to the present invention, the end of the gate electrode and the end of the source / drain region are spaced apart from each other by a predetermined distance, so that the outflow of charges from the floating gate can be effectively prevented. Note that the semiconductor memory device is
For example, by using a configuration in which side wall insulating films are provided on both sides of a gate electrode, stable production can be achieved.

According to the present invention, a semiconductor substrate and the semiconductor substrate are provided.
A source region and a source region formed separately near the surface of the conductive substrate.
And the drain region, and the source region and the drain region.
And tunneling on the semiconductor substrate.
Floating gate, blow
A gate insulating film and a control gate are stacked in this order.
A gate electrode in a gate length direction of the gate electrode.
Thickness of the tunneling insulating film in the portion, the gate
The tunneling interruption at the center of the electrode in the gate length direction
The thickness of the edge film is d _TwoThen, d_TwoIs less than 3 nm
Semiconductor memory device characterized by 1.5 to 5 times
Is provided.

According to the present invention, the thickness of the tunneling insulating film at the end portion in the gate length direction of the gate electrode is formed to be thicker than the thickness at the central portion. Can be prevented.

In this semiconductor memory device, the source / drain region may be formed so as to include a region immediately below the gate electrode. That is, at the end of the gate electrode, the source / drain region and the gate electrode may be configured to overlap. In this case, the film thickness of the tunnel insulating film in the portion which is at least the overlapping with the d _1, it is preferable to form the thick film.

According to the present invention, there is also provided a method of manufacturing a semiconductor memory device, comprising the steps of: forming a floating gate on a semiconductor substrate via a tunneling insulating film having a thickness of 3 nm or less;
A method for manufacturing a semiconductor memory device, comprising: stacking a block insulating film and a control gate in this order to form a gate electrode, and then thermally oxidizing the tunnel insulating film by a heat treatment at 600 to 900 ° C. Provided.

According to this manufacturing method, the thickness of the tunnel insulating film can be selectively increased at the end of the gate electrode, and the semiconductor memory device can be manufactured stably.

Further, according to the present invention, in the readout circuit of the semiconductor memory device, the drain region of the semiconductor memory device and the precharge transistor are connected by a wire, and one end of the wire is grounded. A reading circuit of a semiconductor memory device, wherein a capacitor is connected. A configuration in which a sense amplifier is further connected to the wiring may be employed. According to the present invention, it is possible to accurately read out the charges in the floating gate of the semiconductor memory device according to the present invention.

Further, according to the present invention, the semiconductor memory device
Reading method of semiconductor memory device using readout circuit
A source region and a control region of the semiconductor memory device.
After grounding the control gate, connect the precharge transistor
By driving the power supply, the capacitor₀To pre
Charge, then turn off the precharge transistor
After setting the state, a voltage is applied to the control gate,
Flowing drain current I _DDue to floating gate
Method of reading out semiconductor memory device that reads out electric charges
Law is provided. According to the present invention, the present invention provides
Reading charge in floating gate of semiconductor memory device
Dispensing can be performed accurately.

[0022]

(First Embodiment) FIG. 1A shows an example of a semiconductor memory according to the present invention.

A tunnel insulating film made of a silicon oxide film having an average film thickness and a maximum film thickness in a range of 0.5 nm to 3 nm is formed on a semiconductor substrate 101 made of silicon into which boron is introduced at about 10 ¹⁵ to 10 ¹⁹ cm ^-3. 104 are formed. On the tunnel insulating film 104, a floating type of polycrystalline silicon having a thickness of about 10 to 1000 nm into which impurities of a conductivity type different from that of the semiconductor substrate 101, for example, arsenic or phosphorus is introduced at about 10 ¹⁹ to 10 ²¹ cm ^-3. A gate 105 is formed. On this floating gate 105, a block insulating film 106 made of a silicon oxide film having a thickness of about 3 to 100 nm is formed. Then, 10 to 1000 nm in which phosphorus or arsenic is introduced at about 10 ¹⁹ to 10 ²¹ cm ^-3 so as to be stacked on the block insulating film 106.
Control gate 10 made of polycrystalline silicon with moderate thickness
7 are formed. The side surface of the gate electrode including the floating gate 105, the block insulating film 106, and the control gate 107 is covered with a sidewall insulating film 114. As described above, in the present embodiment, since the cell structure is formed by the gate electrode formed by stacking the floating gate 105 and the control gate 107 having substantially the same gate length, the cell size is effectively reduced as compared with a DRAM or the like. be able to.

A source region 102 and a drain region 103 are formed near the surface of the semiconductor substrate 101 so as to sandwich a gate electrode formed by stacking the floating gate 105 and the control gate 107. In the source / drain region,
An impurity of a conductivity type different from that of the semiconductor substrate 101 is usually 10 ¹⁸
About 10 ²¹ cm ^{-3 is} introduced. In the source region 102 and the drain region 103, electrodes 108a and 108b made of aluminum, copper, or an alloy thereof are provided. Although not shown in this cross-sectional view, an electrode is also provided on the control gate 108.
On the other hand, the electrode is not in contact with the floating gate 105 and is in an electrically floating state.

Here, the distance between the end of the source region 102 on the gate electrode side and the end of the gate electrode on the source region 102 is x ₁ , the end of the drain region 103 on the gate electrode side and the gate electrode on the drain region 103 side. the distance between the ends is taken as x _2, x ₁ and x ₂ are both, preferably 1 to 2
0 nm, more preferably 2 to 20 nm. With this configuration, it is possible to effectively prevent outflow of retained charges due to gate leakage.

As described above, the semiconductor memory device according to the present embodiment is formed so that the thickness of the tunnel insulating film is 0.5 to 3 nm and the source region and the drain region do not include the region immediately below the gate electrode. ing. Since the thickness of the tunnel insulating film is 0.5 to 3 nm, writing, reading and erasing of signal charges with the floating gate can be performed directly using the tunneling phenomenon. As a result, high-speed writing and reading of signal charges at low voltage can be performed. Further, since the floating gate is separated from the ends of the source region and the drain region by a predetermined distance, the signal charges accumulated in the floating gate are prevented from flowing out to the source region or the drain region, and the accumulation time of the signal charges is reduced. The length can be sufficient for a semiconductor memory device.

Next, a method of manufacturing the semiconductor memory device according to this embodiment will be described.

First, the semiconductor substrate 101 is oxidized in an oxygen atmosphere at a temperature of 650 to 800.degree.
A tunnel insulating film 104 having a thickness of 0.5 to 3 nm is formed on the entire surface.
As another forming method, it can also be formed by irradiating infrared rays in an oxygen atmosphere at 800 to 1100 ° C. for several seconds to several minutes.

Next, a chemical vapor deposition method (hereinafter referred to as CVD
Called law. ), A polycrystalline silicon film (thickness: 10 to 1000 nm) which will later become the floating gate 105 is grown on the tunnel oxide film 104. This polycrystalline silicon film contains an n-type impurity. For example, when phosphorus is used as an n-type impurity, ion implantation of phosphorus is performed, and thereafter,
It is introduced into polycrystalline silicon by a method of activating by heat treatment or a method of diffusing phosphorus from the gas phase into polycrystalline silicon by heat treatment in POCl ₃ .

Thereafter, thermal oxidation is performed in an oxygen atmosphere at an oxidation temperature of 600 to 900 ° C. to form a block insulating film 106 over the entire surface of the polycrystalline silicon film.

Next, polycrystalline silicon which will later become the control gate 107 is grown, and an n-type impurity such as phosphorus or arsenic is introduced.

Next, unnecessary portions of a three-layer structure of polycrystalline silicon / block insulating film / polycrystalline silicon formed on the entire surface of the semiconductor substrate 101 are removed by using a lithography technique and a dry etching technique.
The gate electrode 105, the block insulating film 106, and the control gate 107 are stacked in this order.

Next, after a silicon oxide film having a thickness of 5 to 100 nm is grown on the entire surface of the semiconductor substrate 101 by the CVD method, the silicon oxide film is anisotropically formed by reactive ion etching (hereinafter, appropriately referred to as RIE method). By performing the etching, the side wall insulating film 114 is formed on the side wall of the gate electrode.

Thereafter, arsenic is ion-implanted at a dose of about 10 ¹⁵ to 10 ¹⁶ cm ^-2 at an implantation energy of 1 to 50 keV, and then arsenic is activated by annealing at 800 to 1000 ° C. in a nitrogen atmosphere. Is performed to form a source region 102 and a drain region 103. At this time, since the sidewall insulating film 114 serves as a mask at the time of ion implantation, by appropriately setting the annealing conditions, the end portions of the source / drain regions are separated from the gate electrode formation region, and the gate electrode becomes the source / drain region. And does not overlap. In other words, the structure is such that the end portions of the source / drain regions do not include the region immediately below the gate electrode.

Subsequently, an oxide film is deposited by a CVD method, and a passivation insulating film 109 is formed on the entire surface of the semiconductor substrate 101. As the CVD method for forming the passivation oxide film, a known method such as a normal pressure CVD method, a reduced pressure CVD method, or a plasma CVD method can be used, but a good film quality can be obtained at a relatively low temperature. It is common to use a suitable plasma CVD method. As the passivation film, a known film such as a PSG, BPSG, or SiON film can be used in addition to the silicon oxide film.

Subsequently, by a known photolithography technique, contact holes for forming electrodes reaching the source region 102, the drain region 103 and the control gate 107 are formed by wet etching using HF or gas such as CF ₄ . The electrodes 108a and 108b are formed by a dry etching technique, and are formed by sputtering, vapor deposition, or plating.

Next, the electrical operation of the memory device will be described. FIG. 1B is a diagram showing the C-C of the semiconductor substrate 101 in FIG.
It is an electron energy distribution on the C 'plane. Fig. 1 (b)
A and B in FIG. 1 respectively represent the positions of intersections between the line AA ′ and the line BB ′ in FIG. 1A and the semiconductor surface. At point B, the distance from floating gate 105 is larger than at point A, so A
The energy is slightly higher than the point. Figure 2 shows A-A '
The electron energy distribution along the line BB ′ is shown.

FIGS. 2 (a) and 2 (b) show the energy distribution in the thermal equilibrium state when source voltage = drain voltage = semiconductor substrate voltage = control gate voltage (V _G ) = 0V. In FIG. 2, regions 1 to 5 are a control gate 107, a block insulating film 106,
The floating gate 105 corresponds to the (sidewall insulating film 114 and the tunnel insulating film 104) and the semiconductor substrate 101.

The writing of signal charges to the floating gate is performed as follows. When the control gate 107 goes positive voltage gradually applied, a threshold voltage of V _G is the point A (hereinafter V
_th ), point B, which has higher electron energy than point A, does not invert.
No inversion layer is formed at point A (FIGS. 2 (a2) and (b2)).
Furthermore V _G is increased, the point B is inverted and exceeds the threshold voltage of the point B, to point A is inverted layer is formed, electrons are injected into the floating gate 105 by direct tunneling process (FIG. 2 (a3 ), (B3)). In this case, the inversion layer is also formed at the point B, but the direct tunneling probability is small at the point B because the distance between the semiconductor substrate and the floating gate is large.

Therefore, electron injection into the floating gate mainly occurs in a thin region of the tunnel insulating film represented by point A. Due to the electron injection, the electrostatic energy of the floating gate increases, and the energy of the surface of the semiconductor substrate 101 increases. Eventually, the electron injection ends with the disappearance of the inversion layer. After the desired charge injection is completed, the control gate voltage is returned to 0 V, and the signal charge is held (FIG. 2 (a4), (b)
Four)).

Subsequently, a mechanism for retaining signal charges in the floating gate 105 will be described.

As shown in FIG. 2A4, at point A, the Fermi energy in the floating gate 105 is higher than that in the semiconductor substrate 101, but (Φpn-ΔΦ)
Since the energy of the conduction band of the semiconductor substrate 101 is increased by that much, the signal charge does not leak into the semiconductor substrate 101 immediately. Here, Φpn is the built-in energy of the pn junction, and ΔΦ is the energy increase in the floating gate due to signal accumulation. For example, when ΔΦ = 100 meV, the retention time of the signal charge is about several hundred milliseconds to several tens of seconds.

On the other hand, at the point B, Φpn00 meV, but the signal charge does not leak into the semiconductor substrate 101 due to the large thickness of the tunnel insulating film. Therefore, the semiconductor memory device of the present invention has a signal charge retention time of about several hundred milliseconds to several tens of seconds.

Next, the erasure of the signal charges in the floating gate 105 is performed as follows.

FIG. 3A shows the state after the completion of signal writing. Next, as shown in FIG. 3B, a negative voltage is applied to the control gate 107. As a result, the electrostatic energy of the floating gate 105 increases, so that the signal charge directly tunnels through the tunnel insulating film 104, is absorbed by the semiconductor substrate 101, and the erase operation is realized.

The signal in the floating gate 105 can be read with high sensitivity as follows. FIG. 4A is a circuit configuration diagram for reading and capturing signal charges. A capacitor 111, a precharge transistor 112, and a sense amplifier 113 are connected to the drain side of the memory cell 110. Here, a circuit in which an N-type MOSFET and a resistor are connected in series is used as the sense amplifier 113. Further, the other end of the precharge transistor 112, the voltage V ₀ is applied.

The detection of signal charges is performed in the following sequence. First, V _S = V _G = 0V is set. Next, the capacitor 111 is turned on by turning on the precharge transistor 112.
Is set to V ₀ . After turning off the precharge transistor 112, a constant positive voltage (V _GR ) is applied to the control gate 107 in the memory cell 110. However, when the control gate voltage used for the write operation is V _GW , the condition of V _GW <V _GR <V _th must be satisfied.

If signal charges have been written to the floating gate, no inversion layer is formed on the surface of the semiconductor substrate 101, and no drain current (I _D ) flows. As a result, V _D = V ₀ , and the low level is output to the sense amplifier 113. On the other hand, when no signal charge is written in the floating gate, when V _GR is applied, an inversion layer is induced on the surface of the semiconductor substrate 101, and an electron current ( _IG ) flows to the floating gate 205. At the same time, the drain current (I _D) for voltage V ₀ is applied to the drain 103 also flows. Usually I _D of the order of mA, I _G is because the order of .mu.A, the ratio I _G of I _D reaches about 1000-fold.

The capacitor 111 already precharged
The voltage decreases with time due to _ID . This is shown in FIG. 4 (b). In a state where there is a signal charge in the floating gate (state 1), since _ID = 0, V _D is constant regardless of time, but in a state where there is no signal charge (state 0), V _D
D decreases with time, and at time T ₀ , V _D = 0. As a result, the output of the sense amplifier 113 becomes high level. In this way, even if the amount of charge injected into the floating gate is small, it is amplified 1000 times or more by the drain current,
Highly sensitive signal charge detection is possible.

Actually, the thickness of the floating gate is 2 nm.
The semiconductor memory device having the tunnel insulating film was manufactured. As a result, writing, reading, and erasing of signal charges were performed without any problem at a power supply voltage of 3 V, and a signal holding time of 10 seconds was obtained. In this embodiment, single-crystal silicon is used as the semiconductor substrate 101, but an SOI (Silicon on insulator) substrate can also be used. When α-rays or the like emitted from radioactive atoms contained in a package or the like enter the semiconductor substrate 101, electron-hole pairs are generated, of which electrons are captured by the floating gate and may cause a signal error. However, by using the SOI substrate, such a problem can be avoided and electrons from deep inside the substrate can be prevented from reaching the substrate surface.

In this embodiment, the structure in which the source / drain region and the gate electrode do not overlap is formed by utilizing the side wall insulating film 114. In addition to this method, the floating gate and the control gate are made of different materials. , The above structure can be realized. For example, aluminum or the like used as the control gate, after performing the processing of aluminum / block insulating film / polysilicon three-layered film, performing selective isotropic RIE etching only polysilicon using a gas such as SF ₆ To form a gate electrode.

(Second Embodiment) FIG. 5A shows an example of a semiconductor memory device according to the present embodiment.

A tunnel insulating film 104 made of a silicon oxide film is formed on a semiconductor substrate 101 made of silicon into which boron is introduced at about 10 ¹⁵ to 10 ¹⁹ cm ^-3 . On the tunnel insulating film 104, a floating layer made of polycrystalline silicon having a thickness of about 10 to 1000 nm into which impurities of a conductivity type different from that of the semiconductor substrate 101, for example, arsenic or phosphorus is introduced at about 10 ¹⁹ to 10 ²¹ cm ^-3. A gate 105 is formed. On this floating gate 105, a block insulating film 106 made of a silicon oxide film having a thickness of about 3 to 100 nm is formed.
As stacked on the block insulating film 106, phosphorus or arsenic is introduced about 10 ^{1 9} ~10 ²¹ cm ^-3 10~1000
Control gate made of polycrystalline silicon with thickness of about nm
107 are formed. The side surface of the gate electrode including the floating gate 105, the block insulating film 106, and the control gate 107 is covered with a sidewall insulating film 114. As described above, in the present embodiment, since the cell structure is formed by the gate electrode formed by stacking the floating gate 105 and the control gate 107 having substantially the same gate length, the cell size is effectively reduced as compared with a DRAM or the like. be able to.

The source region 102 and the drain region 103 are formed near the surface of the semiconductor substrate 101 so as to sandwich the gate electrode formed by stacking the floating gate 105 and the control gate 107. In the source / drain region,
An impurity of a conductivity type different from that of the semiconductor substrate 101 is usually 10 ¹⁸
About 10 ²¹ cm ^{-3 is} introduced. In the source region 102 and the drain region 103, electrodes 108a and 108b made of aluminum, copper, or an alloy thereof are provided. Although not shown in this cross-sectional view, an electrode is also provided on the control gate 107.
On the other hand, the electrode is not in contact with the floating gate 105 and is in an electrically floating state.

In the tunnel insulating film according to the present embodiment, the portion in contact with the central portion of the floating gate is thinner than the portion in contact with the peripheral portion of the floating gate. Thereby, the outflow of the retained charges can be effectively prevented.

FIG. 8 is a circuit diagram of the semiconductor memory device shown in FIG.
FIG. 4 is an enlarged view of the vicinity of a contact electrode. As shown in the figure,
Thickness of tunnel insulating film 104 at the end in the gate length direction
To d ₁, The ton at the center of the gate electrode in the gate length direction.
The thickness of the tunnel insulating film 104 is d_TwoThen, d₁Is d_Two
1.5 to 5 times, preferably 2 to 4 times
Is more preferable. As a specific film thickness, for example,
d_TwoIs about 1 to 3 nm, and d₁1.5 to 10 nm, preferably
Preferably, about 1.5 to 5 nm (however, d₁> D_Two).
This ensures high speed and low voltage operation while maintaining
It is possible to more effectively prevent outflow of the stored charges. What
The end in the gate length direction of the gate electrode is, for example, a gate.
The distance from the end face of the gate electrode is 0.2 times the gate electrode length
Within the area of the gate electrode in the gate length direction center
Means a region excluding the end.

The above structure can be manufactured as follows. First, a tunnel insulating film 104 is formed by oxidizing a silicon substrate at about 650 ° C. to 800 ° C. in an oxygen atmosphere. The formation can also be performed by infrared irradiation at 800 ° C. to 1100 ° C. for several seconds to several minutes in an oxygen atmosphere. Next, CVD
The polycrystalline silicon is grown by the method. After this, POCl
_{In step 3} , phosphorus is introduced into the polycrystalline silicon. Phosphorus or arsenic can also be introduced by ion implantation. Thereafter, thermal oxidation is performed in an oxygen atmosphere at 600 ° C. to 900 ° C. to form the block insulating film 106. Next, polycrystalline silicon is grown by the CVD method, and phosphorus or arsenic is introduced.

Next, using lithography technology and dry etching technology, polysilicon / block insulating film /
The polysilicon three-layer film is processed, and the floating gate 105 and the control gate 107 are formed. Then, arsenic or phosphorus is implanted at an energy of 1 to 50 keV of about 10 ¹⁵ to 10 ¹⁶ cm ⁻³ , and annealing is performed at 800 to 1000 ° C. in a nitrogen atmosphere to form the source 102 and the drain 103. During this annealing, arsenic or phosphorus in the source 102 and the drain 103 diffuses in the lateral direction, so that an overlapping structure of the source 102 and the drain 103 and the floating gate 105 is formed. Thereafter, 600 ° C to 900 ° C, preferably 70 ° C
Oxidation in an oxygen atmosphere at 0 to 850 ° C. increases the thickness of the tunnel insulating film at the end of the gate electrode. At this time, part of the supplied oxygen diffuses from the end of the floating gate into the tunnel insulating film, and the semiconductor substrate 101
Alternatively, it reacts with silicon atoms in the floating gate 105 to grow a silicon oxide film. When the oxidation temperature is relatively high, oxygen reaches the center of the gate because the viscosity of the oxide film is low.However, when the oxidation temperature is low, the stress in the oxide film increases because the viscosity of the oxide film increases and the oxygen Diffusion is suppressed. Therefore, the oxygen diffused from the floating gate end into the tunnel insulating film below the floating gate is consumed in growing the oxide film near the floating gate end, and does not diffuse below the center of the floating gate. Also, due to the presence of arsenic or phosphorus in the source 102 or the drain 103,
Above, accelerated oxidation also occurs. As a result, the tunnel insulating film 104 having a shape as shown in FIG. 5A can be formed. Thereafter, an oxide film is deposited by a CVD method, and a passivation insulating film 109 is formed. By then dry etching technique using the wet etching or CF ₄ or the like of the gas using HF, forming electrode 108a, a contact hole at a position to form a b, sputtering, vapor deposition or by plating, the electrode 108a, the b I do.

Next, the electrical operation of the present memory element will be described. FIG. 5B shows an electron energy distribution on the surface of the half-substrate 101 in FIG. 5A. In addition, A, B in FIG.
Represents the position of the intersection between the line AA ′ and line BB ′ in FIG. 5 (a) and the semiconductor surface. At point B, the distance from the floating gate 105 is larger than at point A, so the energy is slightly higher than at point A. FIG. 7 shows the electron energy distribution along the line AA ′ and the line BB ′. The electron energy distribution along the line A-A 'is shown in FIGS. 2 (a1), (a2), (a3), (a4), respectively.
The electron energy distribution along the line BB ′ is the same as that shown in FIGS. 2 (b1), (b2), (b3) and (b4), respectively. However
Regions (b1) to (b4) correspond to the tunnel insulating film 104.
Therefore, the method of writing, erasing, and reading signal charges is the same as in the first embodiment. This embodiment is different from the first embodiment in that the source / drain and the floating gate may overlap each other, so that there is an advantage that the cell area can be reduced. In this embodiment,
Writing, reading, and erasing of signal charges were performed without any problem at a power supply voltage of 3 V, and a signal holding time of 10 seconds was obtained.

[0060]

As described above, according to the semiconductor memory of the present invention, high-speed and low-voltage volatile operation can be realized by setting the thickness of the tunnel insulating film to 3 nm or less.
Practically sufficient charge holding ability can be realized. Also, since the storage node can be formed under the control gate and the thickness of the tunneling insulating film can be reduced, the DRAM (Dynamic Random
Cell area can be reduced as compared with ccess memory). Also,
Since the memory cell itself has a current amplifying function, there is an advantage that it is possible to detect the presence or absence of signal charges with high sensitivity.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure and an electron energy distribution of a semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing a potential distribution in the depth direction at points A and B at the time of writing signal charges in the semiconductor memory device according to the present invention.

FIG. 3 is a diagram showing a potential distribution in a depth direction at a point A when a signal charge is erased in the semiconductor memory device according to the present invention.

FIG. 4 is a diagram showing a signal charge reading circuit (a) according to the present invention and a time change (b) of a drain voltage at the time of reading.

FIG. 5 is a diagram showing a cross-sectional structure and an electron energy distribution of a semiconductor memory device according to the present invention.

FIG. 6 is a diagram showing a cross-sectional structure and electron energy distribution of a conventional nonvolatile semiconductor memory.

FIG. 7 is a diagram showing a potential distribution in a depth direction at points A and B at the time of signal charge writing in a conventional nonvolatile semiconductor memory.

8 is an enlarged view near the gate electrode of the semiconductor memory device shown in FIG.

[Explanation of symbols]

 101,301 Semiconductor substrate 102,302 Source region 103,303 Drain 104,304 Tunneling insulating film 105,305 Floating gate 106,306 Block insulating film 107,307 Control gate 108a, b Electrode 109,309 Passivation insulating film 110 Memory cell 111 Capacitor 112 Precharge transistor 113 Sense amplifier 114 Side wall insulating film 308a, b electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/10 481 F term (Reference) 5B025 AA03 AB01 AC01 AD05 AD11 AE05 AE07 AE08 5F001 AA09 AA21 AA62 AB08 AD12 AE02 AE08 AG12 AG22 5F083 EP02 EP14 EP15 EP23 EP42 EP43 EP45 ER09 ER19 ER21 ER30 GA01 GA05 GA09 JA36 JA37 LA03 LA09 PR12 PR13 PR36 5F101 BA03 BA24 BA35 BB05 BD02 BE05 BE07 BH04 BH09

Claims (7)

[Claims] 1. A semiconductor substrate, a source region and a drain region formed in the vicinity of a surface of the semiconductor substrate and separated from each other, and disposed between the source region and the drain region, and a tunneling insulator is provided on the semiconductor substrate. And a gate electrode formed by laminating a floating gate, a block insulating film, and a control gate in this order, wherein the thickness of the tunneling insulating film located below the gate electrode is 3 nm or less. Wherein the source region and the drain region are formed so as not to include a region immediately below the gate electrode. 2. The semiconductor memory device according to claim 1, wherein a distance between a gate electrode side end of the source region and a source region side end of the gate electrode, and a gate electrode side end of the drain region and the gate electrode. Wherein the distance between the end portions on the drain region side is 1 to 20 nm. 3. A semiconductor substrate and a vicinity of a surface of the semiconductor substrate.
And drain regions formed apart from each other
And the source region and the drain region.
Formed on the semiconductor substrate via a tunneling insulating film.
Floating gate, block insulating film and
A gate electrode in which control gates are stacked in this order.
And the gate at the end of the gate electrode in the gate length direction.
The thickness of the tunneling insulating film is d ₁The gate electrode gate
Thickness of the tunneling insulating film in the central part in the length direction
To d_TwoThen, d_TwoIs 3 nm or less and d₁Is d_Two
Semiconductor storage device characterized by 1.5 to 5 times as large as
Place. 4. The method for manufacturing a semiconductor memory device according to claim 3, wherein a floating gate, a block insulating film, and a control gate are formed in this order on a semiconductor substrate via a tunneling insulating film having a thickness of 3 nm or less. A method for manufacturing a semiconductor memory device, comprising: laminating and forming a gate electrode; and thermally oxidizing the tunnel insulating film by a heat treatment at 600 to 900 ° C. 5. The read circuit of a semiconductor memory device according to claim 1, wherein a drain region of the semiconductor memory device and a precharge transistor are connected by a wiring, and one end of the read region is grounded. A readout circuit for a semiconductor memory device, wherein the read capacitor is connected. 6. The readout circuit of a semiconductor memory device according to claim 5, wherein a sense amplifier is further connected to said wiring. 7. A method for reading a semiconductor memory device using a read circuit of a semiconductor memory device according to claim 5, wherein a source region and a control gate of the semiconductor memory device are grounded and then precharged. By driving the transistor, the capacitor is precharged to the power supply V ₀ , and then the precharge transistor is turned off, then a voltage is applied to the control gate, and the drain current _ID flowing at this time causes the floating gate to have a low voltage. A reading method of a semiconductor memory device which reads charges.