JP3402212B2 - Digital data compression method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data compression method for variable length coding coefficients obtained by transform coding such as DCT (discrete cosine transform).

[0002]

2. Description of the Related Art As a method of compressing the information amount of a digitized image signal, a method of combining transform coding and variable length coding is known. Since image signals generally have high correlation, energy can be concentrated by using transform coding such as orthogonal transform. DCT is often used as the transform coding, whereby the energy is concentrated on the DC component on the frequency axis, and the energy decreases as the frequency increases. For this reason, the coefficient corresponding to the component having a high frequency has a small value and has a high probability of becoming zero.

Further, in order to further compress the amount of information, weighting and quantization of coefficients are performed for each frequency component. This further increases the probability that the high frequency component will be zero. Coefficients obtained by transform coding using such a property are arranged in order from those corresponding to low frequency components to those corresponding to high frequency components, and the number of consecutive 0s (referred to as "zero run"). 2) and a coefficient value other than zero are combined to generate a codeword according to the appearance probability thereof (two-dimensional Huffman coding, which is a kind of entropy coding).

[0004]

By the way, in order to ensure the accuracy of the DCT operation, the number of bits in the middle of the operation is increased to ensure the accuracy, and when the final conversion coefficient is obtained,
Rounding processing such as rounding and truncation is generally performed so that the required number of bits is reached.
Although the error caused by CT conversion and inverse conversion can be reduced, for example, 0.5 is rounded up to 1,
The number of code words increases without the zero run becoming too large. In addition, since a code word having a longer code length is generally assigned to a coefficient having a larger value, the length of the code word itself also becomes longer.

When the total code amount increases due to a longer code length or an increase in the number of code words, it is necessary to increase the width of the quantization step and increase the compression rate in order to keep the predetermined code amount. However, there is a problem that the image quality is deteriorated.

On the other hand, if rounding down is performed instead of rounding off,
Such a problem does not occur. For example, 0.5 is rounded to 0, so that the zero run becomes long and the number of code words is reduced, and the value is rounded to the smaller value, and the code length becomes shorter.
Therefore, since the code amount is reduced as a whole, if the code amount is the same, the compression rate can be reduced, and the deterioration of image quality due to compression can be suppressed. However, since the data is rounded down at the time of calculation, it is more DC than the case of rounding off.
There is a problem that a calculation error due to the T conversion and the inverse conversion becomes large.

The present invention has been made in view of the above-mentioned points, and provides a digital data compression method capable of suppressing a calculation error of transform coding to a minimum and reducing signal deterioration due to compression. The purpose is to

[0008]

In order to achieve the above object, the invention according to claim 1 is a variable length coding of a coefficient obtained by transform coding of digital data based on the number of appearances of 0 and the coefficient value. A method of compressing digital data according to claim 1, wherein the coefficient value obtained by the transform coding is rounded to a predetermined number of bits by rounding.
For at least a part of the coefficients obtained by the step and the rounding process, it is determined whether or not the absolute value is smaller than a preset threshold value larger than 0. If the absolute value is smaller than the threshold value, the coefficient is determined. It is characterized by comprising a second step of performing coring processing for replacing the value of 0 with 0 and a third step of performing variable length coding on the data after the coring processing.

According to a second aspect of the present invention, in the method of compressing digital data according to the first aspect, the coring process is performed on one of the coefficients corresponding to a high frequency component. Characterize.

According to a third aspect of the present invention, in the method of compressing digital data according to the first aspect, the coefficient is divided into a plurality of groups in order from a component having a low frequency to a component having a high frequency, and each group is divided into a plurality of groups. The threshold is set, the coring process is executed, and the threshold of the group corresponding to the high frequency component is equal to or larger than the threshold of the group corresponding to the low frequency component, and at least two thresholds have different values. It is characterized by setting.

According to a fourth aspect of the present invention, in the digital data compression method according to the first aspect, the threshold value is set so that the code amount generated in the code amount control unit does not exceed a predetermined code amount. Characterize.

According to a fifth aspect of the present invention, in the digital data compression method according to the first aspect, the coring process is performed so that the code amount generated in the code amount control unit does not exceed a predetermined code amount. It is characterized in that the range of the coefficient to be set is set.

According to a sixth aspect of the present invention, in the method of compressing digital data according to the first aspect, the coefficient is divided into a plurality of groups in order from a component having a low frequency to a component having a high frequency, and each group is divided into a plurality of groups. The coring process is executed by independently setting the threshold value, and the threshold value is changed so that the code amount generated in the code amount control unit does not exceed a predetermined code amount. The feature is that the higher the group, the larger the setting.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing the arrangement of an image signal recording / reproducing apparatus to which the digital data compression method of the present invention is applied. The recording system of this apparatus includes a DCT arithmetic circuit 1 for performing DCT arithmetic and a DT obtained by the DCT arithmetic.
Rounding circuit 2 for rounding off CT coefficients
A zigzag scan (ZZS) circuit 3 for arranging the DCT coefficients in order from the one having a lower frequency component, a coring circuit 4 for performing a coring process described later, and a code amount corresponding to a predetermined number of DCT blocks. A code amount control circuit 5 for determining a quantization level so that the quantization level is within a predetermined code amount, a quantization circuit 6 for performing a quantization process according to the quantization level, and a zero run (consecutive 0 Number) and a run length coding (RLC) circuit 7 for converting into a set of coefficient values other than 0, a variable length coding (VLC) circuit 8 for performing variable length coding by a two-dimensional Huffman code,
AC (AC) component data input from the variable length encoding circuit 8 and DC input from the zigzag scan circuit 3.
A recording signal processing circuit 9 that adds an error correction code, a synchronization signal, ID information, additional information, etc. to the data of the (DC) component, performs modulation, and records the modulated signal on the recording medium 100.
It has and.

The reproduction system also includes a reproduction signal processing circuit 1 for demodulating a signal reproduced from the recording medium 100 to perform error correction and the like.
1 and a variable length decoding (VLD) circuit 12 for converting the output data of the reproduction signal processing circuit 11 into a set of zero run and coefficient value.
, And insert 0 as many as necessary according to zero run, and the original D
A run-length decoding (RLD) circuit 13 that restores a CT coefficient sequence and an inverse quantization circuit 1 that inversely quantizes DCT coefficients
4, an inverse zigzag scan (inverse ZZS) circuit 15 for returning the DCT coefficient sequence to the original 8 × 8 array, an inverse DCT operation circuit 16 for performing an inverse DCT operation, and image data obtained by the inverse DCT operation. And a rounding circuit 17 for performing rounding processing.

An 8-bit digital image signal is input to the DCT arithmetic circuit 1 of the recording system in units of small blocks of horizontal 8 pixels × vertical 8 pixels (hereinafter referred to as “DCT block”) on the screen, and the DCT arithmetic circuit 1 Performs DCT operation in units of this DCT block, and the coefficient value obtained as a result is set to 1
Output as 6-bit digital data. The rounding circuit 2 rounds the 16-bit AC component digital data to round to 10-bit digital data, and rounds the 16-bit DC component digital data to 9-bit digital data.

The "round-off" processing of digital data in this specification may include at least round-up processing. If the input data is greater than or equal to a predetermined threshold value, the digital data is rounded up, and in other cases, it is rounded down. Say. As an example, a process of rounding 5-bit binary complement data (input data) into a 3-bit binary complement code will be described with reference to Table 1. In the numerical values shown in Table 1, the most significant bit is the sign bit. Also, (li
The numerical value with m) means that the limiter is applied because the value exceeds the range by rounding up.

[Table 1]

Table 1 shows two types of truncation processing for comparison. The truncation 1 is processing of simply truncating the lower 2 bits. This eliminates the need for a special circuit, but has the disadvantage that the operation becomes asymmetric between positive and negative. The truncation 2 is a modification of the truncation 1 to perform truncation so that positive and negative are symmetrical. For example, in the case of a negative value, the rounding processing is performed by once converting the value into an absolute value, truncating the lower 2 bits, and returning to the negative value again.

Rounding 1 in Table 1 corresponds to so-called rounding in decimal numbers, and when it is considered that there is a decimal point in the second and third bits from the bottom of the 5-bit input data, the first decimal point is This is equivalent to the process of rounding off by place. Rounding 2 is a rounding up and rounding down threshold in rounding 1 changed to a direction in which there is a high possibility of being rounded down. That is, in rounding 1, 0.25, 0.50, 0.75 are rounded to 0, 1, 1 respectively, while in rounding 2, they are rounded to 0, 0, 1 respectively. Rounding 2 rounds 1
Since the value is rounded toward a smaller value, the result of requantization is smaller, and the probability of becoming 0 is higher, which is effective in reducing the code amount.

As described above, “rounding off” in the present specification
Rounds up when input data is above a predetermined threshold,
In other cases, it means a process of rounding down. Note that Table 1 shows an example of rounding signed 5-bit data into signed 2-bit data. However, when rounding signed 16-bit data into signed 10-bit data, "rounding off" is similarly performed. It goes without saying that the processing can be performed, and the threshold value for determining rounding up or rounding down can be set to various values.

As shown in FIG. 2, the zigzag scanning circuit 3 supplies the DC component (No. 0) of the DCT coefficient to the recording signal processing circuit 9, and the AC component of the DCT coefficient is the lowest frequency component ( The signal is supplied to the coring circuit 4 as a DCT coefficient sequence sequentially arranged from the highest component (No. 63) to the highest component (No. 63).

As shown in FIG. 4A, the coring circuit 4 includes preset N1th to 63rd DCs.
D included in the target area with the T coefficient as the target area (hereinafter, "N1" is referred to as "area designation parameter")
The absolute value of the CT coefficient D (i) (i = N1 to 63) is calculated,
It is determined whether or not the absolute value is smaller than a preset threshold TH1 which is larger than 0. When | D (i) | <TH1, the DCT coefficient D (i) is replaced with “0” and output. , | D (i) | ≧ TH1, a process of outputting the DCT coefficient D (i) as it is (hereinafter referred to as “coring process”) is performed.

The code amount control circuit 5 has a code amount CA in a code amount control unit composed of a predetermined number of DCT blocks.
So as not to exceed the predetermined code amount CAX (however, so that the value becomes as close as possible to the predetermined code amount CAX), the quantization level of the DCT block included in the code amount control unit is determined and the quantization control is performed. Quantization circuit 6 as signal Q
Supply to. The quantization circuit 6 quantizes the DCT coefficient supplied from the coring circuit 4 in accordance with the quantization level designated by the quantization control signal Q.

The run length encoding circuit 7 converts the quantized DCT coefficient sequence into a set of zero run and the value of the DCT coefficient immediately after that, and the variable length encoding circuit 8 converts the zero run and D
A set of CT coefficient values is variable length coded by a two-dimensional Huffman code. The recording signal processing circuit 9 includes a variable length coding circuit 8
An AC (alternating current) component data input from the device and a DC (direct current) component data input from the zigzag scan circuit 3 are added with an error correction code, a synchronizing signal, ID information, additional information, etc., and modulated. , The modulated signal to the recording medium 1
The process of recording in 00 is performed.

The reproduction processing circuit 11 demodulates the signal reproduced from the recording medium 100 to perform error correction and the like, and supplies the 9-bit DC component directly to the inverse zigzag scanning circuit 15.
The AC component data is supplied to the variable length decoding circuit 12.
The variable length decoding circuit 12 converts the output data of the reproduction signal processing circuit 11 into a set of zero run and coefficient value, and the run length decoding circuit 13 inserts a necessary number of 0s according to the zero run, and Restore the DCT coefficient sequence. Inverse quantization circuit 1
4 is a DC input from the run length decoding circuit 13
The T coefficient is inversely quantized and input to the inverse zigzag scan circuit 15 as 10-bit data. The inverse zigzag scan circuit 15 performs processing for returning the DCT coefficient sequence to the original 8 × 8 array, and the inverse DCT operation circuit 16 performs inverse DCT operation with 16-bit operation accuracy and outputs 16-bit image data. To do. The rounding circuit 17 rounds the 16-bit image data obtained by the inverse DCT operation to 8 bits and outputs the original digital image signal.

Although it has been described that the DCT coefficient is converted into the absolute value in the coring circuit 4, the DCT coefficient may be converted into the absolute value in the rounding circuit 2 first. That is, the rounding circuit 2
Converts 16-bit signed data into 1-bit sign bit and 15-bit absolute value data, and then
Round 5 bit absolute value data to 9 bit absolute value data. To the zigzag scan circuit 3, AC data consisting of a total of 10 bits including a sign bit of 1 bit and absolute value data of 9 bits is output. In this case, the absolute value conversion process in the coring circuit 4 becomes unnecessary.

As described above, in this embodiment, the rounding circuit 2 rounds the 16-bit DCT coefficient to 10-bit data (DC component is 9 bits) by rounding, and the coring circuit 4 performs coring. It is determined whether or not the absolute value | D (i) | of the DCT coefficient D (i) (i = N1 to 63) of the target area is smaller than the threshold value TH1, and when | D (i) | <TH1, Since the coring process for replacing the DCT coefficient with "0" is performed, the calculation error due to the rounding process can be minimized and the zero run can be lengthened. As a result, the number of code words is reduced, and the overall code amount can be reduced. Therefore, the code amount of the code amount control unit can be set to a predetermined code amount or less with a smaller compression rate, and the image quality associated with compression can be reduced. Deterioration can be reduced.

Further, since the area to be subjected to the coring processing is the high frequency area of the AC component (the area from the N1th to the 63rd areas), the influence of the coring processing (the deterioration of the image quality) is visually confirmed. You can make it almost unnoticeable.

(Second Embodiment) In the present embodiment, the coring circuit 4 of FIG. 1 is replaced with the coring circuit 4a of FIG.
The coring circuit 4a has four thresholds TH0, TH1, and TH.
2, TH3 and area designation parameters N1, N2, N3
Is to be entered. Here, the four thresholds are 0 <TH0 ≦ TH1 ≦ TH2 ≦ TH3 (however, 4
All three thresholds are equal (TH0 = TH1 = TH2 = T
H3) never set, in other words, at least 2
Three thresholds have different values) and the three area designation parameters are 0 <N1 <N2 <N3 <64
Have a relationship.

The coring circuit 4a performs the following processing. By the area designation parameters N1, N2, N3,
As shown in FIG. 4B, the DCT coefficient of the AC component is divided into four groups G0 to G3. That is, group G
0 consists of DCT coefficients D (i) (i = 1 to N1-1), and group G1 includes DCT coefficients D (i) (i = N1 to N1).
N2-1), the group G2 has a DCT coefficient D
(I) (i = N2 to N3-1), and includes group G3
Consists of DCT coefficients D (i) (i = N3 to 63).
The threshold value TH0 is set for each of the groups G0 to G3.
~ TH3 is applied to perform coring processing.

That is, 1) It is determined whether or not the absolute value of the DCT coefficient D (i) (i = 1 to N1-1) of the group G0 is smaller than the threshold value TH0. 2) DCT coefficient D (i) (i = N1 to N2-1) of group G1 is discriminated whether or not its absolute value is smaller than threshold TH1. Replace the coefficient with "0",
3) DCT coefficient D (i) of group G2 (i = N2 to N
For 3-1), it is determined whether or not the absolute value is smaller than the threshold value TH2, and when it is smaller, the DCT coefficient is replaced with "0", and 4) the DCT coefficient D of the group G3.
For (i) (i = N3 to 63), it is determined whether or not the absolute value is smaller than the threshold value TH3, and when it is smaller, a process of replacing the DCT coefficient with "0" is performed.

Except for the above points, it is the same as the first embodiment. According to this embodiment, the thresholds TH0 to TH3 applied to the groups G0 to G3 are 0 <TH0 ≦ TH1.
Since the relationship of ≦ TH2 ≦ TH3 is satisfied and at least two threshold values have different values, a lower threshold value is applied to a component having a lower frequency. As a result, in the low frequency region where the visual influence is large, the number of DCT coefficients replaced by “0” is small, while in the high frequency region where the visual influence is small,
It can be easily replaced with "0", the number of zero runs can be increased, and the generated code amount can be suppressed.

(Third Embodiment) In the present embodiment, the coring circuit 4 and the code amount control circuit 5 of FIG. 1 are replaced with a coring circuit 4b and a code amount control circuit 5a shown in FIG. 5, respectively. is there.

The code amount control circuit 5a includes three coring circuits 41, 42 and 43, and three code amount control circuits 51,
52 and 53 and a quantization level / threshold value selection circuit 55. The coring circuits 41, 42 and 43 have area designating parameters N1 and different threshold values t1 and t, respectively.
2, t3, and the threshold values t1 to t
3 is also input to the quantization level / threshold value selection circuit 55.

The coring circuits 41 to 43 perform the same coring processing as the coring circuit 4 in the first embodiment using different threshold values t1 to t3 and the same area designating parameter N1, and the processed DCT. The coefficients are supplied to the code amount control circuits 51 to 53, respectively. The code amount control circuits 51 to 53, like the code amount control circuit 5 of FIG. 1, prevent the code amount CA of the code amount control unit consisting of a predetermined number of DCT blocks from exceeding the predetermined code amount CAX.
The quantization level of the DCT block included in the code amount control unit is determined, and this is supplied to the quantization level / threshold selection circuit 55 as the quantization control signals Q1 to Q3.

The quantization level / threshold value selection circuit 55 includes a quantization control signal (Q1, Q2 or Q3) having the smallest quantization level and a threshold value (t) corresponding to the quantization control signal.
1, t2 or t3) are supplied to the quantizing circuit 6 and the coring circuit 4b as the selective quantizing control signal QSEL and the selective threshold THSEL, respectively.

The coring circuit 4b has a selection threshold value THSE.
Coring processing similar to the coring circuit 4 of FIG. 1 (processing in which the threshold TH1 is replaced with THSEL in the first embodiment) is performed according to L and the area designation parameter N1.
The quantization circuit 6 performs a quantization process using the quantization control signal QSEL.

Except for the above points, it is the same as the first embodiment. As described above, in the present embodiment, different threshold values t1 to t1.
Using t3, the quantization level is determined so that the code amount CA of the code amount control unit does not exceed the predetermined code amount CAX, and the threshold value with the smallest quantization level (small quantization step and small quantization error) is selected. Since this is done, the optimum coring process can be performed within the range that satisfies the condition of the predetermined code amount CAX.

(Fourth Embodiment) In the present embodiment, the coring circuit 4 and the code amount control circuit 5 of FIG. 1 are replaced with a coring circuit 4c and a code amount control circuit 5b shown in FIG. 6, respectively. is there.

The code amount control circuit 5b includes three coring circuits 61, 62 and 63 and three code amount control circuits 71,
72, 73 and a quantization level / threshold value selection circuit 75, and the coring circuits 41, 42, 43 respectively have different area designation parameters n1, n2, n3,
The same threshold value TH1 is supplied, and the area designation parameters n1 to n3 are also input to the quantization level / threshold value selection circuit 75.

The coring circuits 61 to 63 perform the same coring processing as the coring circuit 4 in the first embodiment using different area designation parameters n1 to n3 and the same threshold value TH1, and the DCT after the processing is performed. The coefficients are supplied to the code amount control circuits 71 to 73, respectively. The code amount control circuits 71 to 73, like the code amount control circuit 5 of FIG. 1, prevent the code amount CA of the code amount control unit including a predetermined number of DCT blocks from exceeding the predetermined code amount CAX. The quantization level of the DCT block included in the code amount control unit is determined, and this is used as the quantization control signals Q1 to Q3.
Is supplied to the quantization level / threshold value selection circuit 75.

The quantization level / threshold value selection circuit 75 has a quantization control signal (Q1, Q2 or Q3) having the smallest quantization level and an area designation parameter (n1, n2 or n3) corresponding to the quantization control signal. And are supplied to the quantization circuit 6 and the coring circuit 4c as the selected quantization control signal QSEL and the selected area designating parameter nSEL, respectively.

The coring circuit 4c uses the selected area designating parameter nSEL and the threshold value TH1 to perform the same coring processing as the coring circuit 4 of FIG. 1 (processing in which the area designating parameter N1 is replaced by nSEL in the first embodiment). ), The quantization circuit 6 determines the quantization control signal QSEL.
Quantization processing using is performed.

Except for the above points, it is the same as the first embodiment.

As described above, in this embodiment, the code amount C of the code amount control unit is used by using different area specifying parameters.
Since the quantization level is determined so that A does not exceed the predetermined code amount CAX, and the area designation parameter having the smallest quantization level (small quantization step and small quantization error) is selected, the predetermined code amount CAX is set. It is possible to set the optimum target area of the coring process within the range satisfying the condition (1) and perform the coring process while suppressing the visual influence to the minimum.

(Fifth Embodiment) This embodiment is basically a combination of the second embodiment and the third embodiment, and has a coring circuit 4 and a code amount control circuit 5 of FIG. In place of the coring circuit 4d and the code amount control circuit 5c shown in FIG. 7, respectively.

The code amount control circuit 5c includes three coring circuits 81, 82 and 83, three code amount control circuits 91,
92 and 93 and a quantization level / threshold value selection circuit 95, and the coring circuits 81, 82 and 83 respectively have different area designation parameters N1, N2 and N3.
Different threshold vectors THG1, THG2, THG3, T
HG4 and a threshold vector T
HG1 to THG3 are quantization level / threshold value selection circuits 95.
Is also configured to be input. Similar to the second embodiment, the four threshold values are 0 <TH0 ≦ TH1 ≦ TH2.
≤TH3 (However, all four thresholds are equal (TH0
= TH1 = TH2 = TH3) they are not set, in other words, at least two threshold values have different values), and the three area designation parameters are 0 <N
It has a relationship of 1 <N2 <N3 <64.

The threshold vectors THG1 to THG4 have thresholds TH0, TH1, TH2 and TH3 corresponding to the four groups G0 to G3 (see FIG. 4B) divided by the area designation parameters N1 to N3 as elements. Is a vector that is (TH0, TH1, TH2, TH
3) is displayed. Each threshold vector is set as follows in decimal notation, for example. THG1 = (TH0, TH1, TH2, TH3) =
(1,1,1,2) THG2 = (TH0, TH1, TH2, TH3) =
(1,1,2,3) THG3 = (TH0, TH1, TH2, TH3) =
(1, 2, 3, 6) THG4 = (TH0, TH1, TH2, TH3) =
(2, 3, 5, 9)

Here, the difference between the respective vectors is as follows, and it is set so that the higher the frequency is, the larger the threshold change amount becomes. That is, each group G0
The change amount of the threshold value corresponding to G3 is set to ΔTH0, ΔTH1, Δ
If TH2 and ΔTH3, then ΔTH0 ≦ ΔTH1 ≦ ΔT
It is set so that H2 ≦ ΔTH3. THG2-THG1 = (ΔTH0, ΔTH1, ΔTH2, ΔTH3) = (0,0,1,1) THG3-THG2 = (ΔTH0, ΔTH1, ΔTH2, ΔTH3) = (0,1,1,3) THG4-THG3 = (ΔTH0, ΔTH1, ΔTH2, ΔTH3) = (1, 1, 2, 3)

Each of the coring circuits 81 to 83 performs the same coring process as that of the coring circuit 4a in the second embodiment using the thresholds TH0 to TH3 for each of the groups G0 to G3, and after the processing. The DCT coefficients are supplied to the code amount control circuits 91 to 93, respectively. Like the code amount control circuit 5 of FIG. 1, the code amount control circuits 91 to 93 prevent the code amount CA of the code amount control unit including a predetermined number of DCT blocks from exceeding the predetermined code amount CAX. The quantization level of the DCT block included in the code amount control unit is determined, and this is used as the quantization control signals Q1 to Q3.
Is supplied to the quantization level / threshold value selection circuit 95.

The quantization level / threshold value selection circuit 95 includes a quantization control signal (Q1, Q2 or Q3) having the smallest quantization level and a threshold vector (THG1, THG2, THG3 or THG4) corresponding to the quantization control signal. ) And are respectively supplied to the quantization circuit 6 and the coring circuit 4d as the selection quantization control signal QSEL and the selection threshold vector THGSEL.

The coring circuit 4d uses the area designating parameters N1, N2, N3 and the selection threshold vector THGSE.
Using L (TH0, TH1, TH2, TH3), the same coring process as the coring circuit 4a of FIG. 3 is performed, and the quantizing circuit 6 performs the quantizing process using the quantizing control signal QSEL.

Except for the above points, it is the same as the first embodiment. As described above, in this embodiment, each group G0 to
The threshold values TH0 to TH3 applied to each G3 are 0 <TH0.
Since the relationship of ≦ TH1 ≦ TH2 ≦ TH3 is satisfied and at least two threshold values have different values, a smaller threshold value is applied to a component having a lower frequency. As a result, the DCT that is replaced with "0" in the low frequency region that has a large visual impact.
While the coefficient is small, in the high frequency region where the visual influence is small, the coefficient is easily replaced with "0", the zero run is increased, and the generated code amount can be suppressed.

Further, the quantization level is determined so that the code amount CA of the code amount control unit does not exceed the predetermined code amount CAX by using different threshold vectors having different thresholds TH0 to TH3 as elements, and the quantization level is the smallest. Since the threshold vector is selected, the optimum coring process can be performed within a range satisfying the condition of the predetermined code amount CAX.

Further, each element TH0 to TH of the threshold vector
Since the change amount of 3 is set to increase as the frequency increases, the code amount can be increased or decreased more effectively.

(Other Embodiments) The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, in the above-described embodiment, an example in which the image information recording / reproducing apparatus is applied is shown. However, the present invention is not limited to this, and the recording signal processing circuit 9 and the reproduction signal processing circuit 11 in FIG. The image information transmitting / receiving apparatus may be realized by replacing the recording medium 100 with a communication transmission line instead of the reception signal processing circuit. Further, the information to be compressed is not limited to image information, and if the compression process is performed by using a coefficient sequence obtained by transform coding of digital data by using zero run and the data value immediately after that. The present invention can be applied.

[0057]

As described above in detail, according to the invention described in claim 1, the coefficients obtained by the transform coding are rounded to a predetermined number of bits, and at least a part of the coefficients obtained by the rounding process. Is determined whether the absolute value is smaller than a preset threshold value larger than 0, and when the absolute value is smaller than the threshold value, coring processing for replacing the value of the coefficient with 0 is performed. Since the variable-length coding is performed on the data after the coring processing, it is possible to minimize the calculation error due to the rounding processing and to extend the zero run. As a result, the number of code words is reduced, and the overall code amount can be reduced. Therefore, the code amount of the code amount control unit can be set to a predetermined code amount or less with a smaller compression rate, and the image quality accompanying compression Deterioration can be reduced.

According to the second aspect of the present invention, since the coring process is performed for the coefficient corresponding to the high frequency component, the influence of the coring process (degradation of image quality) is reduced. , Can be made visually unnoticeable.

According to the third aspect of the present invention, the coefficient is divided into a plurality of groups in the order of low to high frequency components, and the coring process is performed by setting the threshold value for each of the plurality of groups. The threshold value of the group corresponding to the high frequency component is set to be equal to or larger than the threshold value of the group corresponding to the low frequency component and at least two threshold values are different. A threshold is applied. As a result, in the low frequency region where the visual influence is large, the number of DCT coefficients replaced by “0” is small, while in the high frequency region where the visual influence is small, the DCT coefficient is easily replaced by “0” and the zero run is increased. Let
The generated code amount can be suppressed.

According to the fourth aspect of the present invention, the threshold value is set so that the code amount generated in the code amount control unit does not exceed the predetermined code amount. A coring process can be performed.

According to the invention of claim 5, the range of the coefficient to be subjected to the coring processing is set so that the code amount generated in the code amount control unit does not exceed the predetermined code amount. It is possible to set an optimum target area for coring processing within a range that does not exceed a predetermined code amount, and perform coring processing with a minimum visual effect.

According to a sixth aspect of the present invention, the coefficient is divided into a plurality of groups in order from a component having a low frequency to a component having a high frequency, and the coring is performed by individually setting the threshold value for each of the plurality of groups. Since the processing is executed and the threshold value is changed so that the code amount generated in the code amount control unit does not exceed the predetermined code amount, the same effects as claims 3 and 4 can be obtained. When changing the threshold value further, the degree of change of the threshold value is
The higher the frequency component, the larger the setting, so
The code amount can be increased or decreased more effectively.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information recording / reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining zigzag scanning.

FIG. 3 is a block diagram for explaining a coring circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram for explaining areas and groups that are targets of coring processing.

FIG. 5 is a block diagram for explaining a code amount control circuit and a coring circuit according to a third embodiment of the present invention.

FIG. 6 is a block diagram for explaining a code amount control circuit and a coring circuit according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram for explaining a code amount control circuit and a coring circuit according to a fifth embodiment of the present invention.

[Explanation of symbols]

2 rounding circuit 3 Zigzag scan circuit 4 Coring circuit 5 Code amount control circuit 6 Quantization circuit 7 Run-length coding circuit 8 Variable length coding circuit

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Claims (6)

(57) [Claims] 1. A method for compressing digital data in which a coefficient obtained by transform coding of digital data is variable-length coded based on the number of appearances of 0 and a coefficient value, wherein coefficient values obtained by the transform coding are rounded off. A first step of performing a rounding process for rounding to a predetermined number of bits, and determining whether or not the absolute value of at least a part of the coefficients obtained by the rounding process is smaller than a preset threshold value greater than 0, When the absolute value is smaller than the threshold value, a second step of performing coring processing for replacing the value of the coefficient with 0, and a third step of performing variable length coding on the data after the coring processing. A method for compressing digital data, which comprises: 2. The method of compressing digital data according to claim 1, wherein the coring process is performed on a component corresponding to a high frequency component of the coefficient. 3. The coefficient is divided into a plurality of groups in order from a component having a low frequency to a component having a high frequency, the threshold is set for each of the plurality of groups, and the coring process is executed to cope with a component having a high frequency. 2. The method for compressing digital data according to claim 1, wherein the threshold value of the group is set to be equal to or larger than the threshold value of the group corresponding to the component having a low frequency, and at least two threshold values are different. 4. The method of compressing digital data according to claim 1, wherein the threshold value is set so that the code amount generated in the code amount control unit does not exceed a predetermined code amount. 5. The digital signal according to claim 1, wherein a range of coefficients to be subjected to the coring processing is set so that a code amount generated in a code amount control unit does not exceed a predetermined code amount. Data compression method. 6. The code amount control unit, wherein the coefficient is divided into a plurality of groups in order from a component with a low frequency to a component with a high frequency, the threshold is independently set for each of the plurality of groups, and the coring process is executed. 2. The digital data according to claim 1, wherein the threshold value is changed so that the code amount generated in 1 does not exceed a predetermined code amount, and the change degree of the threshold value at this time is set to be larger in a group having a higher frequency component. Compression method.