JP2000068855A - Compression method for digital data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the compression method for digital data where an arithmetic error of conversion coding is minimized and signal deterioration attended with compression is reduced. SOLUTION: A round-off circuit 2 applies round-off processing to a 16-bit DCT coefficient into data in 10-bit (9-bit for a DC component), a coring circuit 4 discriminates whether or not the absolute value |D(i)| of DCT coefficients D(i) (i=N1-63) of a high frequency region is smaller than a threshold TH1, and in the case of |D(i)|<TH1, the circuit 4 applies coring processing to replace the DCT coefficients with '0', and variable length coding is applied to data after the coring processing as an object.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for compressing digital data in which coefficients obtained by transform coding such as DCT (discrete cosine transform) are variable-length coded.

[0002]

2. Description of the Related Art As a method of compressing the information amount of a digitized image signal, a method of combining transform coding and variable length coding is known. Since image signals generally have high correlation, energy can be concentrated by using transform coding such as orthogonal transform. DCT is often used as transform coding, whereby energy concentrates on the DC component on the frequency axis, and the energy decreases as the frequency increases. For this reason, the coefficient corresponding to the component having a high frequency has a small value and a high probability of becoming 0.

In order to further compress the amount of information, weighting and quantization of coefficients are performed for each frequency component. As a result, the probability that a component having a higher frequency becomes zero becomes higher. Coefficients obtained by transform coding using such a property are arranged in order from a component corresponding to a component having a low frequency to a component corresponding to a component having a high frequency, and the number of consecutive 0s (referred to as “zero run”). ) And a coefficient value other than zero, and a codeword is generated (a type of entropy coding) in accordance with the appearance probability, and two-dimensional Huffman coding is often used.

[0004]

By the way, in order to ensure the accuracy of the DCT operation, the number of bits in the middle of the operation is increased to ensure the accuracy, and then, when the final transform coefficient is obtained,
Generally, rounding processing such as rounding and truncation is performed so that the required number of bits is obtained. However, when rounding is performed, D
Although errors due to CT and inverse transforms can be reduced, for example, 0.5 is rounded up to 1 so that
The number of codewords increases without the zero run becoming too large. Further, in general, a code word having a longer code length is assigned to a coefficient having a larger value, so that the length of the code word itself becomes longer.

If the total code amount increases due to a longer code length or an increase in the number of code words, it is necessary to increase the compression step width and increase the compression ratio in order to keep the code amount within a predetermined value. However, there is a problem that the image quality is deteriorated.

[0006] On the other hand, if rounding is performed instead of rounding,
Such a problem does not occur. For example, since 0.5 is rounded to 0, the zero run becomes longer and the number of code words decreases, and the value is rounded to a smaller value, and the code length becomes shorter.
Therefore, since the code amount is reduced as a whole, the compression rate can be reduced with the same code amount, and the image quality deterioration due to compression can be suppressed. However, since the rounding is performed at the time of calculation, the DC is smaller than when rounding is performed.
There is a problem that an operation error accompanying the T-transform and the inverse transform becomes large.

The present invention has been made in view of the above points, and provides a digital data compression method capable of minimizing an operation error in transform coding and reducing signal degradation accompanying compression. The purpose is to:

[0008]

According to a first aspect of the present invention, a coefficient obtained by transform coding of digital data is encoded by a variable length coding method based on the number of occurrences of 0 and the coefficient value. A digital data compression method for performing a rounding process for rounding a coefficient value obtained by the transform coding to a predetermined number of bits by rounding off.
And determining whether an absolute value of at least a part of the coefficient obtained by the rounding process is smaller than a predetermined threshold value larger than 0, and when the absolute value is smaller than the threshold value, And a third step of performing variable-length coding on the data after the coring processing as a target.

According to a second aspect of the present invention, in the digital data compression method according to the first aspect, the coring process is performed on a coefficient corresponding to a high-frequency component of the coefficients. Features.

According to a third aspect of the present invention, in the digital data compression method according to the first aspect, the coefficient is divided into a plurality of groups in order from a component having a low frequency to a component having a high frequency. The coring process is performed by setting the threshold value so that the threshold value of the group corresponding to the high frequency component is equal to or greater than the threshold value of the group corresponding to the low frequency component and at least two threshold values are different. It is characterized by setting.

According to a fourth aspect of the present invention, in the digital data compression method of the first aspect, the threshold value is set such that the code amount generated in the code amount control unit does not exceed a predetermined code amount. Features.

According to a fifth aspect of the present invention, in the method for compressing digital data according to the first aspect, the object of the coring process is such that the code amount generated in the code amount control unit does not exceed a predetermined code amount. It is characterized in that a range of coefficients is set.

According to a sixth aspect of the present invention, in the digital data compression method of the first aspect, the coefficient is divided into a plurality of groups in order from a component having a low frequency to a component having a high frequency. The coring process is executed by independently setting the threshold value, and the threshold value is changed so that the code amount generated in the code amount control unit does not exceed a predetermined code amount. The higher the group, the larger the setting.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a configuration of an image signal recording / reproducing apparatus to which a digital data compression method according to the present invention is applied. The recording system of this apparatus includes a DCT operation circuit 1 for performing a DCT operation,
Rounding circuit 2 for performing rounding processing on CT coefficients
A zigzag scan (ZZS) circuit 3 for arranging DCT coefficients in order from a component corresponding to a low frequency component, a coring circuit 4 for performing a coring process described later, and a code amount corresponding to a predetermined number of DCT blocks. A code amount control circuit 5 for determining a quantization level so as to be smaller than a predetermined code amount, a quantization circuit 6 for performing a quantization process according to the quantization level, and a zero-run (continuous 0) ) And a run-length encoding (RLC) circuit 7 for converting to a set of coefficient values other than 0, a variable-length encoding (VLC) circuit 8 for performing variable-length encoding by two-dimensional Huffman code,
AC (AC) component data input from the variable length encoding circuit 8 and DC input from the zigzag scan circuit 3
A recording signal processing circuit 9 that adds an error correction code, a synchronization signal, ID information, additional information, and the like to (DC) component data, modulates the data, and records the modulated signal on the recording medium 100.
And

The reproduction system includes a reproduction signal processing circuit 1 for demodulating a signal reproduced from the recording medium 100 and performing error correction and the like.
1 and a variable length decoding (VLD) circuit 12 for converting output data of the reproduction signal processing circuit 11 into a set of zero run and coefficient values.
And zero as many as necessary according to the zero run, and the original D
A run-length decoding (RLD) circuit 13 for restoring a CT coefficient sequence and an inverse quantization circuit 1 for inversely quantizing DCT coefficients
4, an inverse zigzag scan (inverse ZZS) circuit 15 for returning the DCT coefficient sequence to the original 8 × 8 array, an inverse DCT operation circuit 16 for performing an inverse DCT operation, and image data obtained by the inverse DCT operation. A rounding circuit 17 for performing a rounding process.

An 8-bit digital image signal is input to the DCT operation circuit 1 of the recording system in units of small blocks (hereinafter, referred to as “DCT blocks”) of 8 × 8 pixels on the screen. Performs a DCT operation in units of DCT blocks, and sets the resulting coefficient value to 1
Output as 6-bit digital data. The rounding circuit 2 rounds 16-bit AC component digital data to 10-bit digital data and rounds 16-bit DC component digital data to 9-bit digital data.

The "rounding off" processing of digital data in the present specification may include at least rounding up processing. If input data is equal to or larger than a predetermined threshold, the processing is rounded up. Say. As an example, a process of rounding 5-bit binary complement data (input data) to a 3-bit binary complement code will be described with reference to Table 1. In each of the numerical values shown in Table 1, the most significant bit is a sign bit. Also, (li
The numerical value with m) means that a limiter has been applied because the range is exceeded by the round-up processing.

[Table 1]

Table 1 shows two types of truncation processing for comparison. Truncation 1 is processing for simply truncating the lower two bits. This eliminates the need for a special circuit, but has the disadvantage that the operation becomes asymmetric between positive and negative. Truncation 2 is a modification of truncation 1 in which truncation is performed so that positive and negative are symmetric. For example, in the case of a negative value, the value is once converted to an absolute value, the lower two bits are truncated, and the value is returned to a negative value again, thereby performing a truncation process.

Rounding 1 in Table 1 corresponds to so-called rounding in a decimal number. When it is considered that there is a decimal point in the second and third bits from the bottom of 5-bit input data, the first decimal point is used. This corresponds to the process of rounding off to the nearest place. Round-off 2 is obtained by changing the round-up and round-down thresholds in round-off 1 to a direction in which the possibility of round-down is increased. That is, in rounding 1, 0.25, 0.50, 0.75 are rounded to 0, 1, 1 respectively, while in rounding 2, they are rounded to 0, 0, 1 respectively. For rounding 2, rounding 1
Since the value is rounded in a direction in which the value becomes smaller, the result of the requantization is smaller, and the probability of becoming 0 is increased, which is effective in reducing the code amount.

As described above, the term “rounding” in the present specification is used.
Is rounded up when the input data is above a predetermined threshold,
At other times, it is a process of rounding down. Table 1 shows an example in which signed 5-bit data is rounded to signed 2-bit data. However, when rounding signed 16-bit data to signed 10-bit data, "rounding off" is similarly performed. It goes without saying that processing can be performed, and the threshold value for determining rounding up or down can be set to various values.

As shown in FIG. 2, the zigzag scan circuit 3 supplies the DC component of the DCT coefficient (No. 0) to the recording signal processing circuit 9 and converts the AC component of the DCT coefficient into the lowest frequency component (No. It is supplied to the coring circuit 4 as a DCT coefficient sequence sequentially arranged from the highest component (No. 63) to the highest component (No. 63).

As shown in FIG. 4 (a), the coring circuit 4 includes N1st to 63rd DC
Assuming that the T coefficient is a target area (hereinafter “N1” is referred to as an “area designation parameter”), D
The absolute value of the CT coefficient D (i) (i = N1 to 63) is obtained,
It is determined whether or not the absolute value is smaller than a predetermined threshold value TH1 larger than 0, and when | D (i) | <TH1, the DCT coefficient D (i) is replaced with “0” and output. , | D (i) | ≧ TH1, a process of outputting the DCT coefficient D (i) as it is (hereinafter referred to as “coring process”) is performed.

The code amount control circuit 5 has a code amount CA of a code amount control unit composed of a predetermined number of DCT blocks.
Is determined so as not to exceed the predetermined code amount CAX (however, so as to be as close as possible to the predetermined code amount CAX), the quantization level of the DCT block included in the code amount control unit is determined. Quantization circuit 6 as signal Q
To supply. The quantization circuit 6 quantizes the DCT coefficients supplied from the coring circuit 4 according to the quantization level specified by the quantization control signal Q.

The run-length encoding circuit 7 converts the quantized DCT coefficient sequence into a set of the zero run and the value of the DCT coefficient immediately after the zero run.
A set of CT coefficient values is variable-length coded by a two-dimensional Huffman code. The recording signal processing circuit 9 includes a variable length encoding circuit 8
An error correction code, a synchronization signal, ID information, additional information, and the like are added to the AC (AC) component data input from the DC and DC (DC) component data input from the zigzag scan circuit 3 to perform modulation. And the modulated signal is stored in a recording medium 1
00 is recorded.

The reproduction processing circuit 11 demodulates the signal reproduced from the recording medium 100 and performs error correction and the like, and supplies the 9-bit DC component directly to the reverse zigzag scanning circuit 15.
The AC component data is supplied to the variable length decoding circuit 12.
The variable length decoding circuit 12 converts the output data of the reproduction signal processing circuit 11 into a set of zero run and coefficient values, and the run length decoding circuit 13 inserts a necessary number of zeros according to the zero run, and Restore the DCT coefficient sequence. Inverse quantization circuit 1
4 is the DC input from the run-length decoding circuit 13
The T coefficient is inversely quantized and input to the inverse zigzag scan circuit 15 as 10-bit data. The inverse zigzag scan circuit 15 performs a process of returning the DCT coefficient sequence to the original 8 × 8 array, and the inverse DCT operation circuit 16 performs an inverse DCT operation with 16-bit operation accuracy and outputs 16-bit image data. I do. The rounding circuit 17 performs a rounding process of rounding the 16-bit image data obtained by the inverse DCT operation to 8 bits, and outputs an original digital image signal.

Although the absolute value of the DCT coefficient has been described as being performed by the coring circuit 4, the absolute value may be converted by the rounding circuit 2 beforehand. That is, the rounding circuit 2
Converts 16-bit signed data into 1-bit sign bit and 15-bit absolute value data,
The 5-bit absolute value data is rounded to the 9-bit absolute value data. The zigzag scan circuit 3 outputs AC data composed of a total of 10 bits of 1 sign bit and 9 bits of absolute value data. In this case, the absolute value processing in the coring circuit 4 becomes unnecessary.

As described above, in the present embodiment, the rounding circuit 2 rounds the 16-bit DCT coefficient to 10-bit data (DC component is 9 bits) by rounding, and the coring circuit 4 performs coring. It is determined whether or not the absolute value | D (i) | of the DCT coefficient D (i) (i = N1 to 63) of the target area is smaller than the threshold value TH1, and if | D (i) | <TH1, Since the coring process for replacing the DCT coefficient with “0” is performed, the calculation error due to the rounding process can be minimized, and the zero run can be lengthened. As a result, the number of codewords is reduced, and the overall code amount can be reduced. Therefore, the code amount of the code amount control unit can be reduced to a predetermined code amount or less with a smaller compression rate, and the image quality associated with compression can be reduced. Deterioration can be reduced.

Further, since the area to be subjected to the coring processing is the high-frequency area of the AC component (the N1st to 63rd areas), the influence of the coring processing (deterioration of image quality) is visually recognized. Can be made almost unnoticeable.

(Second Embodiment) In this embodiment, the coring circuit 4 of FIG. 1 is replaced with the coring circuit 4a of FIG.
Four thresholds TH0, TH1, TH are provided to the coring circuit 4a.
2, TH3 and area designation parameters N1, N2, N3
Is input. Here, the four thresholds are 0 <TH0 ≦ TH1 ≦ TH2 ≦ TH3 (4
Thresholds are equal (TH0 = TH1 = TH2 = T
H3) Never set, in other words at least 2
(Three threshold values have different values), and the three area designation parameters are 0 <N1 <N2 <N3 <64.
Have the relationship

The coring circuit 4a performs the following processing. By area specification parameters N1, N2, N3,
As shown in FIG. 4B, the DCT coefficients of the AC component are divided into four groups G0 to G3. That is, the group G
0 includes DCT coefficients D (i) (i = 1 to N1-1), and group G1 includes DCT coefficients D (i) (i = N1 to N1).
N2-1), and the group G2 has a DCT coefficient D
(I) (i = N2 to N3-1), and the group G3
Consists of DCT coefficients D (i) (i = N3 to 63).
The threshold value TH0 is set for each of the groups G0 to G3.
To TH3 to perform a coring process.

That is, 1) it is determined whether or not the absolute value of the DCT coefficient D (i) (i = 1 to N1-1) of the group G0 is smaller than the threshold value TH0. 2) For the DCT coefficient D (i) (i = N1 to N2-1) of the group G1, it is determined whether or not its absolute value is smaller than a threshold value TH1. Replace the coefficient with "0",
3) DCT coefficient D (i) of group G2 (i = N2 to N)
Regarding 3-1), it is determined whether or not the absolute value is smaller than a threshold value TH2. If the absolute value is smaller than the threshold value TH2, the DCT coefficient is replaced with “0”.
(I) For (i = N3 to 63), it is determined whether or not the absolute value is smaller than a threshold value TH3, and when it is smaller, a process of replacing the DCT coefficient with “0” is performed.

The other points are the same as those of the first embodiment. According to the present embodiment, the thresholds TH0 to TH3 applied to each of the groups G0 to G3 are 0 <TH0 ≦ TH1.
Since there is a relationship of ≤ TH2 ≤ TH3 and at least two thresholds have different values, a smaller threshold is applied to a component with a lower frequency. As a result, in the low-frequency region where the visual influence is large, the number of DCT coefficients replaced with “0” is small, while in the high-frequency region where the visual influence is small,
It becomes easy to be replaced with “0”, zero run can be increased, and the generated code amount can be suppressed.

(Third Embodiment) In this embodiment, the coring circuit 4 and the code amount control circuit 5 shown in FIG. 1 are replaced with a coring circuit 4b and a code amount control circuit 5a shown in FIG. 5, respectively. is there.

The code amount control circuit 5a comprises three coring circuits 41, 42, 43 and three code amount control circuits 51,
52, 53, and a quantization level / threshold selection circuit 55. The coring circuits 41, 42, and 43 have area designation parameters N1 and different thresholds t1, t, respectively.
2 and t3 are supplied, and the threshold values t1 to t3
3 is also configured to be input to the quantization level / threshold value selection circuit 55.

Each of the coring circuits 41 to 43 performs the same coring processing as that of the coring circuit 4 in the first embodiment using different threshold values t1 to t3 and the same area designation parameter N1. The coefficients are supplied to code amount control circuits 51 to 53, respectively. The code amount control circuits 51 to 53 are, like the code amount control circuit 5 of FIG. 1, such that the code amount CA of the code amount control unit including a predetermined number of DCT blocks does not exceed the predetermined code amount CAX.
The quantization level of the DCT block included in the code amount control unit is determined and supplied to the quantization level / threshold value selection circuit 55 as quantization control signals Q1 to Q3.

The quantization level / threshold selection circuit 55 includes a quantization control signal (Q1, Q2 or Q3) having the smallest quantization level and a threshold (t) corresponding to the quantization control signal.
1, t2 or t3) and supplies them to the quantization circuit 6 and the coring circuit 4b as the selection quantization control signal QSEL and the selection threshold THSEL, respectively.

The coring circuit 4b has a selection threshold THSE
Coring processing similar to that of the coring circuit 4 of FIG. 1 (processing in which the threshold value TH1 is replaced with THSEL in the first embodiment) is performed according to L and the area designation parameter N1.
The quantization circuit 6 performs a quantization process using the quantization control signal QSEL.

The other points are the same as those of the first embodiment. As described above, in the present embodiment, different threshold values t1 to t1 are set.
Using t3, the quantization level is determined so that the code amount CA of the code amount control unit does not exceed the predetermined code amount CAX, and a threshold value with the smallest quantization level (small quantization step and small quantization error) is selected. Therefore, it is possible to perform an optimal coring process in a range satisfying the condition of the predetermined code amount CAX.

(Fourth Embodiment) In this embodiment, the coring circuit 4 and the code amount control circuit 5 shown in FIG. 1 are replaced with a coring circuit 4c and a code amount control circuit 5b shown in FIG. 6, respectively. is there.

The code amount control circuit 5b includes three coring circuits 61, 62, 63 and three code amount control circuits 71,
72, 73 and a quantization level / threshold value selection circuit 75. Coring circuits 41, 42, 43 have different area designation parameters n1, n2, n3, respectively.
The same threshold value TH1 is supplied, and the area designation parameters n1 to n3 are also inputted to the quantization level / threshold value selection circuit 75.

Each of the coring circuits 61 to 63 performs the same coring processing as the coring circuit 4 in the first embodiment using different area designation parameters n1 to n3 and the same threshold value TH1, and the DCT after the processing is performed. The coefficients are supplied to code amount control circuits 71 to 73, respectively. The code amount control circuits 71 to 73 are, like the code amount control circuit 5 in FIG. 1, such that the code amount CA of the code amount control unit including a predetermined number of DCT blocks does not exceed the predetermined code amount CAX. The quantization level of the DCT block included in the code amount control unit is determined, and is determined by the quantization control signals Q1 to Q3.
Is supplied to the quantization level / threshold value selection circuit 75.

The quantization level / threshold selection circuit 75 includes a quantization control signal (Q1, Q2 or Q3) having the smallest quantization level and an area designation parameter (n1, n2 or n3) corresponding to the quantization control signal. And supplies them to the quantization circuit 6 and the coring circuit 4c as the selected quantization control signal QSEL and the selected area designation parameter nSEL, respectively.

The coring circuit 4c performs the same coring processing as the coring circuit 4 of FIG. 1 using the selected area specifying parameter nSEL and the threshold value TH1 (the processing in which the area specifying parameter N1 is replaced with nSEL in the first embodiment). ), And the quantization circuit 6 performs the quantization control signal QSEL.
Is performed using the quantization process.

The other points are the same as those of the first embodiment.

As described above, in the present embodiment, the code amount C of the code amount control unit is determined by using different area designation parameters.
The quantization level is determined so that A does not exceed the predetermined code amount CAX, and the area designation parameter having the smallest quantization level (the quantization step is small and the quantization error is small) is selected. Thus, an optimum coring processing target area can be set within a range satisfying the condition (1), and the coring processing can be performed with a minimum visual effect.

(Fifth Embodiment) This embodiment is basically a combination of the second embodiment and the third embodiment. The coring circuit 4 and the code amount control circuit 5 shown in FIG. Are replaced by the coring circuit 4d and the code amount control circuit 5c shown in FIG. 7, respectively.

The code amount control circuit 5c comprises three coring circuits 81, 82, 83 and three code amount control circuits 91,
92, 93 and a quantization level / threshold value selection circuit 95. Coring circuits 81, 82, 83 have different area designation parameters N1, N2, N3, respectively.
Different threshold vectors THG1, THG2, THG3, T
HG4 and the threshold vector T
HG1 to THG3 are quantization level / threshold selection circuits 95
Is also configured to be input. As in the second embodiment, the four thresholds are 0 <TH0 ≦ TH1 ≦ TH2
≤ TH3 (however, all four thresholds are equal (TH0
= TH1 = TH2 = TH3) There is a relationship of not setting (in other words, at least two thresholds have different values), and the three area designation parameters are 0 <N
1 <N2 <N3 <64.

The threshold vectors THG1 to THG4 include thresholds TH0, TH1, TH2, and TH3 corresponding to the four groups G0 to G3 (see FIG. 4B) divided by the area specification parameters N1 to N3, respectively. (TH0, TH1, TH2, TH2)
3) is displayed. Each threshold vector is set, for example, in decimal notation as follows. THG1 = (TH0, TH1, TH2, TH3) =
(1,1,1,2) THG2 = (TH0, TH1, TH2, TH3) =
(1, 1, 2, 3) THG3 = (TH0, TH1, TH2, TH3) =
(1, 2, 3, 6) THG4 = (TH0, TH1, TH2, TH3) =
(2,3,5,9)

Here, the difference between the vectors is as follows, and the difference between the vectors is set so that the higher the frequency, the larger the amount of change in the threshold. That is, each group G0
The change amounts of the threshold value corresponding to G3 are ΔTH0, ΔTH1, Δ
Assuming TH2 and ΔTH3, ΔTH0 ≦ ΔTH1 ≦ ΔT
H2 ≦ ΔTH3 is set. THG2-THG1 = (ΔTH0, ΔTH1, ΔTH2, ΔTH3) = (0,0,1,1) THG3-THG2 = (ΔTH0, ΔTH1, ΔTH2, ΔTH3) = (0,1,1,3) THG4-THG3 = (ΔTH0, ΔTH1, ΔTH2, ΔTH3) = (1, 1, 2, 3)

Each of the coring circuits 81 to 83 performs the same coring processing as that of the coring circuit 4a in the second embodiment using the thresholds TH0 to TH3 for each of the groups G0 to G3. The DCT coefficients are supplied to code amount control circuits 91 to 93, respectively. The code amount control circuits 91 to 93 are, like the code amount control circuit 5 of FIG. 1, such that the code amount CA of the code amount control unit including a predetermined number of DCT blocks does not exceed the predetermined code amount CAX. The quantization level of the DCT block included in the code amount control unit is determined, and is determined by the quantization control signals Q1 to Q3.
Is supplied to the quantization level / threshold value selection circuit 95.

The quantization level / threshold selection circuit 95 includes a quantization control signal (Q1, Q2 or Q3) having the smallest quantization level and a threshold vector (THG1, THG2, THG3 or THG4) corresponding to the quantization control signal. ) Are supplied to the quantization circuit 6 and the coring circuit 4d as the selected quantization control signal QSEL and the selected threshold vector THGSEL, respectively.

The coring circuit 4d includes area designation parameters N1, N2, N3 and a selection threshold vector THGSE.
Using L (TH0, TH1, TH2, TH3), a coring process similar to that of the coring circuit 4a in FIG. 3 is performed, and the quantization circuit 6 performs a quantization process using the quantization control signal QSEL.

The other points are the same as in the first embodiment. As described above, in the present embodiment, each group G0
The threshold values TH0 to TH3 applied for each G3 are 0 <TH0
Since there is a relationship of ≤ TH1 ≤ TH2 ≤ TH3 and at least two thresholds have different values, a smaller threshold is applied to a component with a lower frequency. As a result, in the low-frequency region where the visual influence is large, the DCT replaced with “0”
While the coefficient is reduced, in a high-frequency region where the influence is visually small, it is easily replaced with “0”, zero run is increased, and the generated code amount can be suppressed.

The quantization level is determined so that the code amount CA of the code amount control unit does not exceed the predetermined code amount CAX by using different threshold vectors having different threshold values TH0 to TH3 as elements. Since the threshold vector is selected, an optimal coring process can be performed within a range satisfying the condition of the predetermined code amount CAX.

Further, each element TH0 to TH of the threshold vector
Since the change amount of No. 3 is set to increase as the frequency increases, the code amount can be more effectively increased or decreased.

(Other Embodiments) The present invention is not limited to the above-described embodiments, and various modifications are possible. For example, in the above-described embodiment, an example in which the present invention is applied to an image information recording / reproducing apparatus has been described. However, the present invention is not limited to this, and the recording signal processing circuit 9 and the reproduction signal processing circuit 11 in FIG. Instead of the reception signal processing circuit, the recording medium 100 may be replaced with a communication transmission path, so that an image information transmitting / receiving apparatus may be provided. The information to be compressed is not limited to image information, but may be applied to a case where a compression process is performed by using a zero-run and a data value immediately after the coefficient sequence obtained by transform coding of digital data. The present invention can be applied.

[0057]

As described above in detail, according to the first aspect of the present invention, the coefficient obtained by the transform coding is rounded to a predetermined number of bits by rounding, and at least a part of the coefficient obtained by the rounding process is obtained. It is determined whether or not the absolute value of the coefficient is smaller than a preset threshold value larger than 0. If the absolute value is smaller than the threshold value, a coring process of replacing the coefficient value with 0 is performed. Since the variable length coding is performed on the data after the coring process, the calculation error due to the rounding process can be minimized, and the zero run can be lengthened. As a result, the number of codewords is reduced, and the overall code amount can be reduced. Therefore, the code amount of the code amount control unit can be reduced to a predetermined code amount or less with a smaller compression rate, and the image quality associated with compression can be reduced. Deterioration can be reduced.

According to the second aspect of the present invention, since the coring processing is performed on a coefficient corresponding to a high-frequency component of the coefficients, the influence of the coring processing (deterioration of image quality) is reduced. Can be almost visually inconspicuous.

According to the third aspect of the present invention, the coefficient is divided into a plurality of groups in order from a component having a low frequency to a component having a high frequency, and the threshold is set for each of the plurality of groups to perform the coring process. The threshold value of the group corresponding to the high-frequency component is set to be equal to or greater than the threshold value of the group corresponding to the low-frequency component, and at least two threshold values are set to different values. A threshold is applied. As a result, in the low-frequency region where the visual influence is large, the DCT coefficient to be replaced with “0” decreases, whereas in the high-frequency region where the visual influence is small, the DCT coefficient is easily replaced with “0”, and the zero run increases. Let
The generated code amount can be suppressed.

According to the fourth aspect of the present invention, the threshold value is set so that the code amount generated in the code amount control unit does not exceed the predetermined code amount. Coring processing can be performed.

According to the fifth aspect of the present invention, the range of coefficients to be subjected to the coring process is set so that the code amount generated in the code amount control unit does not exceed the predetermined code amount. It is possible to set an optimal target area for the coring process within a range not exceeding a predetermined code amount, and perform the coring process with a minimum visual effect.

According to the sixth aspect of the present invention, the coefficient is divided into a plurality of groups in order from a component having a low frequency to a component having a high frequency, and the threshold value is independently set for each of the plurality of groups so that the coring is performed. Since the processing is executed and the threshold value is changed so that the code amount generated in the code amount control unit does not exceed the predetermined code amount, the same effects as those of the third and fourth aspects are achieved. When the threshold is further changed, the degree of change of the threshold is
The higher the frequency component, the larger the group is set, so
The code amount can be more effectively increased or decreased.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information recording / reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining zigzag scanning.

FIG. 3 is a block diagram illustrating a coring circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram for explaining areas and groups to be subjected to coring processing.

FIG. 5 is a block diagram illustrating a code amount control circuit and a coring circuit according to a third embodiment of the present invention.

FIG. 6 is a block diagram illustrating a code amount control circuit and a coring circuit according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram illustrating a code amount control circuit and a coring circuit according to a fifth embodiment of the present invention.

[Explanation of symbols]

 2 Rounding circuit 3 Zigzag scan circuit 4 Coring circuit 5 Code amount control circuit 6 Quantization circuit 7 Run length coding circuit 8 Variable length coding circuit

Claims (6)

[Claims] 1. A digital data compression method for performing variable length coding on a coefficient obtained by transform coding of digital data based on the number of occurrences of 0 and a coefficient value, wherein the coefficient value obtained by the transform coding is rounded off. A first step of performing a rounding process for rounding to a predetermined number of bits, and determining whether an absolute value of at least a part of the coefficient obtained in the rounding process is smaller than a preset threshold value larger than 0, When the absolute value is smaller than the threshold value, a second step of performing coring processing for replacing the value of the coefficient with 0, and a third step of performing variable-length coding on the data after the coring processing A method for compressing digital data, comprising: 2. The digital data compression method according to claim 1, wherein the coring process is performed on a coefficient corresponding to a high-frequency component of the coefficients. 3. The coefficient is divided into a plurality of groups in order from a component having a low frequency to a component having a high frequency, the threshold is set for each of the plurality of groups, and the coring process is executed to correspond to a component having a high frequency. 2. The digital data compression method according to claim 1, wherein the threshold value of the group to be set is set to be equal to or greater than the threshold value of the group corresponding to the component having a low frequency, and at least two threshold values are different. 4. The digital data compression method according to claim 1, wherein said threshold value is set such that a code amount generated in a code amount control unit does not exceed a predetermined code amount. 5. The digital coding system according to claim 1, wherein a range of coefficients to be subjected to the coring processing is set so that a code amount generated in a code amount control unit does not exceed a predetermined code amount. Data compression method. 6. The code amount control unit divides the coefficient into a plurality of groups in order from a component having a low frequency to a component having a high frequency, performs the coring process by independently setting the threshold for each of the plurality of groups, 2. The digital data according to claim 1, wherein the threshold value is changed so that the code amount generated in step (b) does not exceed a predetermined code amount, and the degree of change of the threshold value at this time is set larger for a group having a higher frequency component. Compression method.