JP3401610B2 - Signal multiplexing equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal multiplexer for multiplexing data signals output from a plurality of pattern generators and outputting the multiplexed data signals. The present invention relates to a technique for preventing an influence of a variation in delay time due to time or a cable. 2. Description of the Related Art Conventionally, a signal multiplexing apparatus has been used to multiplex and output a plurality of series of data signals output from a plurality of pattern generators. FIG. 5 shows a configuration of a conventional signal multiplexing device 10 for multiplexing data signals D _{1 to} D ₄ output from _four pattern generators 11 to ₁₄ . The signal multiplexing apparatus 10 inputs a clock signal C ₀ having a frequency f output from a clock signal generator 11 as shown in FIG. As shown in (b), the 4-to-1 multiplexer circuit 13 is switched by the count output of the counter 12 which changes from 1 → 2 → 3 → 4, and the frequency-divided signal Ca obtained by dividing the clock signal C ₀ by four. Is output to the clock output terminal 14, and the cable 2 is connected to the clock output terminal 14.
In giving each connected pattern generator is 1 ₁ to 1 _4-divided signal Ca, the data signal D ₁ to D ₄ equal bit rates from each pattern generator 1 ₁ to 1 ₄ and the divided signal Ca Output almost synchronously. [0005] Data signals outputted from the pattern generator ₁ 1 to 1 ₄ are input to the data input terminal 15 ₁ to 15 ₄ of the signal multiplexing apparatus 10 via the cable 3 ₁ to 3 _4.
Data signal input to the data input terminal 15 ₁ to 15 ₄ are inputted to the multiplexer circuit 13 through respective fixed delay circuit _161-164. The fixed delay circuits 16 _{1 to} 16 ₄ delay the data signals and supply the delayed data signals to the multiplexer circuit 13 so that the data of the series selected by the multiplexer circuit 13 does not change at least during the period T of the clock signal C _0. . Namely, the fixed delay circuit 16 ₁ proceeds slightly than count output "1" of the phase of the data signal D ₁ input to the data input terminal 15 ₁ is counter 12 as in FIG. 6 (c) The fixed delay circuits 16 ₂ and 16
₃ is a data input terminal 1 as shown in (d) and (e) of FIG.
5 _2, 15 data signal D ₂ that is inputted to the _3, D ₃ phases to be substantially in phase with the count output of the counter 12 "1", also fixed delay circuit 16 ₄ of FIG. 6 (f data signal D inputted to the data input terminal 15 ₄ as)
The phase of the counter ₄ is slightly delayed from the count output "1" of the counter 12 to give a phase margin to the data signal corresponding to each count output of the counter 12, and a multiplexer circuit as shown in FIG. In step 13, multiplexing of each data is performed correctly. By the way, in the thus constructed signal multiplexing apparatus, when there are variations in the pattern generator 1 ₁ to 1 ₄ internal delay time multiplexed data can not be performed correctly in the multiplexer circuit 13. In particular, when pattern generators of different types are mixed, the variation becomes very large. For example, as shown by a broken line in FIG. A change in the bit of the data signal occurs. For this reason, conventionally, a data signal input to the multiplexer circuit 13 has a phase margin with respect to the count output of the counter 12 (switching of the multiplexer circuit 13) as shown in FIG. in as input, strictly measures the delay time for each pattern generator was used to create the cable 3 ₁ to 3 ₄ the length of the corresponding to the delay time with high accuracy. However, as described above, it is very troublesome to measure the delay time for each pattern generator to prepare a cable, and to use the cable by mistake. If a cable of an appropriate length is used instead of a lost cable, multiplexing cannot be performed correctly, and there is a problem that the cable itself must be strictly managed. The present invention solves this problem and provides a signal multiplexing apparatus capable of obtaining a correctly multiplexed signal without being affected by differences in delay characteristics of individual pattern generators or a cable length. It is an object. [0012] In order to achieve the above object, a signal multiplexing apparatus of the present invention comprises a plurality of pattern generators ( _11).
To 1 _n ), and a plurality of clock output terminals (21 _{1 to} 21 _n ) for outputting a first clock signal to be supplied to the first clock signal, the plurality of clock output terminals being provided corresponding to the respective clock output terminals. before a plurality of pattern generator which receives the
Output at the same frequency as the first clock signal.
Are a plurality of clock input terminal for inputting a second clock signal (22 1 _{through 22 n),} it said provided corresponding to the respective clock output terminal, a plurality of patterns that have undergone the first clock signal Data signals (D ₁₎ output from the generator in synchronization with the second clock signal, respectively.
To D _n) and a plurality of data input terminals for inputting respectively ₍₂₃ 1 _{~23 n),} a clock signal generator for outputting a third clock signal having a predetermined frequency _{(C 0)} (25)
And a multiplexer circuit for multiplexing and outputting a plurality of series of data signals input from the respective pattern generators via the respective data input terminals in synchronization with a third clock signal output from the clock signal generator. (27) The third clock signal output from the clock signal generator is a number equal to the number of the series of data signals.
A frequency divider (26) for dividing the frequency by (n), and a second clock signal (C) which is provided in correspondence with each of the clock output terminals and is inputted from each of the pattern generators to each of the clock input terminals. ₁ ′ to C _n ′) and a plurality of phase comparators (31 _{1 to} 31 _n ) for detecting the phase difference between the frequency-divided signal (Ca) output from the frequency divider and the clock output terminals. Clock signals (C _{1 to} C _n ) which are provided corresponding to each other and whose phase can be changed at the same frequency as the frequency-divided signal output from the frequency divider are used as the first clock signals and the respective clock outputs A plurality of clock phase shift circuits (3
0 ₁ to 30 _n ) and the respective clock output terminals, and the respective clock phase shift circuits such that the respective phase differences detected by the respective phase comparison circuits fall within predetermined ranges. and a plurality of control circuits for controlling the amount of phase shift of _{(32 1 ~32 n, 33 1} ~33 n), said plurality of control circuits is output from the frequency divider
Multiplexed by the multiplexer circuit within one cycle of the divided signal
The data signals input corresponding to the data signals
Of the two clock signals, the multiplexing order is the first data.
The second clock signal corresponding to the data signal is the frequency-divided signal.
, The phase is advanced within a predetermined range, and the multiplexing order is
The second clock signal corresponding to the last data signal is
Delayed phase within a predetermined range with respect to the frequency-divided signal.
A second clock signal corresponding to the data signal of
Each of the clock phase shift circuits so as to be substantially in phase with the signal.
Is configured to control the amount of phase shift. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a signal multiplexing device 20 according to an embodiment. This signal multiplexing device 20 multiplexes data signals D _{1 to} D ₄ output from _four pattern generators ₁₁ to 14 when the number n of sequences of input data signals is four, ie, four. Output from each of the pattern generators 1.
₁ to 1 ₄ clock output terminal 21 ₁ for providing a clock signal via respective cable 5 ₁ to 5 ₄ for any length -
21 ₄ and, a clock input terminal 22 ₁ to 22 ₄ for receiving respectively through the cable ₆₁ through ₄ of an arbitrary length the clock signal from the pattern generator ₁ 1 to 1 _4, the pattern generator 1 ₁ to 1 the data signal from ₄ and data input terminals 23 ₁ to 23 ₄ for receiving respectively through the cable 7 _{1-7 4} any length, and a multiplex signal output terminal 24 for outputting the multiplexed signal Have. [0015] It should be noted that, here, the cable 6 ₁ and the cable 7
_1, the cable 6 ₂ and the cable 7 _2, the cable 6 ₃ and the cable 7 _3, and a cable 6 ₄ and the cable 7 ₄ are each identical in length, each pattern generator ₁ 1 to 1 ₄ are data D ₁ (1 ) To D ₁ (M), data D ₂ (1) to D
₂ (M), data D ₃ (1) to D ₃ (M), data D ₄
(1) to D ₄ (M) are output in the order of data at a bit rate equal to the frequency of the input clock signal. The clock signal generator 25 has a predetermined frequency f
And outputs the clock signal C ₀ (e.g. 2488MHz). The counter 26 is a quaternary counter constituting the frequency divider of this embodiment. The counter 26 receives the clock signal C ₀ , outputs the count value to the 4-to-1 multiplexer circuit 27, and outputs the clock signal C _0. Is divided by 4 to output a divided signal Ca. The multiplexer circuit 27 includes a counter 26
Data input terminal 23 ₂ when the count value of "1" to output the data signal D ₁ inputted from the data input terminal 23 ₁ to the multiplexing signal output terminal 24 when the count value is "2"
Data signal D ₂ input from the multiplexed signal output terminal 24
To the data input terminal 2 when the count value is "3".
The data signal D ₃ that is inputted from 3 ₃ outputs to the multiplexing signal output terminal 24, the count value is output to the multiplex signal output terminal 24 of the data signal D ₄ input from the data input terminal 23 ₄ is at "4" . The four counters 30 ₁ to 30 ₄ form a clock phase shift circuit according to the present embodiment, and are constituted by quaternary counters of the same type as the counter 26, and each of the counters 26 divides the clock signal C ₀ by four minutes. Frequency-divided signals C _{1 to} C ₄
And outputs to the clock output terminal 21 ₁ to 21 ₄ as a clock signal for each pattern generator ₁ 1 to 1 _4. Each counter 30 ₁ to 30 _4, to zero (all bits low level) to the count output while receiving a reset signal from the reset signal generating circuit 33 _to 333 ₁ to be described later, the reset is released the clock The counting of the signal C ₀ is started respectively. The four phase comparators 31 _{1 to} 31 ₄ are composed of, for example, a phase comparator and a filter circuit for extracting a DC component of the output of the phase comparator, and input from each of clock input terminals 22 _{1 to} 22 _4. Clock signal C ₁ ′
-C ₄ 'and the divided signal Ca and the respectively phase comparison, and outputs the phase difference signal corresponding to the phase difference to the determining circuit 321 _to 323 _4. Each of the determination circuits 32 _{1 to} 32 ₄ constitutes a control circuit of this embodiment together with reset signal generation circuits 33 _{1 to} 33 ₄ described later.
Either respectively compared with a preset reference range the phase difference signal from _{1-31 4,} the phase difference between the clock signal C ₁ '-C _4' for the divided signal Ca is in the range that is determined, respectively It determines whether to output low (L) level when it is within that range, if the range of the high (H) level determination signal to the reset signal generator 33 _to 333 _4. [0022] Here, when the period of the clock signal C ₀ is T, the determination circuit 32 _1, the phase of the clock signal C ₁ 'with respect to the frequency division signal Ca is progressed in the range of 0.5T~1.5T outputs a low (L) level of the judgment signal when they are, the decision circuit 32 _2, 32 _3, the phase of the divided clock signal C ₂ to the signal Ca ', C _3' is in the range of ± 0.5 T At this time, a low (L) level determination signal is output, and the determination circuit 3
2 _4, when the phase of the clock signal C ₄ 'with respect to the divided signal Ca is delayed in the range of 0.5T～1.5T, so as to output a decision signal of a low (L) level, respectively set Have been. When the phase comparison circuits 31 _{1 to} 31 ₄ output a DC signal corresponding to the phase difference as described above, the determination circuits 32 _{1 to} 32 _{4 change} the voltage to a voltage range corresponding to each set range. Is determined by a comparator or the like. Each reset signal generation circuit 33 _{1 to} 33 _1
4, between the input determination signal is at a high level and outputs to the corresponding counter 30 ₁ to 30 ₄ reset signal at predetermined intervals (e.g., 10 microsecond intervals), the counters 30 ₁ to 30 ₄ is output Clock signals C _{1 to} C ₄
And the output of the reset signal is stopped when the determination signal goes low. The reset signal generation circuit 33 _to 333 _4, the CR type pulse oscillation circuit, for outputting an asynchronous reset signal to the clock signal C ₀ and the divided signal Ca. [0024] The counter 30 ₁ to 30 ₄ in such asynchronous reset signal to reset the control, the divided signal C
By varying the output phase of ₁ -C _4, trumps the phase for frequency division signal Ca of the clock signal C ₁ '-C _4' inputted from the clock input terminal 22 ₁ to 22 ₄ in the respective set range be able to. Next, the operation of the signal multiplexing device 20 will be described with reference to the timing charts of FIGS.
Note that the timing chart in FIG. 2 is a diagram illustrating the operation of the multiplex signal device 20 for one pattern generator 1 ₁ of the four pattern generator 1 ₁ to 1 _4. The clock signal C ₀ output from the clock generator 25 as shown in FIG. 2A is counted by the counter 26 as shown in FIG. 2B, and the counter 26 outputs the clock signal C ₀ from FIG. ) Is output. Here, the counter 3 receiving the divided signal Ca
0 ₁ is, for example, as shown in FIG.
outputs a frequency-divided signal C ₁ with a phase delayed by T time with respect to a.
The divided signal C ₁ from the pattern generator 1 ₁ received as a clock signal, in FIG. 2 (e), the manner of (f), Td time for divided signal C ₁ (Td <1.5T) Clock signal C ₁ 'and data signal D ₁ (i + 1) are input with a delay of. [0028] Thus, the phase of the divided signal Ca divided signal C ₁ with respect to 'is, in a period that is delayed extent of less than 2.5T, the decision circuit 32 _first determination output of FIG. 2 ( It becomes a high level as shown in g). Reset signal generating circuit 33 ₁ is receiving a determination signal of the high level 2
(H), a reset signal R having a Tw width is output at a certain timing t. The counter 30 ₁ receiving this reset signal
Is reset Tw time, the output rises by receiving the first clock signal C ₀ from when reset is released. 3T This phase shift control, e.g., with respect to the divided signal Ca as divided signal C ₁ is view from the counter 30 ₁
When the time delayed clock signal C from the pattern generator 1 _1
1 'will become respect divided signal Ca (3T + Td) to be time-delayed input, the clock signal C _1' phases of, as shown in FIG respect divided signal Ca 0.5T～1 .
If it does not advance within the range of 5T, the determination signal remains at the high level, and this state is maintained until the next reset signal is input. When the phase of the clock signal C ₁ ′ advances by 0.5 T to 1.5 T with respect to the frequency-divided signal Ca by the reset signal R ′ output at t ′, the decision signal It becomes a low level as shown in (g) of FIG.
The output of the reset signal stops, the data signal D ₁ of the phase inputted from the pattern generator 1 _1, an advanced state within the 0.5T~1.5T respect divided signal Ca is maintained . [0031] The above operation is another pattern generator 1 _{2-1 4}
Against, each counter 30 _{2-30 4,} the phase comparator 3
1 _{2-31 4,} the determination circuit 32 _{2-32 4,} is similarly performed by the reset signal generating circuit 33 ₂ to 33 _4. This phase shift control for each pattern generator is completed by several reset respectively, After a lapse of several cycles of time of the reset signal, the four pattern generator 1 ₁ to 1 ₄
The phases of the data signals D _{1 to} D ₄ input from the input device with respect to the frequency-divided signal Ca fall within the respective set ranges as shown in FIGS. 3 (c) to 3 (f). [0032] That is, the data signal D ₁ from the pattern generator 1 ₁ becomes a divided signal Ca in the range of 0.5T~1.5T to phase advance, the data signal D from the pattern generator 1 _2, 1 _{3 2,} D ₃ becomes in the range of ± 0.5 T with respect to the divided signal Ca, the data signal D ₄ from the pattern generator 1 ₄ whereas divided signal Ca a delay phase of 0.5T~1.5T Thus, each data signal changes at a timing sufficiently separated from the change timing of the count output of the counter 26. Therefore, a signal multiplexed in the order of correct data for each stream is output from the multiplexer circuit 27 as shown in FIG. [Other Embodiments] In the above embodiment, each judgment circuit 32
The determination range of _{1-32 4} has been provided for each pattern generator, but the phase of the data signal from each pattern generator 1 ₁ to 1 _4, all ± 0.5 T with respect to e.g. dividing signal Ca It is set to fall within the range, and the data input terminal 23
_The data signal D ₁ input from _{1 is} input to the multiplexer circuit 27 via a fixed delay circuit of 3T time, and the data signals D ₂ and D ₃ input from the data input terminals 23 ₂ and 23 ₃ are: input to the multiplexer circuit 27 via the fixed delay circuit 4T time, the data signal D ₄ input from the data input terminal 23 _4,
Multiplexer circuit 2 via a fixed delay circuit of 5T time
7 may be configured to be input. In this case, a delay line patterned on a printed circuit board, a cable, or the like can be used as each fixed delay circuit. In the above embodiment, the clock signal C
Using the counter 30 ₁ to 30 ₄ which counts ₀ as a clock phase shifting circuit, by resetting control this
As was to replace the divided outputs of the phase, but if the reset control the counter is divided by the counter a high frequency signal than the clock signal C _0, it is possible finer phase adjustment is. Further, instead of the counter, a voltage-controlled oscillator that oscillates a signal having the same frequency as the frequency-divided signal Ca is used, and the phase of the output signal of the voltage-controlled oscillator is controlled in accordance with the output of the phase comparison circuit. Of the clock signals C ₁ ′ to C ₄ ′ with respect to the frequency-divided signal Ca may be locked within a set range. In the above embodiment, the clock signal C
₀ Although not output the divided signal to each counter 30 as a clock signal to the pattern generator, as the signal multiplexing apparatus 20 'shown in FIG. 4, in place of the counter 30 ₁ to 30 _4, the multiplexer circuit using a clock phase shifting circuit 40 ₁ to 40 ₄ for varying the phase of the output signal of the counter 26 for switching the 27, the clock phase shift circuit 40 _1-4
0 ₄ phase shift amount, may be controlled by the control circuit 50 ₁ to 50 _4. In this case, the clock phase shift circuit 4
0 _{1-40 4} can be used as the structure for varying the line length by on-off control of objects or structures which vary the mechanical line length by the rotation control of the motor, the electronic switch (e.g. diode switch) . Although the above embodiment has been described with reference to the case where the number of series n is 4, even when the number of series n is 2, 8 or 16, etc., the clock phase shift circuit, the phase comparison circuit, and the control circuit are replaced by the number of series. If provided, each data signal can be correctly multiplexed as described above. As described above, the signal multiplexing device of the present invention provides a frequency-divided signal obtained by dividing the clock signal output from the clock signal generator, and a data signal from each pattern generator. The phase of the clock signal for each pattern generator is independently variably controlled so as to compare the phases with the clock signal input together with the signal and to make the phase difference fall within a preset range. I have. Therefore, it is not necessary to strictly measure the delay time of each of the pattern generators, and it is not necessary to perform a complicated operation of accurately producing a cable corresponding to the delay time.
The multiplexing of data signals input from each pattern generator can be performed without taking into account any delay time inside the pattern generator, its variation, and the length of the cable connected to the pattern generator. Can do it correctly.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of one embodiment. FIG. 4 is a block diagram showing another embodiment of the present invention. FIG. 5 is a block diagram of a conventional device. FIG. 6 is a timing chart for explaining the operation of the conventional device. ₁ to 1 ₄ pattern generator 20 signal multiplexing apparatus 25 clock signal generator 26 counter 27 the multiplexer circuit 30 ₁ to 30 ₄ counter 31 _{1-31 4} phase comparator 32 _{1-32 4} judging circuit 33 _to 333 ₄ reset signal generator circuit

Claims (1)

(57) [Claims] A plurality of pattern generators (1)₁~ 1_nSupply)
A plurality of clocks for outputting a first clock signal
Output terminal (21₁~ 21_n)When, Provided in correspondence with each of the clock output terminals,
A plurality of pattern generators receiving the first clock signal;
LaOutput at the same frequency as the first clock signal.
EmpoweredMultiple clocks for inputting the second clock signal
Lock input terminal (22₁~ 22_n)When, Provided in correspondence with each of the clock output terminals,
A plurality of pattern generators receiving the first clock signal;
Output in synchronization with the second clock signal.
Data signal (D₁~ D_n) To enter each
Multiple data input terminals (23₁~ 23_n)When, A third clock signal (C₀) To output
A lock signal generator (25); From each of the pattern generators through each of the data input terminals
A plurality of input data signals are generated from the clock signal.
Multiplexing in synchronization with the third clock signal output from the creature
A multiplexer circuit (27) for converting and outputting A third clock output from the clock signal generator
SignalA number equal to the number of sequences of the plurality of data signals
(N)A frequency divider (26) for frequency division; Provided in correspondence with each of the clock output terminals,
Input to each clock input terminal from each pattern generator
The second clock signal (C₁'~ C_n') And the minute
The phase difference from the frequency-divided signal (Ca) output from the
A plurality of phase comparison circuits (31₁~ 31_n)
When, Provided in correspondence with each of the clock output terminals,
At the same frequency as the frequency-divided signal output from the frequency divider,
Clock signal whose phase can be changed (C₁~ C_n)
From each clock output terminal as a first clock signal
Multiple clocks each outputting to the corresponding pattern generator
Phase shift circuit (30₁~ 30_n)When, Provided in correspondence with each of the clock output terminals,
Each phase difference detected by each of the phase comparison circuits is
Each of the clocks so as to fall within a preset range.
The phase shift amount of the phase shift circuitcontrolControl circuits (32₁~
32_n, 33₁~ 33_n) And, The plurality of control circuits include a frequency divider output from the frequency divider.
Multiplexed by the multiplexer circuit within one cycle of the signal.
The second data signals respectively corresponding to the data signals
Data of the clock signal whose multiplexing order is first
A second clock signal corresponding to the divided signal corresponds to the divided signal.
Phase within the predetermined range, and the multiplexing
A second clock signal corresponding to the data signal of
The signal has a lag phase within a predetermined range, and other data
The second clock signal corresponding to the data signal is the frequency-divided signal.
So that each of the clock phase shift circuits is shifted in phase.
Characterized in that it is configured to control the phase amount
Signal multiplexing equipment.