JP3401521B2 - Information processing device having error status display function - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is applicable to, for example, a LAN (LA).
N: Local Area Network (WAN) line and WAN (WAN: Wide)
Area network) The present invention relates to a line control device for performing line control between lines, other communication control devices, an information processing device having an error status display function that can be used for consoleless personal computers and the like.

In recent years, many information processing apparatuses have become consoleless due to downsizing and cost reduction. Even if an error occurs, a console is connected and the content of logging data is analyzed in order to analyze the content of the error. Had to analyze.

Particularly, in an apparatus having an automatic restart (automatic restart) function, even if an error occurs, the error is automatically recovered by the automatic restart by software, and therefore the error content is confirmed. Is becoming difficult,
There has been a demand for improvement in this respect.

[0004]

2. Description of the Related Art A conventional example of a line control device for controlling a line between a LAN line and a WAN line will be described below.

§1: Description of the configuration of the line control device--see FIG. 13 FIG. 13 is a configuration diagram of a conventional example. The line control device 1 of the conventional example receives data on a LAN line and converts the data into WAN line data, and then transmits the converted data to the WAN line, or receives the data on the WAN line and LA.
Converted to N line data and converted data to LAN
It is transmitted to the line.

The line controller 1 includes a CPU 3, a power supply unit 4, a reset generator 5, a RAM 6, a WAN controller 7, a LAN controller 8, a console controller 9, a flexible disk unit (floppy disk unit,
FD unit) 10, flexible disk controller (floppy disk controller, FD controller) 11, ROM 1
2, disk control unit 13, disk device 14, error monitoring unit 15, buzzer 16, operation panel control unit 1
7, an operation panel 18 and the like are provided.

The operation panel 18 is provided with an error lamp 20, a status display lamp including a system ready lamp 21, a reset switch (reset SW) 19 and the like.

A public line or a dedicated line is connected to the WAN controller 7 and an LA controller 8 is connected to the LAN controller 8.
N lines are connected and each line is controlled. Furthermore, a console such as a personal computer (PC) can be connected to the console control unit 9 if necessary (normally, the console is not connected).
Functions and the like of the above-mentioned respective parts are as follows.

(1): The CPU 3 executes various programs to perform various controls in the line control device 1. (2): The power supply unit 4 supplies power to each part of the line control device 1.

(3): The reset generator 5 generates a soft reset signal according to an instruction (I / O access instruction) from the CPU 3 when performing a soft reset (reset in the apparatus by software).

(4): The RAM 6 is a memory accessed by the CPU 3, and is an application program (line control program, etc.) stored in the disk device 14.
It is also used to load various initial setting parameters and the like.

Further, the RAM 6 stores logging data for analyzing error contents and the like. The logging data is saved in a disk before the power is cut off or before automatic restart (automatic restart) is performed.

(5): The WAN controller 7 controls the WAN line. (6): The LAN control unit 8 controls the line of the LAN. (7): The console control unit 9 controls a console such as a personal computer (PC). The console is not connected during normal operation,
It is connected as needed when an error occurs.

(8): Flexible disk unit 10
Drive a flexible disk medium. (9): The flexible disk control unit 11 controls the flexible disk unit 10.

(10): The ROM 12 is a memory accessed by the CPU 3, and includes a self-diagnosis program, an IPL (Init
Various programs such as ial program loader) are stored in advance.

(11): The disk controller 13 controls the disk device 14. (12): The disk device 14 drives and controls a disk medium (such as a magnetic disk and a magneto-optical disk) to write / read data. The disk medium of the disk device 14 stores an application program such as a line control program and various parameters for initial setting, or is used to save logging data stored in the RAM 6. .

(13): The error monitoring unit 15 has an error (failure).
When the error is detected, the CPU 3 is notified of the error, and an error signal of high level H is sent to the operation panel control unit 17 to notify the occurrence of the error.

In this case, the error monitoring section 15 is provided with a flip-flop circuit for setting a system ready lamp signal indicating the operating state (operating / starting state) of the system (line control device). The output (high level H / low level L) of this flip-flop circuit is sent to the operation panel control section 17 as a system ready lamp signal.

The state of the flip-flop circuit can be set by the error monitoring unit 15 or the CPU 3, and its output is high level H during system operation.
At other times (during self-diagnosis, during device initialization processing such as during system initialization, etc.), low level L is set.

Further, the error monitoring unit 15 constantly sends an error signal to the operation panel control unit 17. When no error is detected, a low level L error signal (a signal indicating a no error state) is sent. Then, when an error is detected, a high level H error signal (a signal indicating an error occurrence state) is transmitted.

(14): The buzzer 16 is driven on / off by the operation panel control unit 17,
It sounds when an error occurs. (15): The operation panel control unit 17 operates the operation panel 18 based on the signal from the error monitoring unit 15.
Various controls (ON / OFF control of the system ready lamp 21, ON / OFF control of the error lamp 20, etc.) are performed.

(16): Reset switch (reset SW)
Reference numeral 19 denotes a switch operated by the operator, which is used, for example, when operated to turn off the error lamp after an error occurs. The reset switch 19 is normally off and is turned on only when the operator pushes it. For example, when the reset switch 19 is on, it outputs a high-level H reset signal, and when it is off, it is low-level L. Output a signal.

(17): The error lamp 20 is a status display lamp for notifying the operator of the occurrence of an error. (18): The system ready lamp 21 is a status display lamp for notifying the operator that the device is in the ready state (system operating state or operating state).

§2: Process description of line control device--FIG. 1
4 Reference FIG. 14 is a processing flowchart of a conventional example. Hereinafter, the processing of the line control device will be described with reference to FIG. Note that S1 to S19 indicate each processing step. The line control device 1 is also referred to as a system.

First, when power is turned on by the power supply unit 4 (S1), power is supplied to each part in the system. Next, the CPU 3 sets the system ready lamp signal = 0 (low level L) in the flip-flop circuit of the error monitoring unit 15 to start the self-diagnosis. Therefore, the system monitor lamp signal of low level L is sent from the error monitoring unit 15 to the operation panel control unit 17. When the system ready lamp signal becomes low level L, the operation panel control unit 17 turns off the system ready lamp 21 and turns off the light (S2).

After that, the CPU 3 carries out self-diagnosis by the self-diagnosis program in the ROM 12 (S3). This self-diagnosis is, for example, a process of confirming that an error does not exist and a process of pseudoly generating an error and confirming that the error occurs.

If an error (not a pseudo-generated error but an unpredicted error) occurs in the self-diagnosis (S4), the error monitoring unit 15 detects the error and the CPU 3
Error notification is sent to the operation panel control unit 17, and an error signal of high level H (a signal indicating that an error has occurred) is sent to the operation panel control unit 17.

In response to this error signal, the operation panel control unit 17 turns on the buzzer 16 to make it sound, and turns on the error lamp 20 to turn it on (S5).
Notify the operator of the error occurrence. After that, the CPU 3 that has received the error notification determines that it is a fatal error at the initial stage of power-on and stops the subsequent operation (S6).

If no error occurs in the self-diagnosis (S4), the CPU 3 gives an instruction to the disk controller 13 to display the line control program on the disk in the disk device 14 and parameters for initial setting. read out.
Then, the CPU 3 expands the read line control program on the RAM 6, reads the parameters on the RAM 6 and performs setting processing, and also activates the line control program to perform system initialization (S7).

When the line control program normally starts up, the CPU 3 recognizes that the system initialization has been completed, and sets the system ready lamp signal = 1 (high level H) in the flip-flop circuit of the error monitoring unit 15. .

With this setting, a high level H system ready lamp signal is sent from the error monitoring section 15 to the operation panel control section 17, so that the operation panel control section 17 turns on the system ready lamp 21 and lights it (S8). . The system is operated in this state (S9). The logging data during system operation is C
The PU 3 stores it in the RAM 6.

If no error occurs during system operation (S10), the system operation is continued, but if an error occurs, the error monitoring unit 15 detects the error and notifies the CPU 3 of the error. At the same time, the error signal of high level H is sent to the operation panel control unit 17. In the operation panel control unit 17, the buzzer 16 is turned on to sound by the error signal of the high level H, and the error lamp 20 is turned on to light (S11).

After that, the CPU 3 carries out a retry process for recovering the fault causing the error (S12). Then, when the error is recovered by the retry processing (S13), the error monitoring unit 15 sets the flip-flop circuit to set the operation panel control unit 1
The error signal sent to 7 is set to low level L.

Therefore, the operation panel control unit 1
7 turns off the buzzer 16 to stop the ringing, and turns off the error lamp 20 to turn off the light (S14),
System operation is continued (S9).

However, when the failure cannot be recovered by the retry processing (S13), the CPU 3 reads the logging data stored in the RAM 6 and reads the data from the disk controller 1.
3, the disk controller 13 is instructed to write the logging data to the disk (storage medium) of the disk device 14 and save it (S15). After that, the CPU 3 resets itself and automatically restarts (automatic restart) to recover the failure of the device (S1).
6).

When the failure can be recovered by the automatic restart (S17), the error monitoring unit 15 sends an error signal of low level L to the operation panel control unit 17. Therefore, the operation panel control unit 17 turns off the buzzer 16 to stop the ringing, turns off the error lamp 20 (S19), and continues the system operation (S9). However, if the failure cannot be recovered by the automatic restart, the CPU 3 stops the subsequent operation (S18).

The above-mentioned automatic restart (automatic restart)
If the failure is recovered by, the console (for example, personal computer PC) is connected after the system operation time, the logging data saved on the disk is read and analyzed, and it is determined whether the element is deteriorated or not. And take the necessary measures. If recovery from a failure is difficult, immediately connect the console, read the logging data on the disk and analyze it, remove the cause of the failure, and restore the system.

[0038]

SUMMARY OF THE INVENTION The above-mentioned conventional device has the following problems. (1): When an error occurs during system operation, recovery is attempted by retry, but even if it is not recovered by retry, it is usually recovered by automatic restart (automatic restart) processing by software. After recovery from the error, normal system operation continues.

Therefore, even if the error lamp is turned on when the error occurs and the buzzer is sounded, when the error is recovered by the automatic restart, the error lamp and the buzzer are reset, and the maintenance staff etc. I cannot confirm that it has occurred.

For this reason, even if there is a failure, the maintenance staff cannot find the failure, and the small failure gradually develops into a large failure. Finally, the failure suddenly occurs during system operation (from the maintenance staff etc.). Suddenly when I look at it), the response may increase or the system may go down.

Further, in a device in which an external console cannot be connected, it is difficult to analyze what caused the restart (restart) (analysis of logging data). (2): In a device to which an external console can be connected, by periodically monitoring the logging data in the disk and analyzing the presence or absence of automatic restart and error content,
It was prevented that the response time suddenly increased during system operation (when a failure was overlooked) or the system went down. However, in this case, the maintenance person has to carry the console all the time, which is inconvenient.

(3): Even if there is a disk device, the cause of the error could not be specified without connecting the console and analyzing the logging data. Therefore, the maintenance person has to carry the console all the time, which is inconvenient, and also requires troublesome work such as analysis of logging data. Also, it was difficult to realize a completely consoleless system.

(4): It is possible to always connect a console to the line control device in order to analyze an error, but in this case, as many consoles as the number of line control devices are required, which causes a cost increase. It was uneconomical.

The present invention solves such a conventional problem, makes it possible to easily confirm the occurrence of an error and the content of the error without performing periodical analysis of logging data, and also makes it consoleless. The purpose is to realize the device.

[0045]

FIG. 1 is a diagram for explaining the principle of the present invention. The present invention is configured as follows to achieve the above object.

(1): As shown in FIG. 1, an information processing apparatus having an error status display function, an error monitoring section 15 for monitoring an error, a power supply unit 4 for supplying power to each section in the apparatus, Error lamp 20 for displaying error status
-1, 20-2, 20-3, an operation panel 18 having a reset switch 19 and the like, and an error lamp control section 23 for controlling the error lamp are provided.

The error lamp control section 23 has an encoder 31 (encoding means) for encoding the error signal sent from the error monitoring section 15 and a flip-flop circuit FF- for latching the output of the encoder 31.
1, FF-2, FF-3 (register) and drivers DV-1, DV- that drive the error lamps 20-1, 20-2, 20-3 based on the output Q of the flip-flop circuit (register). 2, DV-3 and the power supply unit 4
An OR circuit OR (reset means) for resetting the flip-flop circuit (register) by a power source reset signal from the power switch or a manual reset signal from the reset switch 19 is provided.

An information processing apparatus having an error status display function is constructed as follows. (2): In an information processing device having an error status display function, an error monitoring unit 15 that monitors an error and error lamps 20-1, 20-2, 20- that display the status of the error detected by the error monitoring unit 15. 3 and the error lamp 2
An error lamp control unit 23 for controlling 0-1, 20-2, and 20-3 is provided, and the error lamp control unit 2 is provided.
3 encodes and latches the error information detected by the error monitoring unit 15 only during the system operation, and the error lamps 20-1, 20-2, 2 are based on the latched error information.
Error lamp display driving means (encoder 31, FF-1, FF-) for displaying error information coded by 0-3.
2, FF-3, DV-1, DV-2, DV-3) and a reset signal (manual reset signal from the reset switch 19 and power source reset from the power supply unit 4) based on an artificial operation other than the soft reset signal. The reset means (OR circuit OR) is provided for resetting the latched error information only by a signal).

(3): In the information processing device having the error status display function, the error monitoring unit 15 for monitoring the error
And a plurality of error lamps 20-1, 20-2, 20-3 displaying the status of the error detected by the error monitoring unit 15.
And an error lamp control unit 23 for controlling the error lamp, and the error lamp control unit 23 is
Encoding means (encoder 31) for determining whether the system is in operation and encoding the error information detected by the error monitoring unit 15 only during the system operation, and latching the error information encoded by the encoding means. Registers (FF-1, FF-2, FF-3) and drivers DV-1, DV-2, DV-3 that drive error lamps based on the contents of the registers to display coded error information.
And a reset means (OR circuit OR) for resetting the contents of the register only by a reset signal based on an artificial operation other than the soft reset signal generated during the reset processing by software.

(4): In the information processing device having the error status display function, the error monitoring unit 15 for monitoring the error
And a console control section for controlling the console and outputting a console connection signal according to the connection status of the console, and a plurality of error lamps 20-1, 20 for displaying the status of the error detected by the error monitoring section 15. -2, 2
0-3 and an error lamp control unit 23 for controlling the error lamp, and the error lamp control unit 2
Reference numeral 3 is a coding means (encoder 31) for judging whether or not the system is in operation and coding the error information detected by the error monitoring unit 15 only during the system operation, and an error coded by the coding means. By a register (FF-1, FF-2, FF-3) that latches information and a console connection signal output from the console control unit,
If the console is not connected, the output of the register is selected, and if the console is connected, the output of the encoding means is selected and output, and error lamps 20-1 and 20 based on the output of the selector. -2, 20-
Only the drivers DV-1, DV-2, and DV-3 that drive 3 to display coded error information and the reset signal based on an artificial operation other than the soft reset signal generated during the reset processing by software, Reset means for resetting the contents of the register (OR circuit OR)
Equipped with.

(5): In the information processing apparatus having the error status display function, the error lamp control section 23 is provided with error lamp blinking means for driving the error lamps 20-1, 20-2 and 20-3 to blink. The error lamp blinking means is configured to display a part of the error information by blinking the error lamp.

(6): In the information processing apparatus having the error status display function, the error lamp control section 23 is provided with a soft reset means for resetting the contents of the register by a soft reset signal generated at the time of reset processing by software, and the software. The valid / invalid setting means for setting whether to enable or disable the reset of the register by the soft reset signal in the reset means is provided.

[0053]

The function of the present invention will be described below. (1): Operation 1 ... Operation of the means (1) to (3) In FIG. 1, the encoder 31 (encoding means) includes a hard error signal sent from the error monitoring unit 15 and a system ready lamp signal. (READY LAMP) is input, the input signal is encoded (encoded), and converted into a coded output signal ABC.

In this case, the output signal AB of the encoder 31
C becomes the output signal coded by the state (0/1) of the hard error signal. For example, when the system ready lamp signal = 0 (when the system is not operating), the encoder output signal = ABC = 000 for all input patterns (in this case, no error state is output).

When the system ready lamp signal = 1 (during system operation), ABC = 001 if the error type is a memory parity error, ABC = 010 if a bus parity error, and ABC if the bus time is over.
= 011, AB if memory write protect error
C = 100, A if watchdog timer error
BC = 101, if CPU diagnosis error, ABC = 11
It becomes 0.

Further, the flip-flop circuits FF-1 and F
In F-2 and FF-3 (registers), if the set input is S, the reset input is R, and the output is Q, S = 0, and if R = 0, Q = previous state hold, S = 1. , If R = 0,
If Q = 1, S = 0, R = 1, then Q = 0,
If S = 1 and R = 1, then Q = 1.

The output Q of each flip-flop circuit
Is Q = 0, the drivers DV-1, DV-2, DV-
3 are error lamps 20-1, 20-2, 20-, respectively.
If 3 is turned off and Q = 1, the drivers DV-1, DV
-2, DV-3 are error lamps 20-1, 20-2, 2
Turn 0-3 on.

As described above, the error lamp 20-1,
If the error lamps 20-2 and 20-3 are off, no current flows through the error lamps, and the error lamps are in the off state.
An electric current flows through and lights up.

Therefore, from the OR circuit OR (reset means) to the flip-flop circuits FF-1, FF-2, FF-3.
If the reset signal R = 0 input to
The state (error state) of the output signal ABC can be latched by the flip-flop circuits FF-1, FF-2, FF-3. If the reset signal R is 1, all the contents latched in the flip-flop circuits FF-1, FF-2, FF-3 are reset.

In this way, since the system ready lamp signal = 0 (low level L) is set while the CPU 3 performs the apparatus startup processing (self-diagnosis, system initialization, etc.), the error lamp 20-1 , 20-2, 20-3 are all off and off.

Since the system ready lamp signal is set to 1 (high level H) during system operation, if a hardware error occurs during system operation, the error monitoring unit 1
The error information coded by the error lamp is lit up and displayed by the signal sent from 5. Therefore, the operator can determine the error content from the lighting state of the error lamp.

Thereafter, the operator or the like depresses the reset switch 19 to set the manual reset signal = 0 (low level), or the power source unit 4 resets the power source (manually operates the power source switch). When the power reset signal = 0 (low level), the error lamp is reset, but until then, the coded lighting states of the error lamps 20-1, 20-2 and 20-3 are latched. To be done.

That is, the contents of the register are not reset by automatic restart (automatic restart) by software, and the contents of the register are reset only when a reset signal is input by an artificial operation (operation of a switch or the like). To be done. Therefore, the error content is latched even if the software is automatically restarted during system operation, and the operator can easily confirm the error content from the lighting state of the error lamp.

Therefore, it is possible to easily confirm the occurrence of an error and the content of the error from the lighting state of the error lamp without performing the regular analysis of the logging data as in the conventional case. Further, since the content of the error can be confirmed by the error lamp, it is possible to detect the failure early and take countermeasures against it. Therefore, it is possible to avoid sudden increase in response and system down.

(2): Action 2 ... Action of the means (4) As in the case of the means (4), in the device having the console control section and the selector, when the console is connected to the console control section, the console control is performed. The selector selects the output of the encoder 31 according to the console connection signal from the section. Therefore, the output of the encoder 31 directly drives the driver DV-1,
The DV-2 and DV-3 are operated, and the driver drives the error lamps 20-1, 20-2 and 20-3.

Thus, if the console is connected when an error occurs, the output of the encoder 31 can be detected through. Therefore, it becomes possible to confirm the reset timing or the like caused by the error from the console. The operation when the console is not connected and the console connection signal is at the low level is the same as the above-described operation 1.

In this case, if the console connection signal is low level, the selector is the flip-flop circuit FF-.
Since the outputs of 1, FF-2, FF-3 (register) are selected, the drivers DV-1, DV-2, DV-3 are operated by the output of the flip-flop circuit, and the error lamp 20-1, 20-2 and 20-3 can be driven.

(3): Operation 3 ... Operation of the means (5) In the apparatus having the structure of the means (5), the error monitoring unit 1
When the error lamp 5 detects an error, the error lamp blinking means of the error lamp controller 23 displays a part of the error information by blinking the error lamps 20-1, 20-2, 20-3.

By doing so, since three kinds of information of lighting (continuous lighting), blinking, and extinguishing can be displayed by one error lamp, the amount of information to be displayed becomes large and the error lamp can be effectively used.

Therefore, the number of error lamps can be minimized when there is no or little space for mounting error lamps. Moreover, even with a minimum of error lamps, it is possible to code and display the status of errors that occurred during system operation.

(4): Action 4 ... Action of the means (6) In the device having the means (6), if the soft reset is set to be invalid by the valid / invalid setting means, the soft reset is performed. This is the same as the above-mentioned action 1. However, if the soft reset is enabled by the valid / invalid setting means, the error information latched in the register can be reset by the soft reset signal.

For example, when a test is conducted by a test program during system operation and a soft reset signal is generated, the error information latched in the register is reset by the soft reset means. If you do this,
By supporting the conventional mode, the conventional test program can be used as it is.

For example, a test is performed by an existing test program during system operation, and when an error occurs, the error information is latched in the register. However, since this error information is error information due to the test, if the latch is continued as it is, the system is in operation. It can no longer be distinguished from the original error.

Therefore, after the test by the test program is completed, a soft reset signal is generated to reset the error information of the register. By doing so, correct error information during system operation can always be obtained.

[0075]

2 to 12 are views showing an embodiment of the present invention. Each embodiment applied to the same line control device as the conventional example will be described below with reference to FIGS. In the following description, the line control device will also be referred to as a system.

(Explanation of First Embodiment) The line control device of the first embodiment is an example of a device which does not have a console control section and cannot be connected to a console and which is not equipped with a disk device.

§1: Description of configuration of line control device--see FIG. 2 FIG. 2 is a configuration diagram of the line control device of the first embodiment. This line control device is a line control device that performs line control between a LAN line and a WAN line, receives LAN line data, converts it to WAN line data, and sends the converted data to the WAN line. Alternatively, the data of the WAN line is received and converted into the data for the LAN line, and the converted data is transmitted to the LAN line.

As shown in the figure, the line controller 1 has a CP
U3, power supply unit 4, reset generator 5, RAM 6,
WAN controller 7, LAN controller 8, flexible disk unit (floppy disk unit, FD unit) 10, flexible disk controller (floppy disk controller, FD controller) 11, ROM 12, flash memory (FLASH memory) 25, error Monitoring unit 1
5, a buzzer 16, an operation panel control unit 17, an operation panel 18, etc. are provided.

Further, the error monitoring section 15 is provided with a flip-flop circuit (FF) 33 for setting the system ready lamp signal. Further, the operation panel 18 includes error lamps 20 (a plurality), a system ready lamp 21, and a reset switch (reset SW) 1.
9, resistors R (plurality) and the like are provided. And the W
A public line or a dedicated line is connected to the AN control unit 7,
A LAN line is connected to the LAN control unit 8 and each line is controlled. Functions and the like of the above-mentioned respective parts are as follows.

(1): The CPU 3 executes various programs to perform various controls in the line control device 1. (2): The power supply unit 4 supplies power to each part of the line control device 1, and outputs a power supply reset signal according to the state of the power supply. The power reset signal is a signal generated based on the operation of the power switch, and is at a high level H from the time the power is turned on until the power supply voltage reaches the circuit operation guarantee voltage, and then the power supply voltage guarantees the circuit operation. During normal operation while maintaining voltage (during normal operation)
Is a low level L, and is a high level H when the power supply voltage drops after the power is turned off and the power supply voltage deviates from the operation guarantee voltage.

(3): The reset generating unit 5 outputs the I
A reset signal (soft reset signal) is generated by the / O access instruction. (4): The RAM 6 is a memory accessed by the CPU 3, and loads the line control program, parameters, etc. stored in the flash memory 25. Further, the RAM 6 is for the CPU 3 to store logging data.

(5): The WAN control unit 7 performs WAN line control and the like. (6): The LAN control unit 8 controls the line of the LAN. (7): The flexible disk unit (floppy disk unit) 10 drives a flexible disk medium. When saving the logging data stored in the RAM 6, the data is stored in a flexible disk (storage medium) inserted in this flexible disk unit and saved.

(8): The flexible disk control section (floppy disk control section) 11 controls the flexible disk unit 10. (9): The ROM 12 is a memory accessed by the CPU 3, and stores programs such as a self-diagnosis program and an IPL.

(10): The flash memory 25 stores application programs such as a line control program and parameters for initial setting in advance.

(11): The error monitoring unit 15 monitors the error that has occurred in the device, detects the error when it occurs, notifies the CPU 3 of the error, and sends an error signal to the operation panel control unit 17 To be sent to.

In this case, the error monitoring unit 15 is provided with a flip-flop circuit 33 for setting a system ready lamp signal indicating the operating state (operating / starting state) of the system (line control device). The output (high level H / low level L) of the flip-flop circuit 33 is sent to the operation panel control section 17 as a system ready lamp signal.

The state of the flip-flop circuit can be set by the error monitoring unit 15 or the CPU 3, and its output is high level H during system operation.
At other times (during self-diagnosis, during device initialization processing such as during system initialization, etc.), low level L is set.

Further, the error monitoring unit 15 constantly sends an error signal to the operation panel control unit 17, and when no error is detected, a low level L error signal (a signal indicating a no error state) is sent. Then, when an error is detected, a high level H error signal (a signal indicating an error occurrence state) is transmitted.

(12): The buzzer 16 is driven on / off by the operation panel controller 17.
It sounds when an error occurs. (13): The operation panel control unit 17 performs various controls of the operation panel 18.

(14): Reset switch (reset SW)
A switch 19 is operated by an operator (maintenance staff or the like) and generates a manual reset signal. For example, when the reset switch 19 is pressed, it is turned on and outputs a high level H (+ 5V) manual reset signal to the operation panel control unit 17.
Further, when the reset switch 19 is released, it is turned off and the operation panel control unit 17 is set to the low level L.
The signal of (0V) is output.

(15): A plurality of error lamps 20 are provided, and in this example, they are composed of a plurality of light emitting diodes. The error lamp 20 is turned on / off by the operation panel control unit 17, and is for notifying an operator (maintenance staff, etc.) of the error state by performing a coded error display when an error occurs. .

(16): The system ready lamp 21 is turned on / off by the operation panel control unit 17 based on the system ready lamp signal from the error monitoring unit 15, and is turned on when the system (apparatus) is operated. It lights up) and turns off (lights out) at other times.

§2: Explanation of processing by flowchart
..Refer to FIG. 3 and FIG. 4. FIG. 3 is a processing flowchart of the first embodiment (part 1), and FIG.
3 is a processing flowchart (Part 2) of the first embodiment. Hereinafter, the processing of the line control device will be described with reference to FIGS. Note that S31 to S50 indicate processing steps.

First, when power is turned on by the power supply unit 4 (S31), power is supplied to each part in the system (apparatus). Next, the CPU 3 starts self-diagnosis,
The system ready lamp signal = 0 (low level L) is set in the flip-flop circuit 33 of the error monitoring unit 15.

By setting the system ready lamp signal = 0, the system monitor lamp signal = 0 is sent from the error monitoring section 15 to the operation panel control section 17. Therefore, the operation panel control unit 17 turns off the system ready lamp 21 and turns off the light (S3).
2).

After that, the CPU 3 carries out self-diagnosis by the self-diagnosis program in the ROM 12 (S33). This self-diagnosis is, for example, a process of confirming that an error does not exist and a process of pseudoly generating an error and confirming that the error occurs.

If an error (not a pseudo-generated error but an unpredicted error) occurs in the self-diagnosis (S34), the error monitoring unit 15 detects the error and the CPU
3 is notified of an error, and an error signal of high level H (a signal indicating that an error has occurred) is sent to the operation panel control unit 17.

In response to this error signal, the operation panel control unit 17 turns on the buzzer 16 to make it sound (S3
5) Notify the operator of the error occurrence. After that, the CPU 3 that has received the error notification determines that the error is a fatal error at the initial stage of power-on and stops the subsequent operation (S3
6).

However, if no error occurs in the self-diagnosis (S34), the CPU 3 performs system initialization (S37). In this system initial setting, the CPU 3 reads the line control program and various parameters for initial setting on the flash memory 25, expands them on the RAM 6, and then reads the parameters on the RAM 6 for initial setting and executes the line control program. Initialize the system by starting it.

In this way, when the line control program is normally started up by the system initialization, the CPU
3 recognizes that the system initial setting is completed, and sets the system ready lamp signal = 1 (high level H) to the flip-flop circuit 33 of the error monitoring unit 15.

When the system ready lamp signal becomes 1 in this way, the system ready lamp signal of high level H is sent from the error monitoring unit 15 to the operation panel control unit 17. Therefore, the operation panel control unit 17 turns on the system ready lamp 21 to turn it on (S38). Then, system operation (normal system operation) is performed (S39). During system operation,
The CPU 3 stores the logging data in the RAM 6.

During the system operation, the error monitoring unit 15 monitors whether an error (hard error) has occurred (S
40), if no error occurs, the system operation is continued (S39).

However, when an error occurs during system operation (S40), the error monitoring unit 15 detects the error and notifies the CPU 3 of the error, and at the same time, the operation panel control unit 17 outputs an error signal corresponding to the detected error content. Send to.

As described above, when an error occurs when the system ready lamp signal sent from the error monitoring unit 15 to the operation panel control unit 17 is 1 (high level H), the operation panel control unit 17 causes the error monitoring unit 15 to operate. The error state is latched by encoding the error signal sent from the device, and the error lamp 20 is driven to display the error (S41).

At this time, when the CPU 3 recognizes the error state by the error notification from the error monitoring unit 15,
The operation panel control unit 17 is instructed to turn on the buzzer 16 to make it sound (S42). Then CP
U3 retries to recover from the failure (S4
3) Then, it is judged whether or not the failure is recovered by the retry (S44).

As a result, when the failure is recovered by the retry, the CPU 3 gives an instruction to the operation panel control unit 17, turns off the buzzer 16 and stops the ringing (S4).
5) The system operation is continued (S39).

However, if the failure is not recovered by the retry, the CPU 3 transfers the logging data in the RAM 6 to the flexible disk control unit 11 and issues an instruction to the flexible disk control unit 11 to send the RA data.
The logging data on M6 is written to the flexible disk (floppy disk storage medium) and saved (S4
6).

After that, the CPU 3 resets the software and performs an automatic restart (automatic restart) process (S47), and determines whether or not the error (fault) is recovered (S48). As a result, when the error (fault) is recovered, the CPU 3 gives an instruction to the operation panel control unit 17 to turn off the buzzer 16 to stop the ringing (S5).
0), the system operation is continued (S39). However, when the failure is not recovered by the automatic restart, the CPU 3 stops the subsequent operation (S49).

§3: Detailed Configuration of Operation Panel Control Unit and Operation Panel ... See FIG. 5 FIG. 5 is a detailed configuration diagram of the operation panel control unit and the operation panel of the first embodiment. The detailed configurations of the operation panel control unit and the operation panel of the line control device shown in FIG. 2 are as shown in FIG. The system ready lamp 21 of the operation panel 18 is omitted in FIG.

As shown in the figure, the operation panel control unit 17 is provided with an error lamp control unit 23, and the error lamp control unit 23 has an encoder 31, an OR circuit OR, and a flip-flop circuit FF-1. , FF-
2, FF-3 and drivers DV-1, DV-2, DV-
3 is provided. Further, the operation panel 18 includes light emitting diodes LED-1, LED-2, LED-
3, a reset switch (reset SW) 19, a plurality of resistors R and the like are provided. Functions and the like of the above-mentioned respective parts are as follows.

(1): The encoder 31 is the error monitoring unit 1
A hardware error signal (hardware error signal) from 5 and a system ready lamp signal (READY LAMP) are input and coded, and the coded ABC signal is output (coding means).

In this case, the hardware error signal sent from the error monitoring unit 15 to the encoder 31 may be a memory parity error, a bus parity error, a bus time over, a memory write protect error, a watchdog timer error, a CPU diagnostic error, or the like. is there.

Also, the system ready lamp signal is
Flip-flop circuit (FF) 33 of the error monitoring unit 15
Output signal (1: during system operation, 0: during system operation such as during system startup),
Alternatively, it is set by the error monitoring unit 15.

(2): The OR circuit OR is a manual output from the reset switch 19 of the operation panel 18 and a power supply reset signal output from the power supply unit 4 based on the operation of the power switch by the operator (maintenance staff, etc.). It is a device (reset means) that outputs a logical sum signal of the reset signals.

In this case, the power supply reset signal is at a high level H (H = 1) from power-on until the power supply voltage reaches the circuit operation guarantee voltage, and thereafter the power supply voltage maintains the circuit operation guarantee voltage. Low level L during normal operation
(L = 0), which is a signal which becomes a high level H (H = 1) when the power supply voltage drops after the power is turned off and the power supply voltage deviates from the operation guarantee voltage.

(3): Flip-flop circuits FF-1 and F
F-2 and FF-3 are for latching the coded error information output from the encoder 31 (register), and set the output signal ABC of the encoder 31 to the set input S
And the output signal of the OR circuit OR is used as the reset input R.

(4): Drivers DV-1, DV-2, DV
-3 is a flip-flop circuit FF-1, FF-2, F
Based on the output signal Q of F-3, the light emitting diode LED-
1, LED-2 and LED-3 are turned on / off to be turned on / off. In addition, light emitting diode LED
When -1, LED-2, and LED-3 are turned on, a current flows from the 5V power supply through the resistor R to each of the light emitting diodes.

(5): Light emitting diode LED-1, LED
-2, LED-3 are drivers DV-1, DV-2, D
It is driven on / off by V-3 and is for displaying an error state coded. The light emitting diodes LED-1, LED-2, and LED-3 constitute the error lamp 20.

(6): The reset switch 19 outputs a manual reset signal to the OR circuit OR of the operation panel control section 17 when operated by an operator (maintenance staff or the like). In this case, the reset switch 19 is normally off, and the signal of low level L (L = 0V) is output from the GND via the resistor R. A current flows through the two resistors R and outputs a high level H signal.

§4: Operation panel control unit and operation panel operation description: see FIGS. 5 and 6 FIG. 6 is an explanatory diagram of FIG. 5, and FIG. 6A is an encoder truth table / LED output result, and FIG. The figure shows a flip-flop circuit (F
It is a truth table of F). Hereinafter, referring to FIG. 6, FIG.
The operation of the operation panel control unit and the operation panel shown in FIG.

The encoder 31 provided in the operation panel control section 17 has a hardware error signal sent from the error monitoring section 15 and a system ready lamp signal (READ
Y LAMP) is input, the input signal is encoded (encoded), and converted into a coded output signal ABC.

In this case, if the output signal of the encoder 31 is ABC as shown in FIG. 6A, the ABC becomes an output signal coded according to the state (0/1) of the hard error signal. For example, system ready lamp signal =
When 0 (when not operating the system), the encoder output signal = ABC = 000 for all input patterns (error information is not output in this case).

When the system ready lamp signal = 1 (during system operation), if there is no error, ABC = 00.
0, AB if the error type is memory parity error
C = 001, ABC = 01 if there is a bus parity error
0, ABC = 011 if bus time is over, ABC = 100 if memory write protect error, ABC = 101, C if watchdog timer error
If it is a PU diagnosis error, ABC = 110.

Flip-flop circuits FF-1, FF-
2, FF-3, set input is S, reset input is R,
If the output is Q, the truth table is as shown in FIG. 6B. That is, if S = 0 and R = 0, then Q = previous state hold, if S = 1 and R = 0, then Q = 1, and if S = 0 and R = 1, then Q = 0. Yes, S = 1, R
If = 1 then Q = 0.

Then, each flip-flop circuit FF-
If the outputs Q of 1, FF-2, FF-3 are Q = 0, the drivers DV-1, DV-2, DV-3 turn off the light emitting diodes LED-1, LED-2, LED-3, respectively. , Q = 1, drivers DV-1, DV-2, DV-
3 is a light emitting diode LED-1, LED-2, LED-
Turn on 3.

As described above, the light emitting diode LED-
If 1, LED-2, LED-3 are off, no current flows in the light emitting diode, and the light is off. However, when the light emitting diodes LED-1, LED-2, LED-3 are turned on, the 5V power supply is turned on. A current flows through each of the light emitting diodes via a resistor R, and the light emitting diodes LED-1, LED
-2, LED-3 lights up (emits light).

Therefore, the flip-flop circuit FF-1,
If the reset signal R = 0 input to the FF-2 and FF-3, the state (error state) of the output signal ABC of the encoder 31 is set to the flip-flop circuits FF-1, FF-2, and FF.
It can be latched at -3. If the reset signal R is 1, flip-flop circuits FF-1 and FF-
2. Reset all contents latched in FF-3.

As described above, since the system ready lamp signal = 0 (low level L) is set while the CPU 3 performs self-diagnosis and system initialization (when the system is started), the encoder 31 outputs the error signal code. Light-emitting diodes LED-1, LED-2, LED-
All 3 are off and off.

Since the system ready lamp signal = 1 (high level H) is set during system operation, if a hard error occurs during system operation, an error signal (hard error signal) sent from the error monitoring unit 15 causes , Operation panel 18 light emitting diode LED
The error content coded by -1, LED-2, and LED-3 is lit up (light emission display).

Therefore, the operator (maintenance staff or the like) can determine the occurrence of an error and the content of the error from the lighting state of the light emitting diode. Then, the operator presses the reset switch 19 to set the manual reset signal = 0 (low level), or the power supply unit 4 resets the power supply (based on the operation of the power switch), and the power supply reset signal = 0. (Low level)
Then, the flip-flop circuits FF-1, FF-2,
The FF-3 is reset and the light emitting diode is turned off, but until then, the coded lighting state of the light emitting diode is latched.

As described above, the contents of the flip-flop circuits FF-1, FF-2, and FF-3 are not reset by the automatic restart (automatic restart) by the software, and the artificial operation (switch The contents of the register are reset only when a reset signal is input by the operation. Therefore, the error content is latched even if the automatic restart is performed during system operation, and the operator can easily confirm the error content from the lighting state of the error lamp.

Therefore, it is possible to easily confirm the occurrence of an error and the content of the error from the lighting state of the error lamp without regularly analyzing the logging data as in the conventional case. Further, since the content of the error can be confirmed by the error lamp, it is possible to detect the failure early and take countermeasures against it. Therefore, it is possible to avoid sudden increase in response and system down.

(Explanation of Second Embodiment) The second embodiment is the same as the first embodiment.
This is an example in which a console control unit is added to the line control device, and a console can be connected as necessary. The process description based on the process flowchart of the first embodiment shown in FIGS. 3 and 4 is the same in the second embodiment.

§1: Description of configuration of line control device--see FIG. 7 FIG. 7 is a configuration diagram of the line control device of the second embodiment. As illustrated, the line control device 1 includes a CPU 3, a power supply unit 4, a reset generation unit 5, a RAM 6, a WAN control unit 7, and an L
AN controller 8, console controller 9, flexible disk unit (FD unit) 10, flexible disk controller (FD controller) 11, ROM 12, flash memory (FLASH memory) 25, error monitor 1
5, a buzzer 16, an operation panel control unit 17, an operation panel 18, etc. are provided.

Further, the operation panel 18 is provided with an error lamp 20 (composed of a plurality of light emitting diodes), a system ready lamp 21, a reset switch (reset SW) 19, a plurality of resistors R and the like.
Then, a public line or a dedicated line is connected to the WAN control unit 7, and a LAN line is connected to the LAN control unit 8 to perform line control respectively.

The console control section 9 controls the console when the console is connected.
A console is not normally connected to the console control unit 9, but a console (for example, a personal computer PC) can be connected as necessary. For example, if you connect a console when an error occurs,
It is configured so that the error details can be viewed through.

The console control section 9 outputs a low level L (L = 0) console connection signal to the operation panel control section 17 when the console is not connected, and outputs a high level when the console is connected. Level H (H
= 1) console connection signal is output to the operation panel control unit 17. The operation panel control unit 17 and the console control unit 9
The other configuration is the same as that of the first embodiment.

§2: Detailed Configuration of Operation Panel Control Unit and Operation Panel--See FIG. 8 FIG. 8 is a detailed configuration diagram of the operation panel control unit and operation panel of the second embodiment. The detailed configurations of the operation panel control unit and the operation panel shown in FIG. 7 are as shown in FIG. Note that FIG.
Then, the system ready lamp is not shown.

As shown in the figure, the error lamp control section of the operation panel control section 17 includes an encoder 31 and
OR circuit OR and flip-flop circuits FF-1 and FF
-2, FF-3 and drivers DV-1, DV-2, DV
-3, a selector 32 and the like are provided. Further, the operation panel 18 includes light emitting diodes LED-1, L
ED-2, LED-3 (which constitutes the error lamp 20)
A reset switch 19 and a plurality of resistors R are provided.

The selector 32 has A1, A2, A3
Input of A system, B input of B1, B2, B3, select input S for inputting a select signal (selection signal), and output Q for outputting the selected signal.
1, Q2, Q3 are provided. That is, according to the state (0/1) of the select signal, one of the A system input and the B system input is selected to output Q1, Q2, Q3.
Is configured to.

At the select input S of the selector 32,
Although the console connection signal from the console control unit 9 is input, this console connection signal is a low level L when the console is not connected, but becomes a high level H signal when the console is connected to the console control unit 9. It will be.

The output signal ABC of the encoder 31 is input to the A system input of the selector 32, and the output signals Q of the flip-flop circuits FF-1, FF-2 and FF-3 are input to the B system input. ing. The outputs DV1, Q2, Q3 of the selector 32 drive the drivers DV-1, DV-2,
Operate DV-3 to drive these drivers DV-1, DV-
2. Due to the operation of DV-3, the light emitting diode LED-1,
It is configured to drive LED-2 and LED-3. The configuration other than the selector is substantially the same as that of the first embodiment.

§3: Description of Operations of Operation Panel Controller and Operation Panel ... See FIGS. 8 and 9. FIG. 9 is an explanatory diagram of FIG. The operations of the operation panel control unit and the operation panel shown in FIG. 8 will be described below with reference to FIG.

The truth table of the selector 32 is as shown in FIG. As can be seen from this truth table, when the select signal = 0 (low level L), the selector 32 outputs A
The system input is selected to become outputs Q1, Q2, Q3. Also,
When the select signal = 1 (high level H), the B system input is selected and the outputs become Q1, Q2, Q3.

The outputs Q1 and Q of the selector 32 are
2, drivers DV-1, DV-2, DV- according to Q3
3 operates and each of these drivers DV-1, DV-2,
Light emitting diodes LED-1 and LED- by DV-3
2, LED-3 is driven and the coded error information is displayed.

Therefore, if a console (for example, a personal computer PC) is connected to the console control unit 9, the output of the encoder 31 directly drives the drivers DV-1, D.
V-2 and DV-3 are operated, and light emitting diode LED-
1, LED-2, LED-3 can be driven.

For example, if a console is connected when an error occurs, the output of the encoder 31 can be detected through.
Therefore, it becomes possible to confirm the reset timing or the like caused by the error from the console.

The operation when the console is not connected and the console connection signal is at the low level L is the same as the operation of the first embodiment. In this case, if the console connection signal is at the low level L, the selector 32 inputs the B system, that is, the flip-flop circuits FF-1 and FF-.
Since the outputs of 2 and FF-3 are selected, the drivers DV-1, DV-2 and DV-3 are operated by the outputs of the flip-flop circuits FF-1, FF-2 and FF-3, and the light emitting diode LED -1, LED-2, LED-3 can be driven.

(Explanation of Third Embodiment) In the third embodiment, when the error occurs, the light emitting diodes are displayed in combination with lighting (continuous lighting) and blinking, so that the number of light emitting diodes for displaying the cause of the error is minimized. In this example, even if the mounting space of the light emitting diode is small, it is possible to sufficiently cope with the situation.

The block diagram of the line control device of the first embodiment shown in FIG. 2 and the processing flowchart of the first embodiment shown in FIGS. 3 and 4 are the same in the third embodiment. §1: Detailed description of the operation panel control unit and the operation panel in the line control device
-Refer to FIG. 10 FIG. 10 is a detailed configuration diagram of the operation panel control unit and the operation panel of the third embodiment.

In the third embodiment, the error lamp control section of the operation panel control section 17 includes an encoder 31, OR circuits OR, OR-1, OR-2, and flip-flop circuits FF-1, FF-2, FF-. 3, FF-4 and AND circuits AND-1, AND-2, AND-3, AND-
4, drivers DV-1, DV-2, and an oscillator (OS
C) 34 and the like are provided.

The operation panel 18 also includes light emitting diodes LED-1 and LED-2 (error lamp 2
0)), a reset switch 19, and a plurality of resistors R and the like. The oscillator (OSC) 34 blinks the light emitting diodes LED-1 and LED-2, and is composed of an oscillator that outputs a pulse of a constant cycle (for example, 1 second).

The connection state of each part is as follows. The encoder 31, AND circuits AND-1 and AND-2 are connected to the error monitoring unit 15, and the OR circuit OR is the power supply unit 4
And a reset switch 19 on the operation panel 18.

In this case, a hard error signal and a system ready lamp signal are input from the error monitoring unit 15 to the operation panel control unit 17. Further, a power supply reset signal is input from the power supply unit 4 to the operation panel control unit 17, and a manual reset signal is input from the operation panel 18 to the operation panel control unit 17.

Of the hard error signals, the memory parity error, bus parity error, and bus time over signals are input to the encoder 31, and the watchdog timer error is input to the AND circuit AND-1.
The U diagnosis error is input to the AND circuit AND-2.
The system ready lamp signal is input to the encoder 31, AND circuits AND-1 and AND-2.

The output A of the encoder 31 is connected to the set input S of the flip-flop circuit FF-1, the output B of the encoder 31 is connected to the set input S of the flip-flop circuit FF-2, and the output of the AND circuit AND-1 is connected. The output is connected to the set input S of the flip-flop circuit FF-3, and the output of the AND circuit AND-2 is the flip-flop circuit FF.
-4 is connected to the set input S.

The output of the OR circuit OR is connected to the reset inputs R of the flip-flop circuits FF-1, FF-2, FF-3 and FF-4. The output Q of the flip-flop circuit FF-1 is connected to the driver DV-1 via the OR circuit OR-1, and the output Q of the flip-flop circuit FF-2 is connected to the driver DV-2 via the OR circuit OR-2. Connected.

The output Q of the flip-flop circuit FF-3 is connected to the AND circuit AND-3, the output Q of the flip-flop circuit FF-4 is connected to the AND circuit AND-4, and the output of the oscillator 34 is the AND circuit AND-3. -3, AND
-4 is connected.

The output of the AND circuit AND-3 is connected to the driver DV-1 via the OR circuit OR-1, and the output of the AND circuit AND-4 is connected to the driver DV-2 via the OR circuit OR-2. is doing. Then, the driver DV-
1 drives the light emitting diode LED-1 and drives the driver DV
-2 drives the light emitting diode LED-2.

§2: Description of operation of operation panel control unit and operation panel ... FIG. 10, FIG.
FIG. 11 is an explanatory diagram of FIG. 10, FIG. A shows an encoder truth table, and FIG. B shows an output result of the light emitting diode. Less than,
Operations of the operation panel control unit and the operation panel shown in FIG. 10 will be described with reference to FIG. 11.

In FIG. 11, the LED state is represented by 1 for the lit state and 0 for the extinguished state. In the system ready lamp signal and the encoder output, the high level H is represented by H = 1 and the low level L is represented by L = 0.

In the encoder 31, when the system ready lamp signal = 0, outputs A and B = 00 for all input states.
Is. When the system ready lamp signal = 1, memory parity error = 01, bus parity error = 1
0, bus time over = 11.

The output of the encoder 31 is latched by the flip-flop circuits FF-1 and FF-2, and then the driver DV is passed through the OR circuits OR-1 and OR-2.
-1, DV-2, and sent to drivers DV-1, DV-
2 drives the light emitting diodes LED-1 and LED-2. In this case, the flip-flop circuits FF-1 and FF-
2 according to the state of being latched by the light emitting diode LED-
1, LED-2 is turned on / off, and is turned on / off.

On the other hand, when the system ready lamp signal = 0, the outputs of the AND circuits AND-1 and AND-2 = 0, so in this state, a watchdog timer error,
And the outputs of the flip-flop circuits FF-3 and FF-4 are 0 regardless of the state of the CPU diagnosis error.
Therefore, when the system ready lamp signal = 0, all the light emitting diodes LED-1 and LED-2 are turned off and turned off.

However, when the system ready lamp signal = 1 and the watchdog timer error or the CPU diagnosis error becomes 1, the output of the AND circuit AND-1 or AND-2 becomes 1 and the flip-flop circuit FF- 3 output = 1 or FF-4 output = 1, and the error state is latched.

In this case, AND circuits AND-3, AND
-4, the flip-flop circuits FF-3 and FF-
4 and the output of the oscillator 34 are input, and a logical product signal of both is output. And the AND circuit AND-3,
The output signal of AND-4 is OR circuit OR-1, OR-2.
To the drivers DV-1 and DV-2, and the drivers DV-1 and DV-2 are light emitting diodes LED-1 and
Drive LED-2.

In this way, when the watchdog timer error signal or the CPU diagnostic error signal = 1 is reached, the light emitting diode LED corresponding thereto blinks and emits light. In this case, the light emitting diodes LED-1, LE
The lighting state of D-2 is as shown in FIG. 11B.

As shown in FIG. 11B, when there is no error when the system ready lamp signal = 1, the states of the light emitting diodes LED-1 and LED-2 are 00 (LE
D-1: extinguished, LED-2: extinguished). When a memory parity error occurs, the light emitting diode LED-
1, LED-2 is 01 (LED-1: extinguished, LE
D-2: Lights).

When a system parity lamp signal = 1 and a bus parity error occurs, the states of the light emitting diodes LED-1 and LED-2 become 10 (LED-1: lit, LED-2: unlit), and When the time-out occurs, the states of the light emitting diodes LED-1 and LED-2 become 11 (LED-1: lighting, LED-2: lighting).

Further, when the watchdog timer error occurs when the system ready lamp signal = 1, the states of the light emitting diodes LED-1 and LED-2 blink 10 (LED-1: blinking, LED-2: extinguished). Next, CP
When a U diagnosis error occurs, the light emitting diode LED-1,
The state of LED-2 is 01 blinking (LED-1: extinguished, L
ED-2: flashes).

In this way, since one light emitting diode can display error information in three kinds of states of extinguishing, lighting and blinking, the amount of display information is increased and the light emitting diode can be used efficiently. .

Therefore, since the number of the light emitting diodes LED can be minimized, it is possible to sufficiently cope with the case where the mounting space for the light emitting diodes is not present or is small. Moreover, even with the minimum number of light emitting diodes, it is possible to code and display errors that have occurred during system operation.

(Explanation of Fourth Embodiment) The fourth embodiment is an example in which the error lamp (light emitting diode) can be reset by a soft reset signal. The configuration diagram of the line control device of the first embodiment shown in FIG. 2 and the processing flowchart of the first embodiment shown in FIGS. 3 and 4 are the same in the fourth embodiment.

§1: Detailed description of operation panel control unit and operation panel of the fourth embodiment--see FIG. 12 FIG. 12 is a detailed configuration diagram of the operation panel control unit and the operation panel of the fourth embodiment.

In the fourth embodiment, in the error lamp control section of the operation panel control section 17 described in the first embodiment, setting terminals 35 and 36, a short bar 37 for shorting the setting terminals, an AND circuit AND, A resistor R1 is added, and a soft reset signal output from the reset generation section 5 and setting signals (valid / invalid signals) from the setting terminals 35 and 36 are input to the input of the AND circuit AND to input the AND circuit AND. The output is input to the OR circuit OR, and other configurations are the same as those of the device of the first embodiment.

That is, the operation panel control unit 1
The error lamp control unit 7 includes an encoder 31, an OR circuit OR, and flip-flop circuits FF-1 and FF-.
2, FF-3 and drivers DV-1, DV-2, DV-
3, an AND circuit AND, setting terminals 35 and 36, a short bar 37, a resistor R1 and the like are provided. The setting terminals 35 and 36 and the short bar 37 constitute a valid / invalid setting means.

On the operation panel 18, light emitting diodes LED-1, LED-2, LED-3,
A reset switch 19 and a plurality of resistors R and the like are provided. Although a system ready lamp is provided on the operation panel 18, it is not shown in FIG.

A soft reset signal from the reset generator 5 and setting signals (valid / invalid signals) from the setting terminals 35 and 36 are input to the AND circuit AND, and the AND circuit AND inputs the two inputs. It is configured to output a logical product signal of the signals. Also, AND circuit A
The output of the ND is connected to the reset inputs R of the flip-flop circuits FF-1, FF-2, FF-3 via the OR circuit OR.

When the setting terminals 35 and 36 are not connected by the short bar 37, the setting signal (valid signal) of the high level H (H = 1) from the + 5V power source is input to the AND circuit AND to set. When the terminals 35 and 36 are short-circuited and connected by the short bar 37, a low level L (L = 0) setting signal (invalid signal) is sent to the AND circuit AN.
It is configured to input to D.

Therefore, when the setting terminals 35 and 36 are not connected, the soft reset signal from the reset generator 5 is valid, and when the soft reset signal becomes high level H, the flip-flop circuit FF. −
The latch states of 1, FF-2 and FF-3 are reset.

However, when the setting terminals 35 and 36 are short-circuited and connected by the short bar 37, the soft reset signal becomes invalid, and even if the soft reset signal becomes the high level H, the flip-flop circuit FF.
The latch states of -1, FF-2, and FF-3 are configured not to be reset. The other configuration is the same as the first embodiment.
Is the same as.

§2: Description of operation of operation panel control unit and operation panel ... See FIG. 12 In FIG. 12, when the setting terminals 35 and 36 are short-circuited by the short bar 37, the soft reset signal is invalid. And flip-flop circuits FF-1, FF-2,
Since the latched state of the FF-3 cannot be reset by the soft reset signal, the operation in this case is the same as that of the first embodiment.

When the setting terminals 35 and 36 are not connected by the short bar 37, the soft reset signal becomes valid and the soft reset signal becomes high level H.
Then, the flip-flop circuits FF-1, FF-2,
The latched state of FF-3 can be reset by a soft reset signal. Hereinafter, the operation in the case where the setting terminals 35 and 36 are not connected by the short bar 37 and the soft reset signal is valid will be described.

The encoder 31 inputs the hardware signal sent from the error monitor 15 and the system ready lamp signal (READY LAMP), decodes the input signal, and converts it into the output signal ABC.

In this case, the output signal of the encoder 31 is set to A
With BC, ABC is an output signal coded according to the state of the hard error signal. For example, as in the first embodiment, when the system ready lamp signal = 0, the encoder output signal = ABC = 000 for all input patterns.
Becomes

Further, when the system ready lamp signal = 1, ABC = 000 if there is no error, ABC = 001 if the type of error is a memory parity error, ABC = 010 if a bus parity error, and bus time over. If so, ABC = 011, if watchdog timer error, ABC = 101, and if CPU diagnostic error, ABC = 110.

Flip-flop circuits FF-1 and FF-
2, FF-3, set input is S, reset input is R,
When the output is Q, if S = 0 and R = 0, then Q = previous state hold, and if S = 1 and R = 0, then Q = 1,
If S = 0, R = 1, then Q = 0, S = 1, R = 1
Then, Q = 0.

Then, each flip-flop circuit FF-
If the outputs Q of 1, FF-2, FF-3 are Q = 0, the drivers DV-1, DV-2, DV-3 turn off the light emitting diodes LED-1, LED-2, LED-3, respectively. , Q = 1, drivers DV-1, DV-2, DV-
3 is a light emitting diode LED-1, LED-2, LED-
Turn on 3.

As described above, the light emitting diode LED-
If 1, LED-2, LED-3 are off, no current flows in the light emitting diode, and the light is off. However, when the light emitting diodes LED-1, LED-2, LED-3 are turned on, the 5V power supply is turned on. A current flows through each of the light emitting diodes through the resistor R, and the light emitting diodes light up.

Therefore, the flip-flop circuit FF-1,
If the reset signal R = 0 input to the FF-2 and FF-3, the state (coded error information) of the output signal ABC of the encoder 31 is changed to the flip-flop circuits FF-1 and F.
It can be latched by F-2 and FF-3. If the reset signal R is 1, the flip-flop circuit FF
-1, FF-2 and FF-3 are all reset.

In this way, the CPU 3 performs self-diagnosis and system initial setting (during system startup).
Keeps the system ready lamp signal off (low level L), the light emitting diodes LED-1 and LED-
2. LED-3 is all off and off. Since the system ready lamp is turned on (system ready lamp signal = high level) during system operation, if a hard error occurs during system operation, an error signal sent from the error monitoring unit 15 causes the operation panel 18 to emit light. Diodes LED-1, LED-2,
The error information (error content) coded by LED-3 is displayed.

Therefore, it is possible to judge the error content from the lighting state of the light emitting diode. Then, when a high-level reset signal is output from the OR circuit OR, the flip-flop circuits FF-1, FF-2, FF-3 are reset, and as a result, the light emitting diodes LED-1, L
ED-2 and LED-3 turn off and go out.

The reset signal output from the OR circuit OR becomes high level: When the operator presses the reset switch 19 and the manual reset signal becomes high level H (H = 1): When the power supply reset signal from the unit 4 becomes the high level H (H = 1): The soft reset signal is valid and the soft reset signal from the reset generator 5 is the high level H (H = 1). That is the case.

In the above cases, and, the reset signal output from the OR circuit OR becomes the high level H (H = 1), and the flip-flop circuits FF-1, FF-2, FF-.
3 are all reset, and as a result, the light emitting diodes are also reset, but until then, the coded lighting states of the light emitting diodes LED-1, LED-2, LED-3 are latched.

As described above, the setting terminals 35 and 36 and the short bar 37 are provided so that it can be set whether the soft reset signal is valid or invalid. Therefore, if the soft reset signal is set to be valid by the setting terminals 35 and 36 and the short bar 37, the flip-flop circuit FF can be reset by software.
The error information latched in -1, FF-2, FF-3 can be reset.

In this way, the conventional mode can be supported, and the existing test program can obtain the correct error lamp information even if the error check is performed during the system operation. Therefore, the conventional test program can be used as it is. Can be used.

For example, the shorting bar 37 does not short-circuit between the setting terminals 35 and 36, and the soft reset signal is set to the valid state. In this state, when the system is in operation (system ready lamp signal = 1 state), the existing Suppose you have used a test program to test for error conditions.

In this case, if a pseudo error is generated by the test program, the flip-flop circuit FF-
Error information (pseudo error information) is latched by 1, FF-2, FF-3, and light emitting diodes LED-1, LE
Coded error information is displayed on D-2 and LED-3, but since this error information is not the original error information, it is necessary to reset it after the end of the test.

Therefore, at the end of the test by the test program, the soft reset signal is set to the high level H to reset the error information latched in the flip-flop circuits FF-1, FF-2, FF-3.

After the test is completed, the setting terminal 3
If the short bar 37 is short-circuited between 5 and 36, the soft reset signal becomes invalid, and thereafter, only error information due to normal system operation is latched in the flip-flop circuits FF-1, FF-2, and FF-3. To be done.

When the soft reset signal is set to be invalid, the flip-flop circuits FF-1 and FF-
2. Only true error information when an error occurs is latched in FF-3, and it is not reset by automatic restart (auto restart).

(Other Embodiments) The embodiments have been described above, but the present invention can also be implemented as follows.

(1): Not limited to the line control device, it can be applied to other similar information processing devices (for example, various communication control devices, various control devices, consoleless personal computers, other various computers, etc.).

(2): The error lamp is not limited to the light emitting diode and can be realized by any other lamp. (3): The number of error lamps, etc. can be set to any number. That is, when the number of error types increases or decreases, the number of encoder output signals, the number of flip-flop circuits, the number of drivers, the number of error lamps, etc. can be increased or decreased, and the same operation as in each of the above embodiments can be performed. is there.

(4): In the above embodiment, the flip-flop circuit for setting the system ready lamp signal is provided in the error monitoring section, but the flip-flop circuit is also provided in the error control section of the operation panel control section. It is possible.

(5): It can be also realized by using a switch instead of the setting terminal and the short bar shown in FIG. 12 and mounting the switch on a part of the printed board.

[0207]

As described above, the present invention has the following effects. (1): When an error occurs during system operation, the error information is latched in the error control unit, and the error information coded by the error lamp is displayed based on the latched error information. In this case, since the error information coded by the error lamp is displayed, the content of the error can be determined by the lighting state of the error lamp.

Then, after an error occurs, a retry is performed,
If the error still cannot be recovered, the software will automatically restart to recover from the error. However, the latched error information is not reset by the reset (soft reset) at the time of the automatic restart, and remains latched as it is. Therefore, once an error occurs, the error information is held and the lighting state of the error lamp is held until a reset signal is generated by an artificial operation.

Therefore, even after the automatic restart,
A maintenance person or the like can surely determine that an error has occurred and the content of the error from the lighting state of the error lamp. As a result, the details of the failure can be found at an early stage, and by taking measures against it, it is possible to prevent a sudden increase in the response time and a system down.

(2): The system operation state is automatically determined by hardware, and only for errors that occur in the system operation state, error information is coded and latched, and coded and displayed. Error contents can be retained.

Therefore, the contents of the error can be recognized without collecting the logging data by the console. Therefore, it is not necessary to carry around the console as in the conventional example, and the labor and time required for maintenance are reduced.

(3): Since error information is coded and latched and coded and displayed, the error content can be easily recognized from the lighting state of the error lamp. Therefore, the content of the error can be determined without connecting the console, and the information processing apparatus can be realized without the console.

(4): Error lamp display driving means for coding and latching error information detected by the error monitoring unit only during system operation, and displaying error information coded by an error lamp based on the latched error information And a reset means for resetting the latched error information only by a reset signal based on an artificial operation other than the soft reset signal.

Therefore, even if an error occurs during system operation and a reset (soft reset) is performed by automatic restart, it is possible to continue latching the error state. Then, the error state is not reset until the intervention of a manual operation (power-off, pressing of the reset key), and the operator can recognize the error content from the lighting state of the error lamp.

As a result, the details of the trouble can be found early, and by taking measures against it, it is possible to prevent sudden increase in response time and system downtime.

(5): Coding means for judging whether or not the system is in operation and coding the error information detected by the error monitoring section only during the system operation, and a register for latching the coded error information. , A driver for driving the error lamp based on the contents of the register to display coded error information, and a reset means.

Therefore, even if an error occurs during system operation and a reset (soft reset) is performed by automatic restart, the error state can be continuously latched. Then, the error state is not reset until the intervention of a manual operation (power-off, pressing of the reset key), and the operator can recognize the error content from the lighting state of the error lamp.

As a result, the contents of failure can be found early, and by taking measures against it, it is possible to prevent sudden increase in response time and system down.

(6): Coding means for judging whether the system is in operation or not, and coding the error information detected by the error monitoring unit only during the system operation, and a register for latching the coded error information. , A selector for selecting the output of the register when the console is not connected by the console connection signal and selecting and outputting the output of the encoding means when the console is connected, and an error lamp based on the output of the selector A driver for driving and displaying coded error information and a reset means are provided.

Therefore, if the console is connected when an error occurs, the output of the coding means can be detected through. Therefore, for example, the timing of resetting the cause of the error can be confirmed by the console.

(7): Error lamp of error lamp control unit
The driving means includes blinking, turning on, and turning off the error lamp.
Display error information coded in three different states
Drive like

Therefore, one light emitting diode turns off the light,
Since the error can be displayed in three kinds of states of lighting and blinking, the amount of display information is increased and the light emitting diode can be used efficiently.

As a result, since the number of light emitting diodes LED can be minimized, it is possible to sufficiently deal with the case where there is no or little space for mounting the light emitting diodes. Moreover, even with the minimum number of light emitting diodes, it is possible to code and display errors that have occurred during system operation.

(8): Soft reset means for resetting the contents of the register by the soft reset signal generated during reset processing by software, and whether to enable or disable the register reset by the soft reset signal by the soft reset means It is provided with a valid / invalid setting means for setting.

Therefore, since the conventional mode can be supported and the existing test program can obtain the correct error lamp information even if the error check is performed during the system operation, the conventional test program can be used as it is. it can.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of a line control device according to the first embodiment.

FIG. 3 is a processing flowchart (part 1) of the first embodiment.

FIG. 4 is a processing flowchart (part 2) of the first embodiment.

FIG. 5 is a detailed configuration diagram of an operation panel control unit and an operation panel according to the first embodiment.

FIG. 6 is an explanatory diagram of FIG. 5.

FIG. 7 is a configuration diagram of a line controller according to a second embodiment.

FIG. 8 is a detailed configuration diagram of an operation panel control unit and an operation panel according to the second embodiment.

9 is an explanatory diagram of FIG. 8. FIG.

FIG. 10 is a detailed configuration diagram of an operation panel control unit and an operation panel according to the third embodiment.

11 is an explanatory diagram of FIG. 10. FIG.

FIG. 12 is a detailed configuration diagram of an operation panel control unit and an operation panel according to the fourth embodiment.

FIG. 13 is a device configuration diagram of a conventional example.

FIG. 14 is a processing flowchart of a conventional example.

[Explanation of symbols]

1 Line control device 3 CPU 4 power supply unit 5 Reset generator 6 RAM 9 Console control section 12 ROM 15 Error monitor 17 Operation panel control unit 18 Operation panel 19 reset switch 20 Error lamp 21 System ready lamp 23 Error lamp controller 31 encoder 32 selector 33 Flip-flop circuit (FF) 34 oscillator 35, 36 setting terminals 37 Short Bar

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeshi Niwada 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Yasushi Tanzawa, 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Naoyuki Nishimura 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (56) Reference JP-A-2-231650 (JP, A) Actual development Sho-58-90434 (JP, U) Actual development Sho 59-37641 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 11/32

Claims (3)

(57) [Claims] 1. An error monitoring unit for monitoring an error, an error lamp for displaying an error state detected by the error monitoring unit, and an error lamp control unit for controlling the error lamp , the error lamp control unit. Determines whether the system is operating.
Error detection section detects only during system operation.
A coding means for coding the error information,
A register that latches error information coded by a coding method
And the error lamp is driven based on the contents of the register
Driver that displays error information encoded by
Software reset that occurs during software reset processing
The reset signal based on an artificial operation other than
The reset means for resetting the contents of the register.
In addition to being equipped, the software generated during the reset process by software
A soft reset that resets the register contents with a set signal
And the soft reset signal from the soft reset means
Set whether register reset is enabled or disabled
An information processing apparatus having an error status display function, characterized in that it has a valid / invalid setting means . 2. An error monitoring unit for monitoring an error and a controller.
Controls the sole and depends on the connection status of the console
And a console control unit that outputs a console connection signal,
The error monitor displays the status of the error detected by the error monitor.
Number of error lamps and the error lamp control
With the error lamp control section, the error lamp control means determines whether or not the system is in operation.
Judged and detected by the error monitoring unit only during system operation
Coding means for coding the error information that has been generated,
The register that latches the error information coded by the
And a console output from the console control unit.
If the console is not connected due to
Select the output of the register, and when the console is connected,
Select the output of the encoding means and output
Drive the error lamp based on the output of the selector
Driver that displays error information encoded by
Software reset that occurs during software reset processing
The reset signal based on an artificial operation other than
The reset means for resetting the contents of the register.
An information processing device having an error status display function characterized by being provided . 3. The error lamp controller is configured to control the error.
The lamp can be coded in three states, including blinking, turning on, and turning off.
Error that drives to display the converted error information
A lamp driving means is provided, The said 1st characterized by the above-mentioned.
Alternatively , an information processing apparatus having the error status display function described in 2 .