JP3398079B2 - Peak hold circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak hold circuit used for extracting data superimposed on a video signal in a specific horizontal scanning period.

[0002]

2. Description of the Related Art In the United States, it has been a long time since a television receiver with a built-in closed caption function for displaying subtitles of a conversation of a broadcasting person in real time has appeared on the market so that a deaf person can enjoy television broadcasting. Caption data for displaying subtitles is the 21st horizontal included in the vertical blanking period of the video signal.
It is transmitted in a state of being superposed during the scanning period (21H). More specifically, as shown in FIG. 4, the run-in clock indicating the presence or absence of caption data and the caption data indicating the caption data are transmitted while being continuously superimposed on 21H. Decoding of caption data is performed by detecting the peak voltage at the top of the run-in clock with the pedestal of the video signal clamped to the reference voltage, and then detecting the caption data at the midpoint voltage indicated by the alternate long and short dash line between the reference voltage and the peak voltage. This can be realized by slicing to generate multi-bit data having a logical value of “0” or “1” and loading the multi-bit data into a microcomputer.

Recently, XDS data (EXTENDED DA) for the purpose of providing services to viewers such as time information is also available.
TA SERVICE) is also provided.

FIG. 3 shows an example of a peak hold circuit used when generating the above-mentioned multi-bit data.

In FIG. 3, in the comparison result (101), the run-in clock is applied to the + terminal, and the peak voltage at the top of the run-in clock until immediately before is fed back to the-terminal from the output terminal of the operational amplifier in the subsequent stage. . The comparator (101) is +
Outputs a high level (5 volts) when the input voltage of the terminal is greater than the feedback voltage of the-terminal, and conversely outputs a low level (0 volts) when the input voltage of the + terminal is less than the feedback voltage of the-terminal. To do. The inverter (102) is a comparator (10
Invert the output voltage of 1). The P-type MOS transistor (103) has a gate connected to the output of the inverter (102) and a source connected to the power supply Vdd (5 volts). That is, when the peak voltage at the top of the current run-in clock becomes higher than the peak voltage up to immediately before, the P-type MOS
The transistor (103) becomes conductive according to the low level output of the inverter (102). The resistor (104) and the capacitor (105) are P-type MOS transistors (103)
It is connected in series between the drain and the ground and integrates the output current when the P-type MOS transistor (103) is turned on. The + terminal of the operational amplifier (106) is connected to the connection point of the resistor (104) and the capacitor (105), and the-terminal is connected to the output terminal. That is, the operational amplifier (106) has an output voltage of + from the output terminal to the-terminal.
Feedback is applied to make it equal to the integrated voltage of the terminal, and the peak voltage is output from the output terminal. Specifically, the operational amplifier (1
06) updates the output voltage to a larger value when the peak voltage at the top of the run-in clock becomes higher than the peak voltage immediately before, and the peak voltage at the top of the run-in clock reaches the peak immediately before. When the voltage becomes lower than the voltage, the current output voltage is held. And an operational amplifier (106)
The peak voltage obtained from the output terminal of is the comparator (101)
It is also fed back to the-terminal. That is, the comparator (101) is
The peak voltage at the top of the current run-in clock is compared with the peak voltage updated from time to time immediately before.

The peak hold voltage output from the operational amplifier (106) is divided into ½ by a post-stage circuit (not shown), and caption data, XDS data, etc. are divided into a plurality of bits having logical values “0” and “1”. It becomes a threshold voltage (dotted line in FIG. 4) for discriminating the data.

[0007]

However, in the case of the peak hold circuit of FIG. 3, the resistor (10
It is necessary to set an absolute resistance value and capacitance for the capacitor 4) and the capacitor 105. For example, the resistance (10
It is necessary to set the resistance value of 4) to 1 MΩ and the capacitance of the capacitor (105) to about 20 pF. Therefore, when the circuit of FIG. 3 is integrated, it is difficult to reduce the chip area.

Therefore, an object of the present invention is to provide a peak hold circuit that can reduce the chip area.

[0009]

The present invention was made to solve the above problems, and is a peak hold circuit used when extracting data superimposed on a video signal in a specific horizontal scanning period. Of the operational amplifier and the feedback path between the input and output of the operational amplifier,
A first gate circuit which is closed only during a scanning period and a first capacitor which intervenes in a feedback path between the input and output of the operational amplifier and causes a capacitance change only during the specific horizontal scanning period, and an input on the feedback path side of the operational amplifier are connected. A second capacitor having a smaller capacity than the first capacitor, and a second capacitor interposed between both ends of the second capacitor and the reference input of the operational amplifier, and which is opened and closed periodically in the specific horizontal scanning period. A third gate circuit, which is interposed between an input on the feedback path side of the operational amplifier and one end of the second capacitor, and opens and closes at a timing different from that of the second and third gate circuits in the specific horizontal scanning period. 4 and the gate circuit, interposed between the ground and the other end of said second capacitor, and a fifth gate circuit for opening and closing in the fourth gate circuit and the same timing, before
The output of the operational amplifier and the run-in clock are input.
A comparator, and opens the fourth and fifth gate circuits.
Together with closing the second and third gate circuits
The connection point voltage of the first and second capacitors
According to the capacitance ratio of the first and second capacitors,
Accordingly, the output voltage of the operational amplifier is increased,
The output voltage of the operational amplifier is the top voltage of the run-in clock.
Output level of the comparator when held above the value
In response to the opening of the second and third gate circuits,
The second gate so that the fourth and fifth gate circuits are closed.
A signal for controlling the opening and closing of the fourth to fourth gate circuits should be fixed.
Is used to hold the peak value of the data .

Further, the voltage across the first and second capacitors during the period other than the specific horizontal scanning period is equal to the reference input voltage of the operational amplifier.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The details of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a circuit diagram showing a peak hold circuit according to the present invention.

In FIG. 1, the comparator (1) has the + terminal to which the run-in clock shown in FIG. 4 is applied, the -terminal to which the peak voltage output from the preceding operational amplifier is applied, and the run-in clock is the current one. It is to compare whether or not the peak voltage is exceeded. That is, the comparator (1) outputs a high level (logical value “1”) when the run-in clock is higher than the peak voltage, and a low level (logical value “0”) when the run-in clock is lower than the peak voltage. ) Is output. The control unit (2) outputs the signal 21H, the signal Φ1, and the signal Φ2 according to the output level of the comparator (1).
The signal 21H is a signal that becomes high level during the 21st horizontal scanning period, and the signal Φ1 is a pulse signal or signal that is periodically generated until the peak voltage becomes higher than the run-in clock maximum value during the 21st horizontal scanning period. Φ2 is a pulse signal that is periodically generated at a different timing from the signal Φ1 until the peak voltage becomes higher than the run-in clock maximum value in the 21st horizontal scanning period. Signal Φ1, Signal Φ2
Has a pulse width of, for example, about 200 nsec. The reference voltage Vdd / 2 is applied to the + terminal of the operational amplifier (3). The first transmission gate (4) is a P-type MOS
The drain and source of a transistor and an N-type MOS transistor are connected to each other, and are connected between the negative terminal and the output terminal of the operational amplifier (3). The first transmission gate (4) is controlled to be opened / closed by the signal 21H, turned off in the 21st horizontal scanning period, and turned on in the other horizontal scanning periods. The first capacitor (5) is the − of the operational amplifier (3).
It is connected between the terminal and the output terminal. That is, the operational amplifier (3) operates so that the output voltage is fixed to the pedestal level of the video signal in the horizontal scanning period other than the 21st line,
The voltage across the first capacitor (5) is Vdd / 2.

The second and third transmission gates (6) and (7) are controlled to open / close at the same time by the signal Φ1 and transmit the reference voltage Vdd / 2. One end of the fourth transmission gate (8) is connected to the-terminal of the operational amplifier (3), and opening / closing is controlled by the signal Φ2. One end of the second capacitor (9) has a fourth transmission gate (8)
Connected to the other end of. N-type MOS transistor (10)
Has a drain connected to the other end of the second capacitor (9), a source grounded, and is on / off controlled by a signal Φ2. During the horizontal scanning period other than the 21st line, the signals Φ1 and Φ2 are fixed to the high level and the low level, respectively.
That is, the second and third transmission gates (6)
(7) turns on and the 4th transmission gate (8)
Also, the N-type MOS transistor (10) is turned off. Therefore, the voltage across the second capacitor (9) becomes the reference voltage Vdd / 2.

In the embodiment of the present invention, the capacitance of each of the first and second capacitors (5) and (9) is 1.6 p.
F, 0.1 pF. Also, the first, second, third, fourth
The transmission gates (4) (6) (7) (8) and the N-type MOS transistor (10) correspond to the first, second, third, fourth and fifth gate circuits of claim 1, respectively.

Now, when the 21st horizontal scanning period arrives, the first transmission gate (4) outputs the signal 21H.
It always turns off according to the high level of. That is, the voltage across the first capacitor (5) is released from the fixed state of the reference voltage Vdd / 2 and becomes variable based on external factors. At the same time, the second and third transmission gates (6) and (7) are turned off according to the low level of the signal Φ1. That is, like the first capacitor (5), the voltage across the second capacitor (9) is released from the fixed state of the reference voltage Vdd / 2, and can be changed based on an external factor.
After that, the fourth transmission gate (8) and the N-type MOS transistor (10) are turned on according to the high level of the signal Φ2. At this time, the first and second capacitors (5)
(9) is in a state of being connected in series between the output terminal of the operational amplifier (3) and the ground. From this, the connection point voltage of the first and second capacitors (5) and (9) is initially Vdd / 2, but is divided into 16: 1 according to the capacitance ratio of the first and second capacitors (5) and (9). The pressure drops to Vdd / 34. Along with this, the operational amplifier (3) changes the output voltage to (Vdd / 2-V in order to return the-terminal voltage to the reference voltage Vdd / 2.
increase by dd / 34). At this time, since the first capacitor (5) does not have a discharge path, the output voltage of the operational amplifier (3) is maintained in the raised state. Then the second
And the third transmission gates (6) and (7) are turned on, the fourth transmission gate (8) and the N-type MO
The S transistor (10) is turned off, and the voltage across the second capacitor (9) returns to the reference voltage Vdd / 2. When the above operation is repeated and the output voltage of the operational amplifier (3) is kept higher than the voltage value of the top of the run-in clock,
The output of the comparator (1) changes to the low level, and the control section (2) fixes the signals Φ1 and Φ2 again to the high level and the low level, respectively. The output voltage of the operational amplifier (3) is divided by the voltage divider (11) into an intermediate value between the reference voltage Vdd / 2 and the maximum value and becomes a threshold voltage.

The peak hold operation must be completed at the latest before the arrival of caption data, XDS data and the like. For that purpose, it is only necessary to set the capacitance ratio of the first and second capacitors (5) and (9) to an appropriate value.

As described above, the high resistance (about 1 MΩ) forming the integrating circuit is not required, and the peak hold circuit can be downsized when integrated.

Since the capacitance ratio of the first and second capacitors (5) and (9) determines the peak hold operation, the absolute capacitance as in the conventional case is unnecessary. Therefore, a small-capacity capacitor (about pF) is sufficient, and miniaturization and miniaturization are possible when the peak hold circuit is integrated.

Since the first and second capacitors (5) and (9) are integrated on the same semiconductor substrate, the characteristic variations are uniform. Therefore, the peak hold value does not vary. The above-mentioned effects are produced.

[0021]

According to the present invention, when performing the peak hold operation, high resistance is not required and the absolute capacity of the capacitor is not required. Therefore, when the peak hold circuit is integrated, downsizing and miniaturization are possible. Become. Furthermore, the first and second
If the capacitors are integrated on the same semiconductor substrate, the characteristic variation becomes uniform, and therefore the peak hold value does not vary. Such an advantage can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a peak hold circuit of the present invention.

FIG. 2 is a time chart of signals used in the circuit of FIG.

FIG. 3 is a circuit diagram showing a conventional peak hold circuit.

FIG. 4 is a diagram showing superimposition information in a 21st horizontal scanning period.

[Explanation of symbols]

(1) Comparator (3) Operational amplifier (4) First transmission gate (5) First capacitor (6) Second transmission gate (7) Third transmission gate (8) Fourth transmission gate (9) Second capacitor (10) N-type MOS transistor

Claims (2)

(57) [Claims] 1. A peak hold circuit used when extracting data superimposed on a video signal in a specific horizontal scanning period, wherein the peak hold circuit is interposed between an operational amplifier and a feedback path between an input and an output of the operational amplifier, a first gate circuit to close only a specific horizontal scanning period, interposed in the feedback path between the input and output of the operational amplifier, wherein a first capacitor to produce only the capacitance change certain horizontal scanning period, the feedback path side of the operational amplifier Connected to an input, said first
A second capacitor having a smaller capacity than the capacitor, and second and third gate circuits interposed between both ends of the second capacitor and a reference input of the operational amplifier and periodically opening and closing in the specific horizontal scanning period. A fourth gate circuit interposed between the input on the feedback path side of the operational amplifier and one end of the second capacitor, the fourth gate circuit opening and closing at a different timing from the second and third gate circuits in the specific horizontal scanning period, A fifth gate circuit which is interposed between the other end of the second capacitor and the ground and opens and closes at the same timing as the fourth gate circuit, an output of the operational amplifier and a run-in clock are input.
And a comparator for opening the fourth and fifth gate circuits and opening the second and fifth gate circuits.
And the third gate circuit is closed to close the first and second gate circuits.
The connection point voltage of the second capacitor is set to the first and second capacitors.
Decrease according to the capacity ratio of the capacitor,
The output voltage of the amplifier is increased so that the output voltage of the operational amplifier is at the top of the run-in clock.
When the voltage exceeds the voltage value and is maintained, the output level of the comparator is
Depending on the bell, when the second and third gate circuits open
In order to close the fourth and fifth gate circuits,
Fix the signal that controls the opening and closing of the second to fourth gate circuits
Hold the peak value of the above data.
And a peak hold circuit. 2. The peak hold circuit according to claim 1, wherein a voltage between both ends of the first and second capacitors is equal to a reference input voltage of the operational amplifier except during the specific horizontal scanning period.