GB2378066A

GB2378066A - A zeroed TFT inverter-type comparator with two input capacitors

Info

Publication number: GB2378066A
Application number: GB0117906A
Authority: GB
Inventors: Simon Tam
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 2001-07-23
Filing date: 2001-07-23
Publication date: 2003-01-29
Anticipated expiration: 2021-07-23
Also published as: GB2378066B; US20030016060A1; GB0117906D0; US6628146B2; JP2003204250A

Abstract

A CMOS inverter pair of polycrystalline transistors Q1,Q11 is zeroed prior to comparison by the switch Q6. When zeroing is complete, the input switches Q3 and Q10 are enabled to couple the input signals to the inverter through the capacitors C1 and C2. An output buffer Q5,Q9 and an output holding circuit Q7,C3,Q2,Q12 are provided. The zeroing technique reduces the effect of the large spread in threshold voltages exhibited by TFT devices.

Description

Comparator Circuit and Method The present invention relates to a

comparator circuit and method. Such circuits and methods are, of course, already known. However, the known circuits and methods exhibit a number of disadvantages and the object of the present invention is to provide an improved circuit and method.

A very substantial difficulty experienced in transistor implemented comparator circuits is the variation in threshold voltage which occurs between different transistors. This problem was encountered in the 1 970s and techniques were devised to mitigate the effect of the non-uniformity of the threshold voltage. At that time, of course, the transistor fabrication was nMOS and subsequent improvements in the fabrication process for single crystal devices was such that no further attention was paid to the threshold variation problem. Recently this position has changed, particularly as a consequence of the reduction in size of nMOS devices to the sub-micron level.

An example of a recent technique to compensate for threshold voltage variation in a single crystal transistor implemented comparator circuit is disclosed in US patent 5949270 issued on 7th September 1999. As disclosed in that document, a capacitor is connected between the gate of a transistor that is an object of threshold voltage compensation and an input terminal. first switching device is connected between a current source connected to one terminal of the transistor and the gate of the transistor. A second switching device is connected between the input terminal and a terminal to which a reference voltage is applied.

The first switching device is turned ON so that the transistor is diodeconnected. The second switching device is turned ON, thus applying the reference voltage to the input terminal. A reference voltage is applied to a current inflow terminal connected to another terminal of the transistor. After charge dependent on the threshold voltage of the transistor is accumulated in the capacitor, the first switching device is turned OFF. With this control, a difference in threshold voltages between adjoining transistors can be compensated for.

Thin film transistors (TFTs), which are formed using a polycrystalline semiconductor film, such as polycrystalline silicon, are well known. Such polysilicon TFTs are considered to have several advantages over MOS devices formed with a single crystal semiconductor.

Principally, TFTs can be produced relatively inexpensively since the fabrication process avoids the constraints of producing a sufficiently large single crystal silicon substrate with a satisfactorily low level of impurities. Moreover, because the polycrystalline semiconductor film can be produced on any suitable supporting substrate, such as glass sheet, the size constraints necessitated by the production of a single crystal substrate are obviated, so that large numbers of TFTs, and hence a large number of circuits, can be produced on a relatively inexpensive single support substrate.

However, polysilicon TFTs have the significant drawback in that they have widely varying threshold voltages, even when manufactured in the same production batch and using the same polysilicon film. The threshold voltage is effectively the voltage which must be applied to the gate electrode of the TFT to enable a current to flow in the channel region between the source and drain regions and so determine the ON-condition of the TFT. In the fabrication process for the polysilicon film it is difficult to guarantee continuity of individual crystal sizes and, furthermore, there are also variations in the purity of the film. Thus, the polysilicon film material varies between the TFTs fabricated from a common polysilicon film and it is this film material which determines the threshold voltage of the TFTs. Hence, polysilicon TFTs exhibit a far greater variation in threshold voltage in comparison to MOS single crystal transistors. As a consequence of this variation in threshold voltage, TFTs have not been considered for many circuit applications, and in particular for those applications where consistency of transistor threshold voltage is of paramount importance, such as comparator circuits, because any change between the voltages applied to the input terminals is required to produce a large change in the voltage at the output terminal.

Moreover, for TFTs, the current/voltage characteristic varies with the width/length ratio of the channel region. Additionally, for any channel region width/length ratio, the operational characteristic differs significantly between P and N channel devices. For

example, for any change in voltage applied to the device, an N-channel TFT will exhibit a much sharper rise in output current than for a P- channel TFT.

Several concerns also exist with the threshold compensation circuit as described in US 5949270, such that it would not reliably function if implemented using TFTs.

The first switching device described in US5949270 is a MOS transistor connected as a diode which, in essence, acts as a load resistor for the second switching device. As it is a transistor connected to operate as a diode it will exhibit a non-linear impedance characteristic. For comparator circuits, a prime requirement is to make the swing in the voltage at the output terminal as large as possible for any change between the voltages at the input terminals. From Figure 1, which shows the transfer characteristic of an inverter circuit implemented using TFTs, it can be seen that if such a circuit is used as a comparator it is necessary to operate the TFTs on the knee portions of the characteristic so as to ensure that there is a large swing in the output voltage for a small change in the input voltage. The non-

linear characteristic of the first switching device of US5949270 coupled as a diode would not enable this to be achieved reliably in practice.

Furthermore, the circuit described in US 5949270 is implemented using a pair of N-

channel switching devices. Therefore, when the circuit is in operation both devices are ON at all times, creating high power consumption. Hence, it is not a straightforward step to implement the circuit shown in US 5949270 using TFTs, and in particular using complementary TFTs so as to minimise power consumption in use of the circuit.

According to a first aspect of the present invention there is provided a comparator circuit comprising a pair of series connected polycrystalline transistors, two capacitors and a

switch, the switch being connected between the point of series connection of the transistors and a node to which one side of each capacitor and the gates of the transistors are connected in common, with the other side of each capacitor being operably connected to a respective input. In addition to the differences in circuit arrangement between the first aspect of the present invention and the circuit described in US 5949270; it will also be appreciated that the present invention uses polycrystalline transistors rather than the single crystal transistors used in all of the prior art discussed above.

Preferably the comparator circuit according to the present invention comprises two further switches each selectively connecting a respective said other side of said capacitors between ground and the said respective input. Beneficially the switches are implemented by transistors. Very desirably all of the transistors are CMOS TFT transistors.

It is preferred that the comparator circuit of the present invention further comprises an output stage with said output stage being selectively isolated or connected to said transistor pair by an output stage switch. Furthermore, it is preferred that a buffer is connected between the output stage switch and the said transistor pair.

According to a second aspect of the present invention there is provided a method of comparing two input voltages by: providing a comparator having a pair of series connected polycrystalline transistors, two capacitors and a switch, the switch being connected between the point of series connection of the transistors and a node to which one side of each capacitor and the gates of the transistors are connected in common, closing the switch to transfer a bias voltage to the node, storing the bias voltage on the capacitors, opening the switch, applying each input voltage to a respective one of the capacitors, and detecting any resultant change in the bias voltage.

Embodiments of the present invention will now be described by way of further example only and with reference to the accompanying drawings in which: Figure 1 illustrates the effect of threshold voltage variation on the transfer characteristic of an inverter, Figure 2 shows a self-biased TFT CMOS comparator in accordance with an embodiment of the present invention, Figure 3 shows a detailed implementation of the circuit of figure 2, Figure 4 shows the driving waveform, the input waveforms and the output waveform of one particular embodiment of the present invention, and Figure S shows input waveforms and corresponding output waveforms for certain threshold voltage variations of one particular embodiment of the present invention.

Whereas all of the known prior proposals have been based on the use of single crystal nMOS transistors, the present invention is based on the use of polycrystalline transistors.

Not only is it not straight forward to substitute polycrystalline transistors for the single crystal transistors in the known proposals, but also to adopt polycrystalline transistors would appear to be illogical since it is well known that the threshold voltage variation problem is far more severe in polycrystalline transistors than in single crystal transistors. However, the present invention enables this very significant disadvantage to be overcome by providing a comparator which is independent of threshold voltage variation. This enables the significant advantages of TFT AMOS circuitry to be realised in the comparator circuitry. The advantages include the relative ease with which polycrystalline transistors can be fabricated compared with the fabrication of single crystal devices and also the much lower power consumption required by polycrystalline circuits.

The threshold voltage variation difficulties usually encountered with polycrystalline transistors can be readily appreciated by considering the transfer characteristics of an N and P pair of such transistors, for example the transfer characteristics of a TFT inverter circuit.

Figure 1 illustrates the variation in the transfer characteristic of a TFT inverter circuit when different threshold voltage variations exist between the two transistors. Typically the

threshold voltage variation between polycrystalline transistors typically is approximately 1V. Figure 1 illustrates examples of possible combinations of threshold voltage variations; n(0) p(0), n(-1) p(-1), n(l) p(l), n(l) p(-1), n(-1) p(1), where n and p respectively denote the N and P type transistors and 0, 1 and -1 represent the threshold voltage variation (in volts) from an ideal (i.e. n(0) p(0)). As can be seen, the input voltage at which a significant change occurs in the output logic/voltage varies between approximately 2V and just under 4V. The consequence of this is that with the simple implementation of a TFT CMOS comparator the minimum voltage difference which can be distinguished reliably between two input voltages being compared is approximately 2V. This has precluded their use in comparator circuits.

The principle of the circuit used by the present invention will be explained with reference to figure 2. Figure 2 shows a self-biased TFT CMOS comparator in which a TFT NIP pair, T1 and T2, are series connected between supply rails and in which the inputs, Vinl and Vin2, for the voltages to be compared are connected via respective select switches, SW1 and SW2, to one side of respective capacitors, Cal and C2. Ideally, the value of capacitor Cat is equal to the value of capacitor C2. The other sides of the capacitors are connected in common, at node N. to a common connection between the gates of the two transistors T1 and T2. A switch SW3 is connected between the common connection of the gates and the point of series connection between the two transistors.

The circuit of figure 2 operates as follows. Starting from the position shown in figure 2, that is with switch SW3 open and switches SW1 and SW2 connecting the capacitors Cat and C2 to ground, close switch SW3. The voltage (the bias voltage) from the series connection point of the transistors T1 and T2 is thus transferred to node N and capacitors Ci and C2 are charged. Switch SW3 is then opened and the bias voltage is maintained by the capacitors and the voltage at node N floats at the level of the voltage stored in capacitors Cat and C2. The bias voltage can therefore now be used as a point of toggle voltage in the comparison of the voltages respectively input on Vinl and Vin2. Next, switches SW1 and SW2 are operated to connect Vinl and Vin2, respectively, to capacitors Cat and Cal. The

input voltages are thus transferred across the capacitors. If Vinl and Vin2 are equal, the node N stays at the bias voltage level. However, if Vinl is not equal to Vin2 then the voltage at node N will vary upwards or downwards, depending on which is the larger of the two input voltages. Hence, any difference between the input voltages appears as a change in the value of the bias voltage at the node N. Thus, the circuit of figure 2 is capable of detecting relatively small differences between the input voltages, because that difference results in a directly corresponding change in the bias voltage at node N. Input voltage differences of 0.5V or less can be detected very easily using this arrangement. The resolution of the comparator is therefore readily improved from the +2V explained above to better than +0.5V. This improvement in resolution is governed by the slope of the transfer characteristic of the transistors, as shown in figure 1. This slope is in turn governed by the width to length ratio (W/L) of the channel regions of the transistors T1 and T2. The resolution can therefore be further improved by optimising the dimensions of transistors T1 and T2. Moreover, it will be apparent that the circuit of figure 2 is effectively independent of transistor threshold voltage variation.

As a result of improving the sensitivity of the circuit, the power supply requirement can be reduced. The benefits of the low power consumption usually associated with CMOS technology can thus be realised.

A further and very significant advantage deriving from the circuit of figure 2 is a substantial improvement in the ease of fabrication. That is, it is very much easier to manufacture matched pairs of capacitors than it is to manufacture matched pairs of polycrystalline transistors.

A detailed implementation of the circuit of figure 2 is shown in figure 3. Capacitors Cat and C2 retain the same reference numerals. Transistors T1 and T2 will be recognised as Ql and Q11. Switches SW1, SW2 and SW3 will be recognised in their implementation by transistors Q3, Q10 and Q6, respectively. A transistor pair Q4 and Q8 are series connected between the switch plate sides of Cal and C:, with their point of series connection being

stabilised at ground. Thus, the circuit is reset by applying a reset signal RST1 to the gates of transistors Q4, Q6 and Q8. A start signal, GOT, is applied to the gates of transistors Q3 and Q10; so as operate the switches SW1 and SW2.

A buffer, comprising the transistor pair Q5 and Q9 series connected between the supply rails, is connected to the output of the above described input stage. The buffer is connected to the output stage (transistors Q2 and Q12, and capacitor C3) via transistor Q7.

Transistor Q7 (whose gate receives signal GOT) acts as a switch to keep the output switched off until the input stage has had time to self-bias. Transistor Q7 may conveniently be referred to as an output stage switch.

The results achieved with an embodiment of the circuit of figure 3 are illustrated in figures 4 and 5. Figure 4 shows the driving waveform, the input waveforms and the output waveform of one particular embodiment. Figure 5 illustrates input waveforms and corresponding output waveforms for threshold voltage variations in T1 of -1V, OV and 1V (effectively the variation of voltage on Q6).

The foregoing description has been given by way of example only and it will be

appreciated by a person skilled in the art that modifications can be made without departing from the scope of the present invention.

Claims

1. A comparator circuit comprising a pair of series connected polycrystalline transistors, two capacitors and a switch, the switch being connected between the point of series connection of the transistors and a node to which one side of each capacitor and the gates of the transistors are connected in common, with the other side of each capacitor being operably connected to a respective input.

2. A comparator circuit as claimed in claim 1, comprising two further switches each selectively connecting a respective said other side of said capacitors between ground and the said respective input.

3. A comparator circuit as claimed in claim 1 or as claimed in claim 2, wherein the switches are implemented by transistors.

4. A comparator circuit as claimed in any preceding claim, wherein the transistors are CMOS TFT transistors.

5. A comparator circuit as claimed in any preceding claim, further comprising an output stage with said output stage being selectively isolated or connected to said transistor pair by an output stage switch.

6. A comparator circuit as claimed in claim 5, farther comprising a buffer connected between the output stage switch and the said transistor pair.

7. A comparator circuit substantially as hereinbefore described with reference to and as illustrated in figure 3 of the accompanying drawings.

8. A method of comparing two input voltages by:

providing a comparator having a pair of series connected polycrystalline transistors, two capacitors and a switch, the switch being connected between the point of series connection of the transistors and a node to which one side of each capacitor and the gates of the transistors are connected in common, closing the switch to transfer a bias voltage to the node, storing the bias voltage on the capacitors, opening the switch, applying each input voltage to a respective one of the capacitors, and detecting any resultant change in the bias voltage.