JP3396792B2 - Fail-safe logic circuit, fail-safe n-input AND gate circuit, and fail-safe self-holding circuit - Google Patents
Fail-safe logic circuit, fail-safe n-input AND gate circuit, and fail-safe self-holding circuitInfo
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- JP3396792B2 JP3396792B2 JP29685994A JP29685994A JP3396792B2 JP 3396792 B2 JP3396792 B2 JP 3396792B2 JP 29685994 A JP29685994 A JP 29685994A JP 29685994 A JP29685994 A JP 29685994A JP 3396792 B2 JP3396792 B2 JP 3396792B2
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- photocoupler
- circuit
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、いわゆるフェイルセー
フ信号処理による論理回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit by so-called fail-safe signal processing.
【０００２】[0002]
【従来の技術】フェイルセーフ信号処理は、“回路の動
作状態を検査するための信号で入力信号を変調して信号
処理を行い、この信号処理後の変調信号を復調して出力
信号とする”ものである。2. Description of the Related Art Fail-safe signal processing is "modulating an input signal with a signal for inspecting an operating state of a circuit to perform signal processing, and demodulating the modulated signal after the signal processing to obtain an output signal". It is a thing.
【０００３】このフェイルセーフ信号処理を図５に示す
フェイルセーフ２入力アンドゲート回路の例により説明
する。図５において、Ｘ１，Ｘ２は２値の入力信号で、
この入力信号は、第１のトランジスタ１０３，第２のト
ランジスタ１０６の電源入力となっている。１０１は信
号発生器で、前述の“回路の動作状態を検査するための
信号”（以下検査信号という）を発生する。１０８は倍
電圧整流回路等からなる包絡線検波（復調）回路であ
る。１０２，１０４，１０５，１０７は、トランジスタ
１０３，１０６と共にトランジスタ増幅回路を構成する
所要の抵抗である。This fail-safe signal processing will be described with reference to an example of the fail-safe 2-input AND gate circuit shown in FIG. In FIG. 5, X1 and X2 are binary input signals,
This input signal serves as a power supply input to the first transistor 103 and the second transistor 106. A signal generator 101 generates the above-mentioned "signal for inspecting the operating state of the circuit" (hereinafter referred to as an inspection signal). Reference numeral 108 denotes an envelope detection (demodulation) circuit including a voltage doubler rectification circuit and the like. Reference numerals 102, 104, 105 and 107 are required resistors that form a transistor amplifier circuit together with the transistors 103 and 106.
【０００４】この構成で、入力信号Ｘ１，Ｘ２が入力さ
れているとき、すなわちＸ１＝１，Ｘ２＝１のとき、信
号発生器１０１の発生した検査信号は、トランジスタ１
０３，１０６で増幅され、包絡線検波回路１０８で復調
され出力信号Ｙが得られる。すなわちＹ＝１である。With this configuration, when the input signals X1 and X2 are input, that is, when X1 = 1 and X2 = 1, the inspection signal generated by the signal generator 101 is the transistor 1
Amplified by 03 and 106, demodulated by the envelope detection circuit 108 and an output signal Y is obtained. That is, Y = 1.
【０００５】入力信号Ｘ１，Ｘ２の少なくとも一方が入
力されないときは、回路の増幅機能は失われ、包絡線検
波回路１０８の出力信号が得られない。すなわちＹ＝０
である。When at least one of the input signals X1 and X2 is not input, the amplification function of the circuit is lost and the output signal of the envelope detection circuit 108 cannot be obtained. That is, Y = 0
Is.
【０００６】もし回路に故障が生じた場合、例えば、抵
抗１０２，１０４，１０５，１０７のいずれかが断線す
る、トランジスタ１０３，１０６のいずれかが短絡す
る、あるいは回路の一部が断線するといった故障が生じ
た場合、回路の増幅機能が失われるので、入力信号Ｘ
１，Ｘ２が入力されていても包絡線検波回路１０８に出
力信号が得られない。すなわちＹ＝０である。If a failure occurs in the circuit, for example, one of the resistors 102, 104, 105 and 107 is broken, one of the transistors 103 and 106 is short-circuited, or a part of the circuit is broken. Occurs, the amplification function of the circuit is lost, so the input signal X
Even if 1 and X2 are input, the output signal cannot be obtained from the envelope detection circuit 108. That is, Y = 0.
【０００７】ここで回路の動作状態を２値の論理変数ｆ
* で表わし、１を正常な動作状態、０を故障状態とすれ
ば、出力信号Ｙは次式で表わされる。Here, the operating state of the circuit is represented by a binary logic variable f.
The output signal Y is expressed by the following equation, where * is a normal operation state and 1 is a failure state.
【０００８】Ｙ＝Ｘ１・Ｘ２・ｆ*
したがって、回路に故障が生じた場合は、入力信号Ｘ
１，Ｘ２の値に関係なく常にＹ＝０となる。Ｙ＝１をシ
ステムの危険側、Ｙ＝０をシステムの安全側とすれば、
回路に故障が生じた場合、常にシステムの安全側とな
り、フェイルセーフが実現できる。Y = X1.X2.f * Therefore, if a circuit failure occurs, the input signal X
Y = 0 always regardless of the values of 1 and X2. If Y = 1 is the dangerous side of the system and Y = 0 is the safe side of the system,
When a circuit failure occurs, the system is always on the safe side, and fail-safe can be realized.
【０００９】[0009]
【発明が解決しようとする課題】前述のフェイルセーフ
２入力アンドゲート回路の例では、包絡線検波回路の故
障については触れていないが、この回路も例外ではなく
故障が生じる場合がある。In the above-mentioned example of the fail-safe 2-input AND gate circuit, the failure of the envelope detection circuit is not mentioned, but this circuit is not an exception and a failure may occur.
【００１０】図６はこの故障の１例を示す図である。図
示の回路は、入力信号Ｘｎの信号処理においても検査信
号を用いており、１１１はその変調信号である。１１
２，１１５はコンデンサで、１１３，１１４は整流ダイ
オードであって、これらの素子は倍電圧整流回路形の包
絡線検波回路を構成している。１１６は図５に示すよう
な増幅回路（論理演算回路）の最終段の増幅器であり、
信号Ｘｎを入力信号（論理入力）としている。FIG. 6 is a diagram showing an example of this failure. The circuit shown in the figure also uses the inspection signal in the signal processing of the input signal Xn, and 111 is its modulation signal. 11
Reference numerals 2 and 115 are capacitors, and 113 and 114 are rectifying diodes, and these elements form a voltage doubler rectifier type envelope detection circuit. Reference numeral 116 denotes an amplifier at the final stage of the amplifier circuit (logical operation circuit) as shown in FIG.
The signal Xn is used as an input signal (logical input).
【００１１】この回路でコンデンサ１１５が断線する
と、変調信号が増幅器１１６の電源として印加され、前
段の論理状態に関係なく、増幅器１１６から変調信号が
出力されてしまいフェイルセーフが実現できないという
問題がある。When the capacitor 115 is disconnected in this circuit, the modulation signal is applied as the power source of the amplifier 116, and the modulation signal is output from the amplifier 116 regardless of the logic state of the previous stage, so that there is a problem that fail safe cannot be realized. .
【００１２】このような問題を解決する手法としてコン
デンサ１１５に４端子コンデンサ（安全コンデンサとも
いう）を用いることが知られている。４端子コンデンサ
は、図７の（ｂ），（ｄ）に示すように、各電極にリー
ド線を２本づつ取り付けたものである。なお、比較のた
めに、図７の（ａ），（ｃ）で通常のコンデンサの構成
を示している。As a method for solving such a problem, it is known to use a four-terminal capacitor (also called a safety capacitor) as the capacitor 115. As shown in FIGS. 7B and 7D, the four-terminal capacitor has two lead wires attached to each electrode. For the purpose of comparison, FIGS. 7A and 7C show the configuration of a normal capacitor.
【００１３】この４端子コンデンサを包絡線検波回路の
出力側のコンデンサとして用い、たとえば図６の回路に
おいて、リード線１２１，１２３を包絡線検波回路の出
力側に、リード線１２２を増幅器１１６の電源入力側
に、リード線１２４を電源ＶCCに接続する。This 4-terminal capacitor is used as a capacitor on the output side of the envelope detection circuit. For example, in the circuit of FIG. 6, the lead wires 121 and 123 are on the output side of the envelope detection circuit, and the lead wire 122 is on the power supply of the amplifier 116. On the input side, the lead wire 124 is connected to the power supply V CC .
【００１４】この構成によれば、リード線１２１，１２
２のいずれが断線しても変調信号が増幅器１１６に印加
されることがない。According to this structure, the lead wires 121, 12
The modulation signal is not applied to the amplifier 116 even if any of the two is disconnected.
【００１５】しかし回路構成によってはリード線１２４
が断線すると変調信号が直接増幅器に印加され前述と同
様にフェイルセーフが実現できないという問題がある。However, depending on the circuit configuration, the lead wire 124
If the line is disconnected, the modulation signal is directly applied to the amplifier, and there is a problem that fail-safe cannot be realized as described above.
【００１６】図６は包絡線検波回路に倍電圧整流回路を
用いた例であるが、他の復調回路を用いたときも回路構
成に応じて同様の問題が生じる。Although FIG. 6 shows an example in which a voltage doubler rectifier circuit is used for the envelope detection circuit, the same problem occurs depending on the circuit configuration when another demodulation circuit is used.
【００１７】この発明は、このような問題を解決するた
めになされたものであり、包絡線検波回路等の復調手段
を通して変調信号が侵入してきてもフェイルセーフが実
現できるフェイルセーフ論理回路，フェイルセーフｎ入
力アンドゲート回路およびフェイルセーフ自己保持回路
を提供することを目的とするものである。The present invention has been made in order to solve such a problem, and is a fail-safe logic circuit and a fail-safe logic circuit which can realize fail-safe even if a modulation signal enters through demodulation means such as an envelope detection circuit. An object is to provide an n-input AND gate circuit and a fail-safe self-holding circuit.
【００１８】[0018]
【課題を解決するための手段】前記目的を達成するた
め、本発明ではフェイルセーフ論理回路を次の（１）の
とおりに、フェイルセーフｎ入力アンドゲート回路を次
の（２）のとおりに、フェイルセーフ自己保持回路を次
の（３）のとおりに構成する。In order to achieve the above object, the present invention provides a fail-safe logic circuit according to the following (1) and a fail-safe n-input and gate circuit according to the following (2). The fail-safe self-holding circuit is configured as in (3) below.
【００１９】（１）所定周波数の高周波を論理変数信号
で変調した信号を入力する入力端と、この入力端からの
信号を復調する復調手段と、この復調手段の出力により
発光側が付勢されるフォトカプラとを備え、前記所定周
波数を前記フォトカプラの応答不能の周波数としたフェ
イルセーフ論理回路。(1) An input end for inputting a signal obtained by modulating a high frequency of a predetermined frequency with a logic variable signal, demodulation means for demodulating the signal from this input end, and the light emission side is energized by the output of this demodulation means. A fail-safe logic circuit including a photo coupler, wherein the predetermined frequency is a frequency at which the photo coupler cannot respond.
【００２０】（２）第１〜第ｎの検査信号を第１〜第ｎ
の論理変数信号で夫々変調した第１〜第ｎの変調信号を
入力する第１〜第ｎの入力端子と、この第１〜第ｎの入
力端子からの第１〜第ｎの変調信号を復調する第１〜第
ｎの復調手段と、主検査信号で付勢される主検査信号入
力用フォトカプラトの受光素子と、前記第１の復調回路
の出力端に接続した第１のフォトカプラの発光素子と主
検査信号入力用フォトカプラの受光素子との直列回路
と、前記第ｎの復調回路の出力端に接続した第ｎのフォ
トカプラの発光素子と第ｎ−１のフォトカプラの受光素
子との直列回路と、前記第ｎのフォトカプラの受光素子
の出力側に接続した出力段復調手段と、この出力段復調
手段の出力端に接続した当該フェイルセーフｎ入力アン
ドゲート回路の出力端子とを備え、前記第１〜第ｎの検
査信号の周波数を夫々対応する第１〜第ｎのフォトカプ
ラの応答不能の周波数とし、前記主検査信号の周波数
を、主検査信号入力用フォトカプラおよび前記第１〜第
ｎのフォトカプラの応答可能な周波数としたフェイルセ
ーフｎ入力アントゲート回路。(2) The first to nth inspection signals are first to nth
First to nth input terminals for inputting the first to nth modulated signals respectively modulated with the logical variable signals of No. 1 to n, and the first to nth modulated signals from the first to nth input terminals are demodulated. Of the first to nth demodulating means, the light receiving element of the main inspection signal input photocoupler energized by the main inspection signal, and the first photocoupler connected to the output terminal of the first demodulation circuit. A series circuit of the light emitting element and the light receiving element of the photocoupler for inputting the main inspection signal, the light emitting element of the nth photocoupler and the light receiving element of the (n-1) th photocoupler connected to the output terminal of the nth demodulation circuit. And a series circuit, an output stage demodulation means connected to the output side of the light receiving element of the nth photocoupler, and an output terminal of the fail-safe n-input AND gate circuit connected to the output terminal of the output stage demodulation means. The frequency of the first to nth inspection signals A fail in which the corresponding first to nth photocouplers are set to a non-responsive frequency, and the frequency of the main inspection signal is set to a frequency at which the main inspection signal input photocoupler and the first to nth photocouplers can respond. Safe n-input ant gate circuit.
【００２１】（３）第１，第２の検査信号をトリガ信
号，リセット信号で夫々変調したトリガ変調信号，リセ
ット変調信号を入力する第１，第２の入力端子と、この
第１，第２の入力端子から入力したトリガ変調信号，リ
セット変調信号を復調する第１，第２の復調手段と、主
検査信号で付勢される第１のフォトカプラの発光素子
と、前記第１の復調手段の出力端に接続した第２のフォ
トカプラの発光素子と前記第１のフォトカプラの受光素
子の直列回路と、第２の復調手段の出力端に接続した第
３のフォトカプラの発光素子と第４のフォトカプラの発
光素子と第２のフォトカプラの受光素子との直列回路
と、前記第３のフォトカプラの受光素子の出力側に接続
した第３の復調手段と、この第３の復調手段の出力信号
を第１の復調手段の出力側に帰還する帰還手段と、前記
第４のフォトカプラの受光素子に接続された当該自己保
持回路の出力端子とを備え、前記第１の検査信号の周波
数を第２のフォトカプラの応答不能の周波数とし、前記
第２の検査信号の周波数を第３のフォトカプラの応答不
能の周波数とし、主検査信号の周波数を前記第１〜第４
のフォトカプラの応答可能な周波数としたフェイルセー
フ自己保持回路。(3) First and second input terminals for inputting a trigger modulation signal and a reset modulation signal obtained by respectively modulating the first and second inspection signals with a trigger signal and a reset signal, and the first and second input terminals. First and second demodulation means for demodulating the trigger modulation signal and the reset modulation signal input from the input terminal of the first photocoupler, the light emitting element of the first photocoupler energized by the main inspection signal, and the first demodulation means. A series circuit of the light emitting element of the second photocoupler and the light receiving element of the first photocoupler connected to the output terminal of the third photocoupler and the light emitting element of the third photocoupler connected to the output terminal of the second demodulation means. 4, a series circuit of the light emitting element of the photocoupler and the light receiving element of the second photocoupler, a third demodulating means connected to the output side of the light receiving element of the third photocoupler, and the third demodulating means. Output signal of the first demodulation means To the light receiving element of the fourth photocoupler, and the output terminal of the self-holding circuit connected to the light receiving element of the fourth photocoupler. The frequency of the first inspection signal is the frequency at which the second photocoupler cannot respond. And the frequency of the second inspection signal is the frequency at which the third photocoupler cannot respond, and the frequency of the main inspection signal is the first to fourth.
Fail-safe self-holding circuit with the frequency that can be responded to by the photo coupler.
【００２２】[0022]
【作用】前記（１），（２），（３）の構成によれば、
故障により論理回路のフォトカプラの発光側に変調信号
が直接入力しても、フォトカプラはこの変調信号に応答
せず、出力信号がなくなってフェイルセーフが実現でき
る。According to the constitutions of (1), (2) and (3),
Even if the modulation signal is directly input to the light emitting side of the photocoupler of the logic circuit due to a failure, the photocoupler does not respond to this modulation signal and the output signal disappears, so that the fail safe can be realized.
【００２３】[0023]
【実施例】以下本発明を実施例により詳しく説明する。EXAMPLES The present invention will be described in detail below with reference to examples.
【００２４】（実施例１）図１は実施例１である“フェ
イルセーフ２入力アンドゲート回路”の回路図である。
図において、１２と１３は第２のフォトカプラＰＣ２を
構成する発光素子と受光素子である。発光素子１２は発
光ダイオード、受光素子１３はフォトトランジスタであ
る。ところでフォトトランジスタを用いるこの種のフォ
トカプラは応答性が悪く、発光素子への入力周波数があ
る程度以上になると、実質上スイッチングせず、応答不
能となる特性を有している。(Embodiment 1) FIG. 1 is a circuit diagram of a "fail-safe 2-input AND gate circuit" which is Embodiment 1. In FIG.
In the figure, 12 and 13 are a light emitting element and a light receiving element which constitute the second photocoupler PC2. The light emitting element 12 is a light emitting diode, and the light receiving element 13 is a phototransistor. By the way, this type of photocoupler using a phototransistor has a poor response, and when the input frequency to the light emitting element exceeds a certain level, it does not substantially switch and has a characteristic of becoming unresponsive.
【００２５】１は、前記第２のフォトカプラＰＣ２が応
答不能となる周波数の第２の検査信号を、第２の論理変
数Ｘ２で変調した第２の変調信号である。この第２の変
調信号１は、抵抗３，トランジスタ２からなるトランジ
スタ増幅回路で増幅され、コンデンサ４，７、整流ダイ
オード５，６からなる倍電圧整流回路形の包絡線検波回
路Ａで復調され、第２の論理変数Ｘ２相当の信号とな
る。Reference numeral 1 is a second modulation signal obtained by modulating a second inspection signal having a frequency at which the second photocoupler PC2 becomes unresponsive with a second logic variable X2. The second modulated signal 1 is amplified by a transistor amplifier circuit composed of a resistor 3 and a transistor 2, and demodulated by a voltage doubler rectifier type envelope detection circuit A composed of capacitors 4, 7 and rectifier diodes 5, 6. The signal corresponds to the second logic variable X2.
【００２６】１０と１１は、第１のフォトカプラＰＣ１
を構成する発光素子と受光素子である。９は、前記第１
のフォトカプラＰＣ１が応答可能な周波数の第１の検査
信号を、第１の論理変数Ｘ１で変調した第１の変調信号
である。Reference numerals 10 and 11 denote the first photocoupler PC1.
Is a light emitting element and a light receiving element. 9 is the first
Is a first modulation signal obtained by modulating the first test signal of a frequency that can be responded by the photocoupler PC1 of 1. with the first logic variable X1.
【００２７】第２のフォトカプラＰＣ２の発光素子１２
と、第１のフォトカプラＰＣ１の受光素子１１の直列回
路は、電流制限抵抗８を介して、包絡線検波回路Ａの出
力すなわち第２の論理変数Ｘ２相当の電圧で付勢され
る。Light emitting element 12 of second photocoupler PC2
Then, the series circuit of the light receiving elements 11 of the first photocoupler PC1 is energized by the output of the envelope detection circuit A, that is, the voltage corresponding to the second logic variable X2, via the current limiting resistor 8.
【００２８】第２のフォトカプラＰＣ２の受光素子１３
は負荷抵抗１４を介して電源ＶCCにより付勢される。負
荷抵抗１４の信号はコンデンサ１５，１８、整流ダイオ
ード１６，１７からなる包絡線検波回路Ｂで復調され、
出力端子１９から出力信号Ｙとして出力される。Light receiving element 13 of second photocoupler PC2
Is energized by power supply V CC through load resistor 14. The signal of the load resistor 14 is demodulated by the envelope detection circuit B including the capacitors 15 and 18 and the rectifying diodes 16 and 17,
The output signal Y is output from the output terminal 19.
【００２９】ここで、第２の変調信号１があれば、第２
のフォトカプラＰＣ２の発光素子１２と、第１のフォト
カプラＰＣ１の受光素子１１との直列回路は、第２の論
理変数Ｘ２に相当する直流電圧で、電流制限抵抗８を介
して付勢される。そして、第１の変調信号９があれば、
この変調信号９で第１のフォトカプラＰＣ１の発光素子
１０が点滅し、これを受けて受光素子１１がオン，オフ
し、第２のフォトカプラＰＣ２の発光素子１２が点滅
し、受光素子１３がオン，オフして、負荷抵抗１４に第
１の変調信号９に対応する変調信号が発生し、この信号
は包絡線検波回路Ｂで復調され、出力端子１９に出力信
号が発生する。第１の変調信号９が無ければ、受光素子
１１，１３はオン，オフせず、負荷抵抗１４に信号が発
生せず、包絡線検波回路Ｂの出力端子１９には出力信号
が発生しない。Here, if there is the second modulated signal 1, the second modulated signal 1
The series circuit of the light emitting element 12 of the photocoupler PC2 and the light receiving element 11 of the first photocoupler PC1 is energized via the current limiting resistor 8 with the DC voltage corresponding to the second logic variable X2. . Then, if there is the first modulated signal 9,
The modulated signal 9 causes the light emitting element 10 of the first photocoupler PC1 to blink, the light receiving element 11 is turned on and off in response to this, the light emitting element 12 of the second photocoupler PC2 blinks, and the light receiving element 13 When the load resistance 14 is turned on and off, a modulation signal corresponding to the first modulation signal 9 is generated, this signal is demodulated by the envelope detection circuit B, and an output signal is generated at the output terminal 19. Without the first modulation signal 9, the light receiving elements 11 and 13 are not turned on and off, no signal is generated at the load resistor 14, and no output signal is generated at the output terminal 19 of the envelope detection circuit B.
【００３０】第２の変調信号１が無ければ、前記直列回
路は付勢されず、したがって、第１の変調信号９の有無
に関係なく、包絡線検波回路Ｂの出力端子１９には出力
信号が発生しない。Without the second modulation signal 1, the series circuit is not energized and therefore, regardless of the presence or absence of the first modulation signal 9, the output signal at the output terminal 19 of the envelope detection circuit B is the same. Does not occur.
【００３１】このようにして、出力端子１９は論理変数
Ｘ１とＸ２の論理積に相当する出力信号Ｙが得られる。In this way, the output signal Y corresponding to the logical product of the logical variables X1 and X2 is obtained at the output terminal 19.
【００３２】本実施例回路では、包絡線検波回路Ａの出
力側に４端子コンデンサ７を用いており、また第２の変
調信号のトランジスタ増幅回路はこの４端子コンデンサ
７を介して付勢されているので、４端子コンデンサ７の
いずれかのリード線が断線しても、第２の変調信号１が
直接発光素子１２，受光素子１１の直列回路に印加され
ることはない。In the circuit of this embodiment, a 4-terminal capacitor 7 is used on the output side of the envelope detection circuit A, and the transistor amplification circuit for the second modulation signal is energized via this 4-terminal capacitor 7. Therefore, even if one of the lead wires of the 4-terminal capacitor 7 is broken, the second modulation signal 1 is not directly applied to the series circuit of the light emitting element 12 and the light receiving element 11.
【００３３】しかし、何らかの原因で、たとえば４端子
コンデンサのいずれか一方の電極に接続されている２本
のリード線が断線すると共に互いに接触するといった多
重故障により、第２の変調信号１が直接、発光素子１２
と受光素子１１との直列回路に印加されても、前述のよ
うに、第２の検査信号の周波数を第２のフォトカプラＰ
Ｃ２の応答不能の周波数に設定しているので、直接印加
された第２の変調信号には第２のフォトカプラＰＣ２が
応答せず、その負荷抵抗１４に第２の変調信号相当の信
号が生じることがない。したがって、このとき出力端子
１９に出力信号が生じない。すなわちＹ＝０である。However, for some reason, for example, the second modulation signal 1 is directly caused by a multiple failure in which two lead wires connected to one of the electrodes of the four-terminal capacitor are disconnected and contact each other. Light emitting element 12
Even if it is applied to the series circuit of the light receiving element 11 and the light receiving element 11, the frequency of the second inspection signal is set to the second photo coupler P as described above.
Since the frequency that C2 cannot respond is set, the second photocoupler PC2 does not respond to the second modulation signal applied directly, and a signal corresponding to the second modulation signal is generated in the load resistor 14. Never. Therefore, at this time, no output signal is generated at the output terminal 19. That is, Y = 0.
【００３４】このように、本実施例によれば、包絡線検
波回路Ａの故障にもかかわらず、出力端子に出力信号が
生じるということはなく、フェイルセーフが実現でき
る。As described above, according to this embodiment, despite the failure of the envelope detection circuit A, no output signal is generated at the output terminal, and fail safe can be realized.
【００３５】（実施例２）図２は実施例２である“フェ
イルセーフｎ入力アンドゲート回路”の回路図である。
本実施例は、実施例１をｎ入力に一般化した例である。(Embodiment 2) FIG. 2 is a circuit diagram of a "fail-safe n-input AND gate circuit" which is Embodiment 2. In FIG.
The present embodiment is an example in which the first embodiment is generalized to n inputs.
【００３６】図２において、２１，２２，２３は、夫々
対応するフォトカプラＰＣｎ，ＰＣ２，ＰＣ１が応答不
能の、第ｎ，第２，第１の周波数の検査信号を、それぞ
れ第ｎの論理変数，第２の論理変数，第１の論理変数で
変調した、第ｎの変調信号，第２の変調信号，第１の変
調信号である。なお、第ｎ……第１の検査信号は同一周
波数でもよい。In FIG. 2, reference numerals 21, 22, and 23 denote the inspection signals of the nth, second, and first frequencies, respectively, to which the corresponding photocouplers PCn, PC2, and PC1 cannot respond, respectively, and the nth logical variable. , The second logical variable, and the nth modulated signal, the second modulated signal, and the first modulated signal modulated by the first logical variable. Note that the nth ... 1st inspection signals may have the same frequency.
【００３７】第３の変調信号〜第ｎ−１の変調信号の回
路は“……”で示し図示を省略している。The circuits for the third modulation signal to the (n-1) th modulation signal are indicated by "..." And are not shown.
【００３８】２４は、本実施例回路のすべてのフォトカ
プラＰＣ０〜ＰＣｎが応答可能な周波数の検査信号であ
り、説明の便宜上、以下“主検査信号”という。Reference numeral 24 is an inspection signal of a frequency to which all the photocouplers PC0 to PCn of the circuit of this embodiment can respond, and will be referred to as "main inspection signal" hereinafter for convenience of explanation.
【００３９】２７，２８，２９は、実施例１における包
絡線検波回路Ａ，Ｂと同様の構成の、第ｎの包絡線検波
回路Ａｎ，第２の包絡線検波回路Ａ２，第１の包絡線検
波回路Ａ１である。Reference numerals 27, 28, and 29 denote the nth envelope detection circuit An, the second envelope detection circuit A2, and the first envelope having the same configuration as the envelope detection circuits A and B in the first embodiment. This is the detection circuit A1.
【００４０】主検査信号２４はフォトカプラ（主検査信
号入力用フォトカプラ）ＰＣ０の発光素子２５に印加さ
れている。第１の包絡線検波回路Ａ１の出力信号すなわ
ち論理変数Ｘ１相当の電圧は、電流制限抵抗３０を介し
て、第１のフォトカプラＰＣ１の発光素子３１と、フォ
トカプラＰＣ０の受光素子２６の直列回路に印加されて
いる。第２の包絡線検波回路Ａ２の出力信号は、電流制
限抵抗３３を介して、第２のフォトカプラＰＣ２の発光
素子３４と、第１のフォトカプラＰＣ１の受光素子３２
との直列回路に印加されている。第３の包絡線検波回路
ないし第ｎ−１の包絡線検波回路にかかる回路も同様に
構成されている。最終段すなわち出力段の第ｎの包絡線
検波回路Ａｎにかかる回路も同様に構成されるが、第ｎ
のフォトカプラＰＣｎの受光素子３８は、電源ＶCCから
負荷抵抗３９を介して付勢されている。負荷抵抗３９に
は、包絡線検波回路Ａ１〜Ａｎと同様の構成の、コンデ
ンサ４１，４３、整流ダイオード４０，４２からなる倍
電圧整流回路形の包絡線検波回路Ｂが接続されており、
４４はその出力端子である。The main inspection signal 24 is applied to the light emitting element 25 of the photocoupler (main inspection signal input photocoupler) PC0. The output signal of the first envelope detection circuit A1, that is, the voltage corresponding to the logical variable X1 is a series circuit of the light emitting element 31 of the first photocoupler PC1 and the light receiving element 26 of the photocoupler PC0 via the current limiting resistor 30. Is being applied to. The output signal of the second envelope detection circuit A2 passes through the current limiting resistor 33 and the light emitting element 34 of the second photocoupler PC2 and the light receiving element 32 of the first photocoupler PC1.
Is applied to the series circuit with. The circuits related to the third envelope detection circuit to the (n-1) th envelope detection circuit are similarly configured. A circuit related to the nth envelope detection circuit An at the final stage, that is, the output stage is also configured in the same manner.
The light receiving element 38 of the photo coupler PCn is energized from the power source V CC through the load resistor 39. The load resistor 39 is connected to a voltage doubler rectifier circuit type envelope detection circuit B composed of capacitors 41 and 43 and rectifier diodes 40 and 42, which has the same configuration as the envelope detection circuits A1 to An.
44 is its output terminal.
【００４１】第１の包絡線検波回路Ａ１にかかる直列回
路……第ｎの包絡線検波回路Ａｎにかかる直列回路は、
電源を介して干渉しないように、互いに電気的に絶縁し
た直流電源ＶCC１，ＶCC２…ＶCCｎに夫々接続されてい
る。この互いに電気的に絶縁した直流電源を構成するた
め、絶縁トランス４８と、この２次側の互いに絶縁され
た２次巻線に接続した整流・平滑回路４５，４６，……
４７を用いている。A series circuit of the first envelope detection circuit A1 ... A series circuit of the nth envelope detection circuit An is
Direct current power supplies V CC 1, V CC 2 ... V CC n electrically insulated from each other are connected to each other so as not to interfere with each other via the power supply. In order to configure the DC power supply which is electrically insulated from each other, the insulating transformer 48 and the rectifying / smoothing circuits 45, 46, ... Connected to the secondary windings insulated from each other on the secondary side.
47 is used.
【００４２】このように構成されているので、第１〜第
ｎの全ての変調信号が入力されている場合は、各直列回
路は付勢されており、主検査信号２４は、フォトカプラ
ＰＣ０，ＰＣ１，ＰＣ２……ＰＣｎを介して負荷抵抗３
９に伝達され、出力端子４４に出力信号Ｙが得られる。With this configuration, when all the first to nth modulation signals are input, each series circuit is energized, and the main inspection signal 24 is the photocoupler PC0, PC1, PC2 ... Load resistance 3 via PCn
9 and the output signal Y is obtained at the output terminal 44.
【００４３】第１〜第ｎの変調信号のうち、１以上の変
調信号が入力されないと、その変調信号にかかる直列回
路が付勢されず、主検査信号２４はフォトカプラＰＣ
０，ＰＣ１，ＰＣ２……ＰＣｎを介して負荷抵抗３９に
伝達されず、出力端子４４に出力信号が得られない。Unless one or more of the first to nth modulated signals are input, the series circuit associated with the modulated signals is not energized and the main inspection signal 24 becomes the photocoupler PC.
0, PC1, PC2 ... PCn is not transmitted to the load resistor 39, and no output signal is obtained at the output terminal 44.
【００４４】このようにして、論理変調Ｘ１〜Ｘｎの論
理積に相当する出力信号Ｙが得られる。In this way, the output signal Y corresponding to the logical product of the logical modulations X1 to Xn is obtained.
【００４５】本実施例において、何らかの故障で第１〜
第ｎの変調信号のいずれかが、その直列回路に直接侵入
すると、前述のように、第１〜第ｎの変調信号は、各フ
ォトカプラの応答不能の周波数の検査信号を変調したも
のなので、前述の直列回路のフォトカプラの発光素子が
点滅してもこれを受ける次段の前記フォトカプラの受光
素子はオン，オフせず、負荷抵抗３９に主検査信号が伝
達されず、出力端子４４に出力信号が得られない。In the present embodiment, due to some kind of failure,
When any of the n-th modulation signal directly enters the series circuit, as described above, the first to n-th modulation signals are the inspection signals of the unresponsive frequency of each photocoupler, Even if the light emitting element of the photocoupler in the series circuit described above blinks, the light receiving element of the photocoupler in the next stage that receives it does not turn on or off, the main inspection signal is not transmitted to the load resistor 39, and the output terminal 44 No output signal is obtained.
【００４６】このように、本実施例によれば、第１〜第
ｎの包絡線検波回路Ａ１〜Ａｎの故障により、第１〜第
ｎの変調信号がフォトカプラの直列回路に直接印加され
たときは、必ず出力端子４４に出力信号が得られなくな
り、すなわちＹ＝０となり、フェイルセーフが実現でき
る。As described above, according to this embodiment, the first to nth modulation signals are directly applied to the series circuit of the photocoupler due to the failure of the first to nth envelope detection circuits A1 to An. In this case, no output signal is always obtained at the output terminal 44, that is, Y = 0, and fail safe can be realized.
【００４７】（実施例３）図３は実施例３である“フェ
イルセーフ自己保持回路”の回路図である。本実施例は
本発明を自己保持回路に適用した例である。(Third Embodiment) FIG. 3 is a circuit diagram of a "fail-safe self-holding circuit" according to a third embodiment. The present embodiment is an example in which the present invention is applied to a self-holding circuit.
【００４８】図３において、５１は後述のフォトカプラ
ＰＣ１〜ＰＣ３が全て応答可能な周波数の主検査信号で
ある。この主検査信号５１は第１のフォトカプラＰＣ１
の発光素子５２に供給されている。５４は、発光素子６
２と受光素子６３からなる第３のフォトカラＰＣ３が応
答不能な周波数の検査信号を、リセット信号で変調した
変調信号Ｒである。５５は、発光素子５９と受光素子６
０からなる第２のフォトカプラＰＣ２が応答不能な周波
数の検査信号を、トリガ信号で変調した変調信号Ｔであ
る。なお変調信号Ｒ，Ｔの検査信号は同一周波数でもよ
い。In FIG. 3, reference numeral 51 is a main inspection signal of a frequency to which all the photo couplers PC1 to PC3 described later can respond. The main inspection signal 51 is the first photo coupler PC1.
Is supplied to the light emitting element 52 of. 54 is a light emitting element 6
3 is a modulation signal R obtained by modulating a test signal of a frequency at which the third photo-color PC3 including the light receiving element 63 and the light receiving element 63 cannot respond with a reset signal. 55 is a light emitting element 59 and a light receiving element 6
The second photocoupler PC2 consisting of 0 is the modulation signal T obtained by modulating the test signal of the frequency that the second photocoupler PC2 cannot respond with the trigger signal. The inspection signals of the modulation signals R and T may have the same frequency.
【００４９】フォトカプラＰＣ４は出力取出用で、その
受光素子６５には出力端子６６，６７が接続されてい
る。The photocoupler PC4 is for taking out an output, and the light receiving element 65 thereof has output terminals 66 and 67 connected thereto.
【００５０】５６，５７は倍電圧整流回路形の包絡線検
波回路であり、回路５６の出力側には、電流制限抵抗６
１と、第３のフォトカプラＰＣ３の発光素子６２と、第
４のフォトカプラＰＣ４の発光素子６４と、第２のフォ
トカプラＰＣ２の受光素子６０との直列回路が接続され
ており、回路５７の出力側には、電流制限抵抗５８と、
第２のフォトカプラＰＣ２の発光素子５９と、第１のフ
ォトカプラＰＣ１の受光素子５３との直列回路が接続さ
れている。Reference numerals 56 and 57 are voltage doubler rectifier type envelope detection circuits, and the current limiting resistor 6 is provided on the output side of the circuit 56.
1, a light emitting element 62 of the third photocoupler PC3, a light emitting element 64 of the fourth photocoupler PC4, and a light receiving element 60 of the second photocoupler PC2 are connected, and a series circuit of the circuit 57 is connected. On the output side, a current limiting resistor 58 and
A series circuit of the light emitting element 59 of the second photo coupler PC2 and the light receiving element 53 of the first photo coupler PC1 is connected.
【００５１】各直列回路および包絡線検波回路Ｂは互い
に電気的に絶縁するため、実施例２と同様に、不図示の
別個の整流・平滑回路の直流電源ＶCC１，ＶCC２，ＶCC
３に接続されている。Since each series circuit and envelope detection circuit B are electrically insulated from each other, DC power supplies V CC 1, V CC 2, V CC of separate rectifying / smoothing circuits (not shown) are provided as in the second embodiment.
Connected to 3.
【００５２】第３のフォトカプラＰＣ３の受光素子６３
には、負荷抵抗６８を介して電源ＶCC３が供給されてい
る。負荷抵抗６８には、コンデンサ７０，７２、整流ダ
イオード６９，７１からなる倍電圧整流回路形の包絡線
検波回路Ｂが接続されており、７３はその出力端子であ
る。Light receiving element 63 of the third photocoupler PC3
Is supplied with a power supply V CC 3 via a load resistor 68. The load resistance 68 is connected to a voltage doubler rectifier type envelope detection circuit B including capacitors 70 and 72 and rectifier diodes 69 and 71, and 73 is an output terminal thereof.
【００５３】出力端子７３はリアクトル７４を介して包
絡検波回路５７の出力端に接続され、帰還回路が構成さ
れている。リアクトル７４はトリガ用変調信号Ｔがバイ
パスされるのを阻止するために挿入されている。The output terminal 73 is connected to the output end of the envelope detection circuit 57 via the reactor 74 to form a feedback circuit. The reactor 74 is inserted to prevent the modulation signal for trigger T from being bypassed.
【００５４】以上の回路構成において、リセット用の変
調信号Ｒが入力されている状態で、トリガ用の変調信号
Ｔが入力すると、前述の各直列回路が付勢され、主検査
信号５１がフォトカプラＰＣ１，ＰＣ２，ＰＣ３を介し
て負荷抵抗６８に伝達され、包絡線検波回路Ｂで整流さ
れ、出力端子７３に出力信号Ｙが得られる。この出力信
号Ｙはリアクトル７４を介して包絡線検波回路５７の出
力端に帰還され、電流制限抵抗５８，発光素子５９，受
光素子５３の直列回路に印加されるので、トリガ用の変
調信号Ｔがなくなっても、主検査信号５１は負荷抵抗６
８に伝達され、またフォトカプラＰＣ４より出力端子６
６，６７に伝達され続ける。すなわち回路は自己保持状
態となる。In the above circuit structure, when the modulation signal R for resetting is input and the modulation signal T for triggering is input, the series circuits described above are energized, and the main inspection signal 51 becomes the photocoupler. It is transmitted to the load resistor 68 via PC1, PC2, and PC3, rectified by the envelope detection circuit B, and the output signal Y is obtained at the output terminal 73. This output signal Y is fed back to the output terminal of the envelope detection circuit 57 via the reactor 74 and applied to the series circuit of the current limiting resistor 58, the light emitting element 59, and the light receiving element 53, so that the modulation signal T for triggering is generated. Even if it disappears, the main inspection signal 51 is the load resistance 6
8 and the output terminal 6 from the photo coupler PC4.
Continue to be transmitted to 6,67. That is, the circuit is self-holding.
【００５５】その後、リセット用の変調信号Ｒが入力さ
れなくなると、電流制限抵抗６１，発光素子６２，発光
素子６４，受光素子６０の直列回路は付勢されなくな
り、出力端子７３の出力信号がなくなるので、自己保持
状態が解除され、出力端子６６，６７の出力信号はなく
なる。After that, when the reset modulation signal R is no longer input, the series circuit of the current limiting resistor 61, the light emitting element 62, the light emitting element 64, and the light receiving element 60 is no longer energized, and the output signal from the output terminal 73 disappears. Therefore, the self-holding state is released and the output signals from the output terminals 66 and 67 disappear.
【００５６】本実施例においても、実施例２と同様に、
何らかの故障で変調信号Ｒあるいは変調信号Ｔが直接前
述の直列回路に侵入すると、次段へ主検査信号が伝達さ
れなくなり、出力端子７３からの出力信号がなくなって
自己保持が解除され、出力端子６６，６７の出力信号は
なくなる。すなわち、故障によりＹ＝０となり、フェイ
ルセーフが実現できる。Also in this embodiment, as in the second embodiment,
When the modulation signal R or the modulation signal T directly enters the series circuit due to some failure, the main inspection signal is not transmitted to the next stage, the output signal from the output terminal 73 disappears and the self-holding is released, and the output terminal 66 is released. , 67 output signals disappear. That is, Y = 0 due to a failure, and fail safe can be realized.
【００５７】（変形）以上の各実施例は、いずれも負荷
抵抗に接続された包絡線検波回路の出力側に、４端子コ
ンデンサを用いるものであるが、本発明はこれに限定さ
れるものではなく、図４に示すように、通常の２端子の
コンデンサ８１を用いる形で実施することができる。こ
の場合、コンデンサ８１の少なくとも一方のリード線が
断線すると、フォトカプラＰＣの回路に変調信号８０が
直接印加されるが、フォトカプラＰＣはこの変調信号８
０に応答しないので、主検査信号９０が伝達されず、各
実施例と同様にフェイルセーフが実現できる。(Modification) In each of the above embodiments, a 4-terminal capacitor is used on the output side of the envelope detection circuit connected to the load resistor, but the present invention is not limited to this. Instead, as shown in FIG. 4, it can be implemented by using a normal two-terminal capacitor 81. In this case, when at least one lead wire of the capacitor 81 is broken, the modulation signal 80 is directly applied to the circuit of the photocoupler PC, but the photocoupler PC outputs the modulation signal 8
Since it does not respond to 0, the main inspection signal 90 is not transmitted, and fail-safe can be realized as in each embodiment.
【００５８】また、以上の各実施例は、いずれも包絡線
検波回路の出力を電源電位（ＶCC）に重畳させて、いわ
ゆる“電源枠外”による信号伝達を行っている。この場
合、コンパレータを用いて包絡線検波回路の出力Ｖを電
源電位ＶCCと比較し、２値の出力信号Ｙを、
Ｖ＞ＶCCのときＹ＝１
Ｖ≦ＶCCのときＹ＝０
とすることにより、より高度のフェイルセーフが実現で
きる。In each of the above embodiments, the output of the envelope detection circuit is superposed on the power supply potential (V CC ) to carry out signal transmission by the so-called "outside power supply frame". In this case, the comparator V is used to compare the output V of the envelope detection circuit with the power supply potential V CC, and the binary output signal Y is set as follows: Y = 1 when V> V CC and Y = 0 when V ≦ V CC By doing so, a higher degree of fail-safe can be realized.
【００５９】しかし、包絡線検波回路その他の出力信号
を電源電位ＶCCに重畳させない、いわゆる“電源枠内”
による信号伝達の形で実施することもできる。However, the envelope detection circuit and other output signals are not superposed on the power supply potential V CC , so-called "in the power supply frame".
It can also be carried out in the form of signal transmission according to.
【００６０】また、検査信号に、正弦波，矩形波のいず
れを用いる形ででも実施できる。The inspection signal can be implemented using either a sine wave or a rectangular wave.
【００６１】また、以上の各実施例では、フォトカプラ
にフォト・トランジスタ型の素子を用いているが、これ
に限らず、フォト・ダーリントン・トランジスタ型ある
いはフォト・ＩＣ型等の素子を用いることができる。In each of the above embodiments, the phototransistor type element is used for the photocoupler, but the invention is not limited to this, and a photo darlington transistor type or photo IC type element may be used. it can.
【００６２】また、以上の各実施例は“復調手段”に倍
電圧整流回路形の包絡線検波回路を用いているが、復調
手段として適宜の復調回路を用いることができ、たとえ
ば本出願人の出願にかかる特願平５−２１３８９号明細
書に記載のフェールセーフ検波回路を用いる形で実施す
ることができる。Further, in each of the above-mentioned embodiments, the envelope detecting circuit of the voltage doubler rectifying circuit type is used as the "demodulation means", but an appropriate demodulation circuit can be used as the demodulation means. The fail-safe detection circuit described in the specification of Japanese Patent Application No. 5-21389 can be used.
【００６３】[0063]
【発明の効果】以上説明したように、本発明によれば、
包絡線検波回路等の復調手段を介して、論理変数で変調
した変調信号が侵入すると、論理入力に関係なく常に出
力がなくなり、フェイルセーフが実現できる。As described above, according to the present invention,
When a modulation signal modulated by a logic variable enters through a demodulation means such as an envelope detection circuit, the output is always lost regardless of the logic input, and fail safe can be realized.
【図１】 実施例１の回路図FIG. 1 is a circuit diagram of a first embodiment.
【図２】 実施例２の回路図FIG. 2 is a circuit diagram of a second embodiment.
【図３】 実施例３の回路図FIG. 3 is a circuit diagram of a third embodiment.
【図４】 実施例の変形の説明図FIG. 4 is an explanatory diagram of a modification of the embodiment.
【図５】 フェイルセーフ２入力アンドゲート回路の原
理説明図FIG. 5 is an explanatory diagram of the principle of a fail-safe 2-input AND gate circuit.
【図６】 従来例における故障時の動作説明図FIG. 6 is an explanatory diagram of an operation when a failure occurs in the conventional example.
【図７】 ４端子コンデンサの説明図FIG. 7 is an explanatory diagram of a 4-terminal capacitor.
１，９ 変調信号 Ａ，Ｂ 包絡線検波回路 ＰＣ１，ＰＣ２ フォトカプラ 1,9 Modulation signal A, B envelope detection circuit PC1, PC2 Photo coupler
Claims (3)
調した信号を入力する入力端と、この入力端からの信号
を復調する復調手段と、この復調手段の出力により発光
側が付勢されるフォトカプラとを備え、前記所定周波数
を前記フォトカプラの応答不能の周波数としたことを特
徴とするフェイルセーフ論理回路。1. An input end for inputting a signal obtained by modulating a high frequency of a predetermined frequency with a logic variable signal, demodulation means for demodulating the signal from this input end, and a photo whose output side is energized by the output of this demodulation means. A fail-safe logic circuit comprising: a coupler, wherein the predetermined frequency is a frequency at which the photo coupler cannot respond.
理変数信号で夫々変調した第１〜第ｎの変調信号を入力
する第１〜第ｎの入力端子と、この第１〜第ｎの入力端
子からの第１〜第ｎの変調信号を復調する第１〜第ｎの
復調手段と、主検査信号で付勢される主検査信号入力用
フォトカプラトの受光素子と、前記第１の復調回路の出
力端に接続した第１のフォトカプラの発光素子と主検査
信号入力用フォトカプラの受光素子との直列回路と、前
記第ｎの復調回路の出力端に接続した第ｎのフォトカプ
ラの発光素子と第ｎ−１のフォトカプラの受光素子との
直列回路と、前記第ｎのフォトカプラの受光素子の出力
側に接続した出力段復調手段と、この出力段復調手段の
出力端に接続した当該フェイルセーフｎ入力アンドゲー
ト回路の出力端子とを備え、前記第１〜第ｎの検査信号
の周波数を夫々対応する第１〜第ｎのフォトカプラの応
答不能の周波数とし、前記主検査信号の周波数を、主検
査信号入力用フォトカプラおよび前記第１〜第ｎのフォ
トカプラの応答可能な周波数としたことを特徴とするフ
ェイルセーフｎ入力アントゲート回路。2. A first to nth input terminal for inputting first to nth modulation signals obtained by respectively modulating the first to nth inspection signals with first to nth logical variable signals, and the first to nth input terminals. 1st to nth demodulation means for demodulating the 1st to nth modulated signals from the 1st to nth input terminals, and a light receiving element of a photocoupler for inputting a main inspection signal which is energized by the main inspection signal , A series circuit of the light emitting element of the first photocoupler and the light receiving element of the photocoupler for inputting the main inspection signal connected to the output terminal of the first demodulation circuit, and connected to the output terminal of the nth demodulation circuit. A series circuit of a light emitting element of the nth photocoupler and a light receiving element of the (n-1) th photocoupler, an output stage demodulating means connected to the output side of the light receiving element of the nth photocoupler, and this output stage demodulation And an output terminal of the fail-safe n-input AND gate circuit connected to the output terminal of the means. The frequencies of the first to n-th inspection signals are set as the unresponsive frequency of the corresponding first to n-th photo couplers, and the frequency of the main inspection signal is the photo-coupler for inputting the main inspection signal and the A fail-safe n-input anti-gate circuit, characterized in that it has a frequency at which the first to nth photocouplers can respond.
セット信号で夫々変調したトリガ変調信号，リセット変
調信号を入力する第１，第２の入力端子と、この第１，
第２の入力端子から入力したトリガ変調信号，リセット
変調信号を復調する第１，第２の復調手段と、主検査信
号で付勢される第１のフォトカプラの発光素子と、前記
第１の復調手段の出力端に接続した第２のフォトカプラ
の発光素子と前記第１のフォトカプラの受光素子の直列
回路と、第２の復調手段の出力端に接続した第３のフォ
トカプラの発光素子と第４のフォトカプラの発光素子と
第２のフォトカプラの受光素子との直列回路と、前記第
３のフォトカプラの受光素子の出力側に接続した第３の
復調手段と、この第３の復調手段の出力信号を第１の復
調手段の出力側に帰還する帰還手段と、前記第４のフォ
トカプラの受光素子に接続された当該自己保持回路の出
力端子とを備え、前記第１の検査信号の周波数を第２の
フォトカプラの応答不能の周波数とし、前記第２の検査
信号の周波数を第３のフォトカプラの応答不能の周波数
とし、主検査信号の周波数を前記第１〜第４のフォトカ
プラの応答可能な周波数としたことを特徴とするフェイ
ルセーフ自己保持回路。3. A first and second input terminal for inputting a trigger modulation signal and a reset modulation signal, which are obtained by respectively modulating the first and second inspection signals with a trigger signal and a reset signal, and the first and second input terminals.
First and second demodulation means for demodulating the trigger modulation signal and the reset modulation signal input from the second input terminal, the light emitting element of the first photocoupler energized by the main inspection signal, and the first A series circuit of the light emitting element of the second photocoupler and the light receiving element of the first photocoupler connected to the output terminal of the demodulating means, and the light emitting element of the third photocoupler connected to the output terminal of the second demodulating means. And a series circuit of a light emitting element of the fourth photocoupler and a light receiving element of the second photocoupler, a third demodulating means connected to the output side of the light receiving element of the third photocoupler, and the third demodulating means. The first inspection is provided with feedback means for returning the output signal of the demodulation means to the output side of the first demodulation means, and the output terminal of the self-holding circuit connected to the light receiving element of the fourth photocoupler. The frequency of the signal is adjusted by the second photo coupler. An unusable frequency, a frequency of the second inspection signal as an unresponsive frequency of the third photocoupler, and a frequency of the main inspection signal as a responsive frequency of the first to fourth photocouplers. Characteristic fail-safe self-holding circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29685994A JP3396792B2 (en) | 1994-11-30 | 1994-11-30 | Fail-safe logic circuit, fail-safe n-input AND gate circuit, and fail-safe self-holding circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29685994A JP3396792B2 (en) | 1994-11-30 | 1994-11-30 | Fail-safe logic circuit, fail-safe n-input AND gate circuit, and fail-safe self-holding circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08162940A JPH08162940A (en) | 1996-06-21 |
| JP3396792B2 true JP3396792B2 (en) | 2003-04-14 |
Family
ID=17839093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29685994A Expired - Lifetime JP3396792B2 (en) | 1994-11-30 | 1994-11-30 | Fail-safe logic circuit, fail-safe n-input AND gate circuit, and fail-safe self-holding circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3396792B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4729340B2 (en) * | 2005-05-19 | 2011-07-20 | コーセル株式会社 | Power circuit |
| JP2007181355A (en) * | 2005-12-28 | 2007-07-12 | Toshiba Schneider Inverter Corp | Inverter device |
| CN102104319A (en) * | 2011-04-01 | 2011-06-22 | 欧瑞传动电气有限公司 | IGBT drive circuit and control method |
| CN113690083B (en) * | 2021-07-26 | 2023-10-17 | 北京全路通信信号研究设计院集团有限公司 | Small-sized safety AND gate with inherent safety |
-
1994
- 1994-11-30 JP JP29685994A patent/JP3396792B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08162940A (en) | 1996-06-21 |
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