KR20020026098A - Thyristor protection device by gating current detection for serial thyristor circuits - Google Patents

Abstract

PURPOSE: A thyristor protection device by gating current detection for serial thyristor circuits is provided to prevent the abnormal state from spreading to other thyristor by controlling a gating pulse output of all thyristors at the initial abnormality generation. CONSTITUTION: A main controller(10) includes a CPU(Central Processing Unit)(11) for generating a gate control signal of a gate-pulse-string type and a lighting converter(12) for use in the sending for converting the gate control signal generated in the CPU(11) for the fiber cable transmission. A gate actuator(20) includes a lighting converter(21) for use in the reception for receiving the gate pulse string control signal transmitted from the main controller(10) and a gate pulse amplifier(22) for processing an output of the lighting converter(21) to control the gating of plural thyristors. The serial thyristors(SCR1-SCRn) drives a load by controlling a switch on-off operation according to a gate control output of the gate actuator(20).

Description

Thyristor protection device by gating current detection for serial thyristor circuits}

According to the present invention, when an error occurs in any one of a plurality of thyristor elements in a load control series thyristor circuit, it is possible to quickly control the output of gating pulses of all the thyristors to prevent the spread of an abnormal state to another thyristor. The present invention relates to a device protection device by monitoring a gate current in a thyristor series circuit.

Thyristors widely used to control the driving of loads, especially inductive loads, are power control semiconductor devices classified into rectifiers for converting AC into direct current, driving devices for DC motors, and AC power converters. It is the heart of the power conversion system.

In such a power conversion system, the control of the thyristor determines the generation time of the gate signal in the main controller circuit using the CPU and the like to be applied to the gate of the thyristor as a gating signal.

1 shows a configuration of a conventional series thyristor circuit.

As referred to herein, a gate output for thyristor gating is generated for each of the plurality of gate pulse amplifiers (GPA1-GPAn), and each thyristor is driven with each output of these gate pulse amplifiers in series with a series thyristor. The load voltage E2 is applied to the load connected to the motor, that is, the motor M.

Since many thyristors serve to share the capacity of the motor M as a load, it is more economical to apply a single expensive mass thyristor to the same circuit.

The gate pulse amplifiers GPA1-GPAn are configured in the same manner. Specifically, in the circuit configuration of one gate pulse amplifier GPA1, the input voltage E1 is applied to the primary circuit of the impedance matching resistor R1 and the transformer T1 and the series circuit of the driving transistor Q1. And the driving transistor Q1 is configured such that the current of the input voltage flows on the primary side of the transformer while its base input pulse is at a high level, and thus the voltage induced on the secondary side of the transformer is a capacitor ( It is configured to be applied as a gate voltage to one thyristor SCR1 through the rectifying circuit C2) and the diode D1 and the noise absorption circuit by the resistor R3 and the capacitor C3.

At this time, a freewheel circuit by zener diodes ZD1 and ZD2 and an input noise absorbing circuit by resistor R2 and condenser C1 are provided on the input side of transformer T1 so as to maintain reliability in circuit operation.

In such conventional thyristor series circuits, the monitoring for these thyristor protection uses an appropriately fast-acting fuse that can be mounted on an input or output line, and simultaneously detects the current or phase current flowing between each AK of each thyristor. The thyristor is protected by judging whether or not.

However, when the thyristors are connected in series, conventional thyristor protection techniques cannot solve the voltage distribution problem, but also have the disadvantage of slow gate blocking for failure.

For example, if one thyristor is damaged and becomes conductive, the other thyristors are likely to be continuously damaged because the other thyristors have to share the capacity of the failed thyristors. Moreover, such thyristors were difficult to detect in advance.

FIG. 2 shows a saturation voltage versus pressure voltage of each thyristor according to a gate signal in a conventional series thyristor control circuit. In order to monitor the normal status of individual thyristors, when the individual thyristor conducts, the voltage between _AK (V _AK ) is detected and compared with the Vsat voltage (saturation voltage). Since the saturation voltage of the thyristor must be detected on the load voltage supply line of the load line, the burden of dealing with the expensive and high voltage of the detection equipment is increased.

An object of the present invention is to prevent the spread of an abnormal state to other thyristors by controlling the output of all the thyristor gating pulses in the early stage of the abnormality when any one of a plurality of thyristor elements occurs in the load control series thyristor circuit. To provide a device protection device by monitoring the gate current in the thyristor series circuit.

1 is a block diagram of a control circuit of a conventional serial drive thyristor for load driving.

2 is a waveform diagram illustrating a failure determination process using a voltage between the both ends of the thyristor when an abnormality occurs in a conventional thyristor.

3 is a conceptual diagram of a thyristor element protection device according to the present invention.

4 is a detailed circuit diagram of the gate pulse amplifier of the present invention.

Fig. 5 is a detailed circuit diagram of the pulse output limiting circuit provided in the gate pulse amplifier of the present invention.

6A to 6C are output waveform diagrams of respective parts of FIG. 5 according to steady state and abnormal states for each device of the series thyristor.

※ Explanation of symbols about main part of drawing ※

10: main controller 11: CPU

12,21: photoelectric converter 20: gate driver

22: gate pulse amplifier 50: pulse output limiting circuit

60: supervisory circuit 70: filter circuit

80: comparison circuit C1-C4: condenser

D1: diodes E1, E2: input and output voltage

F1: flip-flop G1, G2: gate

M: Motor OP0-OP3: Operational Amplifier

Q1: transistor R1-R12: resistor

SCR1-SCRn: Thyristor ZD1, ZD2: Zener Diode

The present invention for achieving the above object is a transformer for generating a secondary voltage by receiving the input voltage as a primary voltage in accordance with the switching operation of the drive transistor, and the gate of the series thyristor for load driving by rectifying the secondary voltage of the transformer A rectifying circuit for supplying a gating voltage to the side, an impedance matching resistor provided on the primary voltage line of the transformer, and an input variation detecting circuit for differentially amplifying a voltage difference between both ends of the impedance matching resistor to obtain an input voltage variation output; And a pulse output limiting circuit which receives and compares the output of the input fluctuation detecting circuit and the control pulse output of the main controller to determine whether a thyristor abnormal state is detected and to block the transistor driving control pulse output when an abnormality occurs. do.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

3 shows a conceptual circuit block configuration of the apparatus of the present invention. As referred to herein, the main controller 10 including the CPU 11 and the transmission optical converter 12 is configured to generate a pulse for thyristor gate control, and the gate pulse generated by the main controller 10 is generated. The signal (gate pulse train) is configured to be input to the receiving optical converter 21 of the gate driver 20 along the fiber transmission path.

The gate pulse signal output from the receiving optical converter 21 is amplified by the gate pulse amplifier 22 and configured to be provided as a gating signal to each series thyristor SCR1-SCRn. In addition, a voltage detector 30 and a current detector 40 are provided on a series line in which the plurality of series thyristors are connected in series to a load and a power supply voltage terminal, and the signal components detected by the voltage and current detectors are stored in the main controller ( It is configured to reproduce the gate pulse control signal which is fed back to 10) and linked to the load current and voltage state.

4 is a detailed circuit diagram of the gate pulse amplifier 22. As shown in FIG. As referred to herein, the transformer T2 applied to the present invention forms a plurality of secondary coils for one primary coil so that a plurality of gate outputs for a plurality of thyristor gates are generated. This increases the body of the transformer but does not require a second, third transformer, resulting in size reduction and cost reduction of the gate pulse amplifier 22 as a whole.

A plurality of secondary voltages of the transformer T2 are connected in series through a rectifying circuit by the diode D1 and the capacitor C2 and a noise absorption circuit by the resistor R3 and the capacitor C3. Each gate of the thyristors SCR1-SCRn is connected with a gate voltage.

Since the thyristors are connected in series with the load motor M and the load voltage E2 to share the capacity of the load motor M evenly, it is more economical to apply one expensive large capacity thyristor to the same circuit. to be.

An input voltage E1 applied to the input side of the transformer T2 is applied to an impedance matching resistor R1 and a series circuit of the primary coil and the driving transistor Q1 so that the driving transistor Q1 is applied. The current of the input voltage flows to the primary side of the transformer T2 while its base input pulse is high level.

At this time, a freewheel circuit by zener diodes ZD1 and ZD2 and an input noise absorbing circuit by resistor R2 and condenser C1 are provided on the input side of transformer T1 so as to maintain reliability in circuit operation.

On the other hand, when an input current flows through the impedance matching resistor R1, the voltage difference appearing between both ends thereof is differentially amplified by an input voltage detecting circuit composed of an operational amplifier OP0 and resistors R4-R7, thereby detecting an input voltage variation detection signal. (V_Rnew) is generated, and the input voltage fluctuation detection signal of the input voltage detection circuit is processed by the pulse output limiting circuit 50 together with the gate pulse control signal V_GATE output from the main controller to generate the driving transistor Q1. It is configured to be connected to the base side of the power supply by the drive voltage.

5 is a detailed circuit diagram of the pulse output limiting circuit 50. As shown in FIG. As referred to herein, the pulse output limiting circuit amplifies the difference between the input voltage fluctuation detection signal V_Rnew and the gate pulse control signal V_GATE to monitor whether the input fluctuations are the resistance (R8-R10) and the operational amplifier. A monitoring circuit 60 composed of OP1, a filter circuit 70 composed of resistors R11, R12 and a condenser C4 for filtering noise components contained in the output of the monitoring circuit, and the filter circuit. A comparison circuit composed of the first and second operational amplifiers OP2 and OP3 for substituting the rough input variation component value signal to the upper and lower set values Vref_a and Vref_b to compare whether the current detection value exceeds the set value. (80), a NOR gate (G1) for knocking the output values of the first and second operational amplifiers (OP2, OP3) of the comparison circuit, a flip-flop (F1) for latching the output of the NOR gate, ANDing the output of the flip-flop and the gate pulse control signal V_GATE W is composed of the AND gate (G2) for outputting a final pulse output restriction signal.

Referring to the operation of the present invention configured as described above are as follows.

Thyristors, which are widely used in high-capacity power control devices, are driven by the control pulse train generated by the CPU to drive the load. Specifically, as shown in FIG. 3, the gate control signal in the form of a gate pulse string generated by the CPU 11 in the main controller 10 may be connected to the gate driver through the fiber cable and the transmission and reception optical converters 12 and 21. An input is processed to the gate pulse amplifier 22 in 20 to supply a gate voltage to each series thyristor.

At this time, the load voltage E2 is applied to the load side connected in series by the thyristors in series by simultaneous turning on the thyristors in series, and the load is driven.

In addition, the phase voltage and the phase current are picked up by the voltage detector 30 and the current detector 40 on the load driving line, respectively, and provided as a feedback signal to the main controller 10.

The operation of the gate pulse amplifier 22 is as follows.

As shown in FIG. 4, on the primary side of the transformer T2, an input current by switching of the driving transistor Q1, which operates as an output of the pulse output limiting circuit 50, is transferred through an impedance matching resistor R1. When the driving transistor Q1 is turned off, the counter electromotive force is freewheeled by the zener diodes ZD1 and ZD2, and in the input noise absorption circuit by the resistor R2 and the capacitor C1, the noise component included in the input voltage is removed. Will be absorbed.

As the current flows to the primary side of the transformer T2, a plurality of secondary voltages induced on the secondary side are gated to the gate side of each thyristor SCR1-SCRn through a rectifying circuit and a noise absorbing circuit. Is approved.

At this time, the voltage appearing between the both ends of the impedance matching resistor (R1) is changed depending on whether or not the thyristors are abnormal. If any one of a plurality of thyristors is generated, then the secondary output current changes immediately Changes will also occur in the input current. That is, the abnormal state of the thyristors is reflected on the input side as it is, due to the change in the current flowing through the resistor (R1) is a change in the voltage between both ends.

The voltage change between both ends of the resistor R1 is detected by the input variation detection circuit of the operational amplifier OP0 and fed back to the pulse output limiting circuit 50 to be compared with a reference set value. If the detection signal value is greater than or equal to the set variation range, the output of the pulse output limiting circuit 50 is cut off to stop the supply of the gate voltage to each thyristor.

The operation of the pulse output limiting circuit 50 will be described below.

As shown in FIG. 5, the input voltage fluctuation detection signal V_Rnew and the gate pulse control signal V_GATE amplify the difference between the two signals in the monitoring circuit 60 composed of the resistors R8-R10 and the operational amplifier OP1. To monitor input fluctuations.

The input variable component value output of the monitoring circuit 60 passes through the filter circuit 70 composed of the resistors R11 and R12 and the capacitor C4, thereby removing unnecessary noise signals included in the detected component values. This improves the reliability of the circuit operation.

The signal corresponding to the input variation component passed through the filter circuit is input to the inverting terminal (-) and the non-inverting terminal (+) of the first and second operational amplifiers OP2 and OP3 of the comparison circuit 80, respectively. Compared to the magnitudes of the upper and lower set values Vref_a and Vref_b inputted to the opposite polarity terminals of the first and second operational amplifiers OP2 and OP3. This compares and outputs whether the variation of the currently detected input value exceeds a predetermined upper limit or lower limit set value.

The outputs of the first and second operational amplifiers OP2 and OP3 of the comparison circuit 80 are knocked at the NOR gate G1. Therefore, when the input variation exceeds either the upper limit value or the lower limit value, the output of the NOR gate G1 is inverted to invert the input level of the set terminal S of the R-S type flip-flop F1.

When the input level of the set terminal is inverted and input, the R-S flip-flop F1 inverts and outputs the level value of the output terminal Q at the time. The output value of the flip-flop F1 is ANDed together with the gate pulse control signal V_GATE at the AND gate G2, and is output as a final pulse output limit signal for the base drive of the driving transistor Q1.

For example, when the current flowing to the primary side of the gate pulse transformer T2 exceeds the normal range, the output of the RS flip-flop F1 is at a low level, thereby driving the base of the driving transistor Q1 as a switching element. The generation of the signal is interrupted to cut off the supply of the primary voltage (input voltage) of the gate pulse transformer.

6A to 6C show an input waveform and an output waveform of the supervisor circuit 60. FIG. 6A shows each waveform when the thyristors are in a steady state, and FIG. 6B shows the thyristors and gate driving circuits open. Figure 6c shows the waveform of each part of Figure 6c shows the waveform of each part in the case where the thyristors and gate driving circuit is short-circuited.

The present invention can detect and block from the first pulse of the pulse train in which the gate pulses operate, and in the event of an accident in the thyristor or the driving circuit, the primary voltage is cut off immediately to prevent the failure from spreading to the entire thyristor connected in series. do.

As described above, in the load control series thyristor circuit, when an abnormality occurs in any one of a plurality of thyristor elements, the abnormal state propagates to other thyristors by controlling the output of the gating pulses of all the thyristors at an early stage. It has the effect of preventing it from becoming.

Claims (4)

A main controller (10) including a CPU (11) for generating a gate control signal in the form of a gate pulse train and a transmission optical converter (12) for spectively converting the gate control signal generated by the CPU for fiber cable transmission; A receiving optical converter 21 for receiving a gate pulse string control signal converted into an optical signal from the main controller side and a gate pulse amplifier 22 for controlling the gating of a plurality of thyristors by processing the output of the receiving optical converter. A gate driver 20 including; Switch protection device according to the gate current in the thyristor series circuit, characterized in that the switch on / off is collectively controlled in accordance with the gate control output of the gate driver to drive the load. The transformer of claim 1, wherein the gate pulse amplifier 22 receives the input voltage E1 as a primary voltage and generates a secondary voltage according to a switching operation of the driving transistor Q1, and the transformer T2. A rectifying circuit for rectifying the secondary voltage of the rectifier and supplying it as a gating voltage to the gate side of the load driving series thyristors (SCR1-SCRn), an impedance matching resistor (R1) provided on the primary voltage line of the transformer, A thyristor abnormal state is determined by comparing an input variation detection circuit that amplifies the voltage difference between the two ends of the impedance matching resistor to obtain an input voltage variation output, and an output of the input variation detection circuit and a control pulse output of the main controller. And a pulse output limiting circuit 50 for blocking the transistor driving control pulse output when an abnormality occurs. Element protection by monitoring the current bit. 3. The device protection device according to claim 2, wherein the input fluctuation detection circuit comprises a differential amplifier circuit using an operational amplifier (OP0) and resistors (R4-R7). 3. The resistor of claim 8, wherein the pulse output limiting circuit amplifies two signal differences between the input voltage change detection signal V_Rnew and the gate pulse control signal V_GATE to monitor whether the input change occurs. A monitoring circuit 60 composed of OP1, a filter circuit 70 composed of resistors R11, R12 and a condenser C4 for filtering noise components contained in the output of the monitoring circuit, and the filter circuit. A comparison circuit composed of first and second operational amplifiers OP2 and OP3 for substituting the rough input variation component value signal to the upper and lower set values Vref_a and Vref_b to compare whether the current detection value exceeds the set value. 80, a NOR gate G1 for knocking the output values of the first and second operational amplifiers OP2 and OP3 of the comparison circuit, a flip-flop F1 for latching the output of the NOR gate, and Final pulse output by ANDing the output of the flip-flop and the gate pulse control signal (V_GATE) An element protection apparatus according to a gate current monitoring in a thyristor series circuit, characterized in that it comprises an end gate (G2) for outputting an output limit signal.