JP3393118B2 - Plasma etching apparatus and method of manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma etching apparatus and a method for manufacturing a semiconductor device, and more particularly to a plasma etching apparatus for ensuring a uniform etching rate on the entire surface of a semiconductor wafer, and a semiconductor device using the etching apparatus. Regarding the method.

[0002]

2. Description of the Related Art FIG. 3A is a front perspective view for explaining the outline of a conventional plasma etching apparatus. 3B is a plan view of the focus ring and the semiconductor wafer shown in FIG. 3A.

As shown in FIG. 3A, a conventional plasma etching apparatus has a processing chamber 12 for performing plasma etching on a semiconductor wafer 10. A lower electrode 14 that holds the semiconductor wafer 10 is disposed inside the processing chamber 12. Inside the lower electrode 14, an electrostatic adsorption electrode that receives a predetermined DC voltage supplied from a DC voltage power source (not shown) and a cathode electrode that receives RF power supplied from an RF power source 16 (both are shown in FIG. (Not shown). The electrostatic attraction electrode generates an electrostatic force by receiving a DC voltage from a DC voltage power supply to generate a semiconductor wafer 1
Hold 0 by adsorption. The cathode electrode is the RF power source 1.
By receiving the RF power from the processing chamber 6,
A magnetic field is generated to generate plasma inside.

The lower electrode 14 is further provided with a cooling gas supply hole (not shown). The cooling gas supply hole is a passage for guiding a cooling gas such as helium supplied from a cooling gas supply mechanism (not shown) to the back surface of the semiconductor wafer 10. The conventional plasma etching apparatus can cool the semiconductor wafer 10 by using the cooling gas supply holes and the cooling gas supply mechanism (cooling mechanism) during execution of plasma etching.

A gas supply unit 18 for introducing an etching gas inside the processing chamber 12 is provided above the processing chamber 12. In the conventional plasma etching apparatus, an etching gas is introduced into the processing chamber 12 by a gas supply unit 18, and an RF power source 16 is used to apply R to the cathode electrode.
By applying F power, plasma is generated inside the processing chamber 12.

The conventional plasma etching apparatus is provided with a focus ring 20 surrounding the outer circumference of the semiconductor wafer 10 on the lower electrode 14. The focus ring 20 has the following conditions regarding the generation and maintenance of plasma.
It is a member that is arranged so as not to differ greatly between the periphery of the semiconductor wafer 10 and the center thereof. The conventional focus ring 20 is formed by incorporating a second ring 24 made of silicon on the inner peripheral side of a first ring 22 made of quartz.

With such a focus ring 20, sudden changes in plasma conditions near the periphery of the semiconductor wafer 10 can be alleviated. Therefore, the focus ring 20 changes the etching rate of the semiconductor wafer 10 to
It is effective in making the entire surface uniform.

[0008]

However, in the conventional plasma etching apparatus, as shown in FIG. 4 , the etching rate near the outermost periphery of the semiconductor wafer 10 cannot be matched with the rate near the center thereof. Here, FIG. 4 is an experimental result showing the nonuniformity of the etching rate in the conventional plasma etching apparatus, the vertical axis thereof represents the etching rate (vertical axis), and the horizontal axis thereof is from the center of the semiconductor wafer. Represents the distance.
Incidentally, in FIG. 4 , data1 and data2 are respectively the first
The measurement result of the test piece and the measurement result of the second test piece are shown.

From the measurement results shown in FIG. 4 , it can be seen that in the conventional plasma etching apparatus, the etching rate of the semiconductor wafer 10 drops sharply near the outermost periphery thereof.
These results are the results when the RF power was 4500 W and the cooling temperature of the semiconductor wafer 10 was −20 ° C. At this time, the temperature of the focus ring 20 was 250 ° C. at the position of the second ring 24 (silicon position), while the temperature of the semiconductor wafer 10 was 100 ° C.

As described above, in the conventional plasma etching apparatus, a large temperature difference occurs at the boundary between the semiconductor wafer 10 and the focus ring 20 during the plasma etching. Such a temperature difference becomes a cause of disturbing the uniformity of the conditions for generating and maintaining plasma. Therefore, in the conventional plasma etching apparatus, it is considered that the above-mentioned temperature difference is one of the reasons why the etching rate is drastically reduced near the outermost periphery of the semiconductor wafer 10.

The present invention has been made to solve the above problems, and suppresses the temperature difference at the boundary between the semiconductor wafer and the focus ring to make the etching rate of the semiconductor wafer substantially uniform over its entire surface. A first object of the present invention is to provide a plasma etching apparatus capable of doing the above. A second object of the present invention is to provide a manufacturing method for manufacturing a semiconductor device using the above plasma etching apparatus.

[0012]

The invention according to claim 1 is
An apparatus for plasma etching a semiconductor wafer in a processing chamber, comprising: an electrostatic attraction electrode for holding the semiconductor wafer; a DC power supply for supplying a DC voltage to the electrostatic attraction electrode; and an electrostatic attraction electrode for the electrostatic attraction electrode. A cooling mechanism for introducing a cooling gas to the back surface of the held semiconductor wafer, an annular focus ring installed along the outer edge of the semiconductor wafer, an etching gas supplied to the processing chamber, and an internal pressure thereof. And a plasma generating mechanism for generating plasma in the processing chamber, wherein the focus ring is a quartz first ring arranged on the outermost peripheral side, and a first ring of the first ring. The third ring includes a second ring made of silicon arranged on the inner side and a third ring arranged on the innermost side so as to overlap the peripheral edge of the semiconductor wafer. , In situations where the plasma inside the processing chamber is occurring, characterized in that it is composed of a predetermined material showing a gradual increase in temperature as compared with silicon.

According to a second aspect of the invention, there is provided the plasma etching apparatus according to the first aspect, wherein the predetermined material forming the third ring is a fluoropolymer.

A third aspect of the invention is the plasma etching apparatus according to the second aspect, wherein the fluoropolymer is Teflon or Vespel (both manufactured by DuPont).

The invention according to claim 4 is the plasma etching apparatus according to any one of claims 1 to 3, wherein the second ring has a thick plate annular portion having a first plate thickness, and A thin plate annular portion having a second plate thickness that is thinner than the first plate thickness, and the bottom surfaces of the thick plate annular portion and the thin plate annular portion form the same surface, and the thick plate annular portion A part is integrally formed so as to be located on the outer peripheral side of the thin plate annular part, and the third ring is arranged on the thin plate annular part so as to contact the inner wall of the thick plate annular part. It is characterized by

The invention according to claim 5 is the plasma etching apparatus according to any one of claims 1 to 4, wherein the third ring has a width of 0.5 mm or more and 2.0 mm or less. Characterize.

According to a sixth aspect of the present invention, there is provided a semiconductor device manufacturing method including a plasma etching step, wherein the plasma etching step is performed by using the plasma etching apparatus according to any one of the first to sixth aspects. It is characterized by being called.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. It should be noted that elements common to each drawing are denoted by the same reference numerals, and redundant description will be omitted.

Embodiment 1. FIG. 1A is a front view showing the structure of the main part of the plasma etching apparatus according to the first embodiment of the present invention. In addition, FIG.
The figure which showed the focus ring 30 and semiconductor wafer 10 shown to (A) by planar view is shown. The plasma etching apparatus of this embodiment has the same configuration as the conventional apparatus (see FIG. 3) except for the structure of the focus ring 30. Therefore, here, the configuration of the focus ring 30 will be mainly described, and the description of the portions of the apparatus of the present embodiment that are the same as those of the conventional apparatus will be omitted or simplified.

As shown in FIGS. 1A and 1B, in this embodiment, the focus ring 30 includes a first ring 32, a second ring 34, and a third ring 36.
Is equipped with. The first ring 32 is made of quartz and is arranged on the outermost periphery of the focus ring 30. The second ring 34 is made of silicon and is arranged in close contact with the inside of the first ring 32.

The third ring 36 is a main part of the present embodiment, and when subjected to the plasma etching process inside the processing chamber 12, the temperature rising speed (temperature per unit time) lower than that of silicon. It is made of a material showing a rising width). The third ring 36 can be made of, for example, a fluoropolymer, more specifically, Teflon or Vespel manufactured by DuPont (both are trade names).

As shown in FIG. 1A, the third ring 36
Are configured so that a part thereof overlaps the semiconductor wafer 10. That is, the third ring 36 is formed such that the peripheral portion of the semiconductor wafer 10 is located on the third ring. In addition, the third ring 36 is 0.5 mm or more and 2.0.
It is configured to have any width of less than or equal to mm, more preferably 1.0 mm.

As described above, the temperature increase rate of the third ring 36 during the plasma etching process is lower than the temperature increase rate of silicon, that is, the temperature increase rate of the second ring 34. Therefore, according to the plasma etching apparatus of the present embodiment, the focus ring 30
The temperature difference that occurs at the boundary between the semiconductor wafer 10 and the semiconductor wafer 10 can be made smaller than the temperature difference that has conventionally occurred.

For example, when the RF power for generating plasma is 4500 W and the cooling temperature of the semiconductor wafer 10 is −20 ° C., the focus ring 20 (250 ° C.) is used in the conventional plasma etching apparatus as described above. And a temperature difference of 150 ° C. occurs at the boundary between the semiconductor wafer 10 (100 ° C.). On the other hand, in the present embodiment, under the above conditions, the temperature of the third ring 36 is suppressed to about 150 ° C. Therefore, the temperature difference generated at the boundary between the focus ring 30 and the semiconductor wafer 10 is about 50 ° C.

The conditions regarding the generation and maintenance of plasma become more uniform inside the processing chamber 12 as the temperature difference at the boundary between the focus ring 30 and the semiconductor wafer 10 becomes smaller. Therefore, according to the plasma etching apparatus of the present embodiment, it is possible to prevent the etching rate from rapidly decreasing near the peripheral edge of the semiconductor wafer 10 and make the etching rate of the semiconductor wafer 10 substantially uniform over the entire surface. it can.

By the way, by-products are produced as the semiconductor wafer 10 is scraped during the plasma etching. This by-product has a characteristic that it is easily deposited on a site having a relatively low temperature. Therefore, if the third ring 36 having a relatively low temperature has an excessively large width, the third ring 36
There is a disadvantage that the by-products are excessively deposited in the vicinity of the ring 36. On the other hand, if the width of the third ring 36 is unnecessarily narrow, the effect of providing the third ring 36 cannot be obtained.

In the present embodiment, as described above, the width of the third ring 36 is restricted to 0.5 mm or more and 2.0 mm or less. According to the third ring 36 having such a width, it is possible to enhance the uniformity of the etching rate in the processing chamber 12 without causing a substantial problem regarding the deposition of by-products. Therefore, according to the plasma etching apparatus of the present embodiment, it is possible to obtain the effect of improving the uniformity of the etching rate without causing the disadvantage due to the provision of the third ring 36.

Embodiment 2. Next, a second embodiment of the present invention will be described with reference to FIGS. 2 (A) and 2 (B). FIG. 2A is a front view showing the structure of the main part of the plasma etching apparatus according to the second embodiment of the present invention. 2B shows a plan view of the focus ring 40 and the semiconductor wafer 10 shown in FIG. 2A. The plasma etching apparatus of this embodiment has the same configuration as the apparatus of Embodiment 1 except for the structure of the focus ring 40. Therefore, here, only the difference between the focus ring 40 and the focus ring 30 will be described.

As shown in FIG. 2A, the focus ring 40 included in the apparatus of this embodiment is a first ring 42 ,
It is composed of a second ring 44 and a third ring 46 . These rings 42 , 44 , and 46 are each made of quartz, silicon, and a fluoropolymer, as in the case of the first embodiment.

Here, the second ring 44 has a thick plate annular portion 48 having a first plate thickness and a second plate portion thinner than the first plate thickness.
And a thin plate annular portion 50 having a plate thickness of. The thick plate annular portion 48 and the thin plate annular portion 50 are integrally formed such that their bottom surfaces form the same surface, and the thick plate annular portion 48 is located on the outer peripheral side of the thin plate annular portion 50. . Also,
The third ring 46 is arranged on the thin plate annular portion 50 so as to contact the inner wall of the thick plate annular portion 48.

The fluorine-containing polymer forming the third ring 46 and the silicon forming the second ring 44 have electrically different characteristics. The third ring 46 is a component that is not used in the conventional focus ring 20. Therefore, if the third ring 46 is newly used as a constituent element of the focus ring 40, it is considered that the influence of the third ring 46 reaches the semiconductor wafer 10 in some way.

The focus ring 40 is the third ring 46.
By leaving the thin plate annular portion 50 (silicon) of the second ring underneath, the focus ring 3 of the first embodiment
Compared with 0, the same surface state as that of the focus ring 30 is realized while maintaining the configuration close to that of the conventional focus ring 20. Therefore, according to the plasma etching apparatus of the present embodiment, it is possible to obtain the effect related to the uniformization of the etching rate while leaving the effect obtained by the conventional focus ring 20 to a great extent.

As described above, according to the plasma etching apparatus of the first or second embodiment, the uniformity of the etching rate on the semiconductor wafer can be improved. For this reason,
According to the semiconductor manufacturing method using these devices, it is possible to increase the number of effective chips that can be obtained from one semiconductor wafer and increase the yield of semiconductor devices.

[0034]

As described above, according to the plasma etching apparatus of the present invention, the temperature difference at the boundary between the focus ring and the semiconductor wafer can be suppressed, and the uniformity of the etching rate on the semiconductor wafer can be improved. Furthermore, according to the method for manufacturing a semiconductor device of the present invention, the yield of semiconductor devices can be increased by using the above plasma etching apparatus.

[Brief description of drawings]

FIG. 1 is a diagram showing a main part of a plasma etching apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a main part of a plasma etching apparatus according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional plasma etching apparatus.

FIG. 4 is a diagram for explaining a problem of a conventional plasma etching apparatus.

[Explanation of symbols]

10 Semiconductor wafer 12 Processing room 14 Lower electrode 16 RF power supply 18 Gas supply section 30; 40 Focus ring 32; 42 1st ring 34; 44 second ring 36; 46 Third Ring 48 thick plate annular part 50 Thin plate annular part

Claims (6)

(57) [Claims] 1. An apparatus for performing plasma etching on a semiconductor wafer in a processing chamber, comprising: an electrostatic attraction electrode for holding the semiconductor wafer; a DC power supply for supplying a DC voltage to the electrostatic attraction electrode; A cooling mechanism for introducing a cooling gas to the back surface of the semiconductor wafer held by the electrostatic attraction electrode, an annular focus ring installed along the outer edge of the semiconductor wafer, and an etching gas supplied to the processing chamber. Together with a gas supply system that controls the internal pressure thereof, and a plasma generation mechanism that generates plasma inside the processing chamber, the focus ring is a quartz first ring arranged on the outermost peripheral side, A second ring made of silicon arranged inside the first ring, and a third ring arranged on the innermost side so as to overlap the peripheral edge of the semiconductor wafer. The third ring comprises, under the situation that the plasma inside the processing chamber is occurring,
A plasma etching apparatus comprising a predetermined material that exhibits a gradual temperature rise compared to silicon. 2. The predetermined material forming the third ring is
The plasma etching apparatus according to claim 1, wherein the plasma etching apparatus is a fluoropolymer. 3. The plasma etching apparatus according to claim 2, wherein the fluoropolymer is Teflon or Vespel (both manufactured by DuPont). 4. The second ring comprises a thick plate annular portion having a first plate thickness and a thin plate annular portion having a second plate thickness that is thinner than the first plate thickness, The plate annular portion and the thin plate annular portion are integrally formed such that their bottom surfaces form the same surface, and the thick plate annular portion is located on the outer peripheral side of the thin plate annular portion, and the third 4. The plasma etching apparatus according to claim 1, wherein the ring is arranged on the thin plate annular portion so as to be in contact with the inner wall of the thick plate annular portion. 5. The third ring is 0.5 mm or more and 2.0 or more.
The plasma etching apparatus according to claim 1, wherein the plasma etching apparatus has a width of not more than mm. 6. A method of manufacturing a semiconductor device including a plasma etching step, wherein the plasma etching step is performed by using the plasma etching apparatus according to any one of claims 1 to 6. Production method.